workbench/devs/networks/e1000/e1000_manage.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include "e1000_api.h"
  30
  31 static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
  32
  33 /**
  34  *  e1000_calculate_checksum - Calculate checksum for buffer
  35  *  @buffer: pointer to EEPROM
  36  *  @length: size of EEPROM to calculate a checksum for
  37  *
  38  *  Calculates the checksum for some buffer on a specified length.  The
  39  *  checksum calculated is returned.
  40  **/
  41 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
  42 {
  43         u32 i;
  44         u8  sum = 0;
  45
  46         DEBUGFUNC("e1000_calculate_checksum");
  47
  48         if (!buffer)
  49                 return 0;
  50
  51         for (i = 0; i < length; i++)
  52                 sum += buffer[i];
  53
  54         return (u8) (0 - sum);
  55 }
  56
  57 /**
  58  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
  59  *  @hw: pointer to the HW structure
  60  *
  61  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
  62  *
  63  *  This function checks whether the HOST IF is enabled for command operation
  64  *  and also checks whether the previous command is completed.  It busy waits
  65  *  in case of previous command is not completed.
  66  **/
  67 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
  68 {
  69         u32 hicr;
  70         s32 ret_val = E1000_SUCCESS;
  71         u8  i;
  72
  73         DEBUGFUNC("e1000_mng_enable_host_if_generic");
  74
  75         /* Check that the host interface is enabled. */
  76         hicr = E1000_READ_REG(hw, E1000_HICR);
  77         if ((hicr & E1000_HICR_EN) == 0) {
  78                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  79                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
  80                 goto out;
  81         }
  82         /* check the previous command is completed */
  83         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  84                 hicr = E1000_READ_REG(hw, E1000_HICR);
  85                 if (!(hicr & E1000_HICR_C))
  86                         break;
  87                 msec_delay_irq(1);
  88         }
  89
  90         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  91                 DEBUGOUT("Previous command timeout failed .\n");
  92                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
  93                 goto out;
  94         }
  95
  96 out:
  97         return ret_val;
  98 }
  99
 100 /**
 101  *  e1000_check_mng_mode_generic - Generic check management mode
 102  *  @hw: pointer to the HW structure
 103  *
 104  *  Reads the firmware semaphore register and returns true (>0) if
 105  *  manageability is enabled, else false (0).
 106  **/
 107 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
 108 {
 109         u32 fwsm;
 110
 111         DEBUGFUNC("e1000_check_mng_mode_generic");
 112
 113         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 114
 115         return (fwsm & E1000_FWSM_MODE_MASK) ==
 116                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 117 }
 118
 119 /**
 120  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
 121  *  @hw: pointer to the HW structure
 122  *
 123  *  Enables packet filtering on transmit packets if manageability is enabled
 124  *  and host interface is enabled.
 125  **/
 126 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 127 {
 128         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
 129         u32 *buffer = (u32 *)&hw->mng_cookie;
 130         u32 offset;
 131         s32 ret_val, hdr_csum, csum;
 132         u8 i, len;
 133         bool tx_filter = true;
 134
 135         DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
 136
 137         /* No manageability, no filtering */
 138         if (!hw->mac.ops.check_mng_mode(hw)) {
 139                 tx_filter = false;
 140                 goto out;
 141         }
 142
 143         /*
 144          * If we can't read from the host interface for whatever
 145          * reason, disable filtering.
 146          */
 147         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 148         if (ret_val != E1000_SUCCESS) {
 149                 tx_filter = false;
 150                 goto out;
 151         }
 152
 153         /* Read in the header.  Length and offset are in dwords. */
 154         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 155         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 156         for (i = 0; i < len; i++) {
 157                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
 158                                                            E1000_HOST_IF,
 159                                                            offset + i);
 160         }
 161         hdr_csum = hdr->checksum;
 162         hdr->checksum = 0;
 163         csum = e1000_calculate_checksum((u8 *)hdr,
 164                                         E1000_MNG_DHCP_COOKIE_LENGTH);
 165         /*
 166          * If either the checksums or signature don't match, then
 167          * the cookie area isn't considered valid, in which case we
 168          * take the safe route of assuming Tx filtering is enabled.
 169          */
 170         if (hdr_csum != csum)
 171                 goto out;
 172         if (hdr->signature != E1000_IAMT_SIGNATURE)
 173                 goto out;
 174
 175         /* Cookie area is valid, make the final check for filtering. */
 176         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
 177                 tx_filter = false;
 178
 179 out:
 180         hw->mac.tx_pkt_filtering = tx_filter;
 181         return tx_filter;
 182 }
 183
 184 /**
 185  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
 186  *  @hw: pointer to the HW structure
 187  *  @buffer: pointer to the host interface
 188  *  @length: size of the buffer
 189  *
 190  *  Writes the DHCP information to the host interface.
 191  **/
 192 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
 193                                       u16 length)
 194 {
 195         struct e1000_host_mng_command_header hdr;
 196         s32 ret_val;
 197         u32 hicr;
 198
 199         DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
 200
 201         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
 202         hdr.command_length = length;
 203         hdr.reserved1 = 0;
 204         hdr.reserved2 = 0;
 205         hdr.checksum = 0;
 206
 207         /* Enable the host interface */
 208         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 209         if (ret_val)
 210                 goto out;
 211
 212         /* Populate the host interface with the contents of "buffer". */
 213         ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
 214                                           sizeof(hdr), &(hdr.checksum));
 215         if (ret_val)
 216                 goto out;
 217
 218         /* Write the manageability command header */
 219         ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
 220         if (ret_val)
 221                 goto out;
 222
 223         /* Tell the ARC a new command is pending. */
 224         hicr = E1000_READ_REG(hw, E1000_HICR);
 225         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 226
 227 out:
 228         return ret_val;
 229 }
 230
 231 /**
 232  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
 233  *  @hw: pointer to the HW structure
 234  *  @hdr: pointer to the host interface command header
 235  *
 236  *  Writes the command header after does the checksum calculation.
 237  **/
 238 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
 239                                     struct e1000_host_mng_command_header *hdr)
 240 {
 241         u16 i, length = sizeof(struct e1000_host_mng_command_header);
 242
 243         DEBUGFUNC("e1000_mng_write_cmd_header_generic");
 244
 245         /* Write the whole command header structure with new checksum. */
 246
 247         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
 248
 249         length >>= 2;
 250         /* Write the relevant command block into the ram area. */
 251         for (i = 0; i < length; i++) {
 252                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 253                                             *((u32 *) hdr + i));
 254                 E1000_WRITE_FLUSH(hw);
 255         }
 256
 257         return E1000_SUCCESS;
 258 }
 259
 260 /**
 261  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
 262  *  @hw: pointer to the HW structure
 263  *  @buffer: pointer to the host interface buffer
 264  *  @length: size of the buffer
 265  *  @offset: location in the buffer to write to
 266  *  @sum: sum of the data (not checksum)
 267  *
 268  *  This function writes the buffer content at the offset given on the host if.
 269  *  It also does alignment considerations to do the writes in most efficient
 270  *  way.  Also fills up the sum of the buffer in *buffer parameter.
 271  **/
 272 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
 273                                     u16 length, u16 offset, u8 *sum)
 274 {
 275         u8 *tmp;
 276         u8 *bufptr = buffer;
 277         u32 data = 0;
 278         s32 ret_val = E1000_SUCCESS;
 279         u16 remaining, i, j, prev_bytes;
 280
 281         DEBUGFUNC("e1000_mng_host_if_write_generic");
 282
 283         /* sum = only sum of the data and it is not checksum */
 284
 285         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
 286                 ret_val = -E1000_ERR_PARAM;
 287                 goto out;
 288         }
 289
 290         tmp = (u8 *)&data;
 291         prev_bytes = offset & 0x3;
 292         offset >>= 2;
 293
 294         if (prev_bytes) {
 295                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
 296                 for (j = prev_bytes; j < sizeof(u32); j++) {
 297                         *(tmp + j) = *bufptr++;
 298                         *sum += *(tmp + j);
 299                 }
 300                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
 301                 length -= j - prev_bytes;
 302                 offset++;
 303         }
 304
 305         remaining = length & 0x3;
 306         length -= remaining;
 307
 308         /* Calculate length in DWORDs */
 309         length >>= 2;
 310
 311         /*
 312          * The device driver writes the relevant command block into the
 313          * ram area.
 314          */
 315         for (i = 0; i < length; i++) {
 316                 for (j = 0; j < sizeof(u32); j++) {
 317                         *(tmp + j) = *bufptr++;
 318                         *sum += *(tmp + j);
 319                 }
 320
 321                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 322                                             data);
 323         }
 324         if (remaining) {
 325                 for (j = 0; j < sizeof(u32); j++) {
 326                         if (j < remaining)
 327                                 *(tmp + j) = *bufptr++;
 328                         else
 329                                 *(tmp + j) = 0;
 330
 331                         *sum += *(tmp + j);
 332                 }
 333                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
 334         }
 335
 336 out:
 337         return ret_val;
 338 }
 339
 340 /**
 341  *  e1000_enable_mng_pass_thru - Enable processing of ARP's
 342  *  @hw: pointer to the HW structure
 343  *
 344  *  Verifies the hardware needs to allow ARPs to be processed by the host.
 345  **/
 346 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 347 {
 348         u32 manc;
 349         u32 fwsm, factps;
 350         bool ret_val = false;
 351
 352         DEBUGFUNC("e1000_enable_mng_pass_thru");
 353
 354         if (!hw->mac.asf_firmware_present)
 355                 goto out;
 356
 357         manc = E1000_READ_REG(hw, E1000_MANC);
 358
 359         if (!(manc & E1000_MANC_RCV_TCO_EN) ||
 360             !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
 361                 goto out;
 362
 363         if (hw->mac.arc_subsystem_valid) {
 364                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 365                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 366
 367                 if (!(factps & E1000_FACTPS_MNGCG) &&
 368                     ((fwsm & E1000_FWSM_MODE_MASK) ==
 369                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
 370                         ret_val = true;
 371                         goto out;
 372                 }
 373         } else {
 374                 if ((manc & E1000_MANC_SMBUS_EN) &&
 375                     !(manc & E1000_MANC_ASF_EN)) {
 376                         ret_val = true;
 377                         goto out;
 378                 }
 379         }
 380
 381 out:
 382         return ret_val;
 383 }
 384