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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / e1000 / e1000_phy.c
blobad9f6bcd6801a5a73097ce0069e3fb14ba58aa62
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000_api.h"
30
31 /* Cable length tables */
32 static const u16 e1000_m88_cable_length_table[] =
33 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
34 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
35 (sizeof(e1000_m88_cable_length_table) / \
36 sizeof(e1000_m88_cable_length_table[0]))
37
38 static const u16 e1000_igp_2_cable_length_table[] =
39 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
40 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
41 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
42 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
43 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
44 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
45 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
46 104, 109, 114, 118, 121, 124};
47 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_igp_2_cable_length_table) / \
49 sizeof(e1000_igp_2_cable_length_table[0]))
50
51 /**
52 * e1000_init_phy_ops_generic - Initialize PHY function pointers
53 * @hw: pointer to the HW structure
54 *
55 * Setups up the function pointers to no-op functions
56 **/
57 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
58 {
59 struct e1000_phy_info *phy = &hw->phy;
60 DEBUGFUNC("e1000_init_phy_ops_generic");
61
62 /* Initialize function pointers */
63 phy->ops.init_params = e1000_null_ops_generic;
64 phy->ops.acquire = e1000_null_ops_generic;
65 phy->ops.check_polarity = e1000_null_ops_generic;
66 phy->ops.check_reset_block = e1000_null_ops_generic;
67 phy->ops.commit = e1000_null_ops_generic;
68 phy->ops.force_speed_duplex = e1000_null_ops_generic;
69 phy->ops.get_cfg_done = e1000_null_ops_generic;
70 phy->ops.get_cable_length = e1000_null_ops_generic;
71 phy->ops.get_info = e1000_null_ops_generic;
72 phy->ops.read_reg = e1000_null_read_reg;
73 phy->ops.release = e1000_null_phy_generic;
74 phy->ops.reset = e1000_null_ops_generic;
75 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
76 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
77 phy->ops.write_reg = e1000_null_write_reg;
78 phy->ops.power_up = e1000_null_phy_generic;
79 phy->ops.power_down = e1000_null_phy_generic;
80 }
81
82 /**
83 * e1000_null_read_reg - No-op function, return 0
84 * @hw: pointer to the HW structure
85 **/
86 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
87 {
88 DEBUGFUNC("e1000_null_read_reg");
89 return E1000_SUCCESS;
90 }
91
92 /**
93 * e1000_null_phy_generic - No-op function, return void
94 * @hw: pointer to the HW structure
95 **/
96 void e1000_null_phy_generic(struct e1000_hw *hw)
97 {
98 DEBUGFUNC("e1000_null_phy_generic");
99 return;
100 }
101
102 /**
103 * e1000_null_lplu_state - No-op function, return 0
104 * @hw: pointer to the HW structure
105 **/
106 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
107 {
108 DEBUGFUNC("e1000_null_lplu_state");
109 return E1000_SUCCESS;
110 }
111
112 /**
113 * e1000_null_write_reg - No-op function, return 0
114 * @hw: pointer to the HW structure
115 **/
116 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
117 {
118 DEBUGFUNC("e1000_null_write_reg");
119 return E1000_SUCCESS;
120 }
121
122 /**
123 * e1000_check_reset_block_generic - Check if PHY reset is blocked
124 * @hw: pointer to the HW structure
125 *
126 * Read the PHY management control register and check whether a PHY reset
127 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
128 * return E1000_BLK_PHY_RESET (12).
129 **/
130 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
131 {
132 u32 manc;
133
134 DEBUGFUNC("e1000_check_reset_block");
135
136 manc = E1000_READ_REG(hw, E1000_MANC);
137
138 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
139 E1000_BLK_PHY_RESET : E1000_SUCCESS;
140 }
141
142 /**
143 * e1000_get_phy_id - Retrieve the PHY ID and revision
144 * @hw: pointer to the HW structure
145 *
146 * Reads the PHY registers and stores the PHY ID and possibly the PHY
147 * revision in the hardware structure.
148 **/
149 s32 e1000_get_phy_id(struct e1000_hw *hw)
150 {
151 struct e1000_phy_info *phy = &hw->phy;
152 s32 ret_val = E1000_SUCCESS;
153 u16 phy_id;
154
155 DEBUGFUNC("e1000_get_phy_id");
156
157 if (!(phy->ops.read_reg))
158 goto out;
159
160 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
161 if (ret_val)
162 goto out;
163
164 phy->id = (u32)(phy_id << 16);
165 usec_delay(20);
166 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
167 if (ret_val)
168 goto out;
169
170 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
171 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
172
173 out:
174 return ret_val;
175 }
176
177 /**
178 * e1000_phy_reset_dsp_generic - Reset PHY DSP
179 * @hw: pointer to the HW structure
180 *
181 * Reset the digital signal processor.
182 **/
183 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
184 {
185 s32 ret_val = E1000_SUCCESS;
186
187 DEBUGFUNC("e1000_phy_reset_dsp_generic");
188
189 if (!(hw->phy.ops.write_reg))
190 goto out;
191
192 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
193 if (ret_val)
194 goto out;
195
196 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
197
198 out:
199 return ret_val;
200 }
201
202 /**
203 * e1000_read_phy_reg_mdic - Read MDI control register
204 * @hw: pointer to the HW structure
205 * @offset: register offset to be read
206 * @data: pointer to the read data
207 *
208 * Reads the MDI control register in the PHY at offset and stores the
209 * information read to data.
210 **/
211 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
212 {
213 struct e1000_phy_info *phy = &hw->phy;
214 u32 i, mdic = 0;
215 s32 ret_val = E1000_SUCCESS;
216
217 DEBUGFUNC("e1000_read_phy_reg_mdic");
218
219 /*
220 * Set up Op-code, Phy Address, and register offset in the MDI
221 * Control register. The MAC will take care of interfacing with the
222 * PHY to retrieve the desired data.
223 */
224 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
225 (phy->addr << E1000_MDIC_PHY_SHIFT) |
226 (E1000_MDIC_OP_READ));
227
228 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
229
230 /*
231 * Poll the ready bit to see if the MDI read completed
232 * Increasing the time out as testing showed failures with
233 * the lower time out
234 */
235 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
236 usec_delay(50);
237 mdic = E1000_READ_REG(hw, E1000_MDIC);
238 if (mdic & E1000_MDIC_READY)
239 break;
240 }
241 if (!(mdic & E1000_MDIC_READY)) {
242 DEBUGOUT("MDI Read did not complete\n");
243 ret_val = -E1000_ERR_PHY;
244 goto out;
245 }
246 if (mdic & E1000_MDIC_ERROR) {
247 DEBUGOUT("MDI Error\n");
248 ret_val = -E1000_ERR_PHY;
249 goto out;
250 }
251 *data = (u16) mdic;
252
253 out:
254 return ret_val;
255 }
256
257 /**
258 * e1000_write_phy_reg_mdic - Write MDI control register
259 * @hw: pointer to the HW structure
260 * @offset: register offset to write to
261 * @data: data to write to register at offset
262 *
263 * Writes data to MDI control register in the PHY at offset.
264 **/
265 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
266 {
267 struct e1000_phy_info *phy = &hw->phy;
268 u32 i, mdic = 0;
269 s32 ret_val = E1000_SUCCESS;
270
271 DEBUGFUNC("e1000_write_phy_reg_mdic");
272
273 /*
274 * Set up Op-code, Phy Address, and register offset in the MDI
275 * Control register. The MAC will take care of interfacing with the
276 * PHY to retrieve the desired data.
277 */
278 mdic = (((u32)data) |
279 (offset << E1000_MDIC_REG_SHIFT) |
280 (phy->addr << E1000_MDIC_PHY_SHIFT) |
281 (E1000_MDIC_OP_WRITE));
282
283 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
284
285 /*
286 * Poll the ready bit to see if the MDI read completed
287 * Increasing the time out as testing showed failures with
288 * the lower time out
289 */
290 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
291 usec_delay(50);
292 mdic = E1000_READ_REG(hw, E1000_MDIC);
293 if (mdic & E1000_MDIC_READY)
294 break;
295 }
296 if (!(mdic & E1000_MDIC_READY)) {
297 DEBUGOUT("MDI Write did not complete\n");
298 ret_val = -E1000_ERR_PHY;
299 goto out;
300 }
301 if (mdic & E1000_MDIC_ERROR) {
302 DEBUGOUT("MDI Error\n");
303 ret_val = -E1000_ERR_PHY;
304 goto out;
305 }
306
307 out:
308 return ret_val;
309 }
310
311 /**
312 * e1000_read_phy_reg_m88 - Read m88 PHY register
313 * @hw: pointer to the HW structure
314 * @offset: register offset to be read
315 * @data: pointer to the read data
316 *
317 * Acquires semaphore, if necessary, then reads the PHY register at offset
318 * and storing the retrieved information in data. Release any acquired
319 * semaphores before exiting.
320 **/
321 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
322 {
323 s32 ret_val = E1000_SUCCESS;
324
325 DEBUGFUNC("e1000_read_phy_reg_m88");
326
327 if (!(hw->phy.ops.acquire))
328 goto out;
329
330 ret_val = hw->phy.ops.acquire(hw);
331 if (ret_val)
332 goto out;
333
334 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
335 data);
336
337 hw->phy.ops.release(hw);
338
339 out:
340 return ret_val;
341 }
342
343 /**
344 * e1000_write_phy_reg_m88 - Write m88 PHY register
345 * @hw: pointer to the HW structure
346 * @offset: register offset to write to
347 * @data: data to write at register offset
348 *
349 * Acquires semaphore, if necessary, then writes the data to PHY register
350 * at the offset. Release any acquired semaphores before exiting.
351 **/
352 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
353 {
354 s32 ret_val = E1000_SUCCESS;
355
356 DEBUGFUNC("e1000_write_phy_reg_m88");
357
358 if (!(hw->phy.ops.acquire))
359 goto out;
360
361 ret_val = hw->phy.ops.acquire(hw);
362 if (ret_val)
363 goto out;
364
365 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
366 data);
367
368 hw->phy.ops.release(hw);
369
370 out:
371 return ret_val;
372 }
373
374 /**
375 * e1000_read_phy_reg_igp - Read igp PHY register
376 * @hw: pointer to the HW structure
377 * @offset: register offset to be read
378 * @data: pointer to the read data
379 *
380 * Acquires semaphore, if necessary, then reads the PHY register at offset
381 * and storing the retrieved information in data. Release any acquired
382 * semaphores before exiting.
383 **/
384 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
385 {
386 s32 ret_val = E1000_SUCCESS;
387
388 DEBUGFUNC("e1000_read_phy_reg_igp");
389
390 if (!(hw->phy.ops.acquire))
391 goto out;
392
393 ret_val = hw->phy.ops.acquire(hw);
394 if (ret_val)
395 goto out;
396
397 if (offset > MAX_PHY_MULTI_PAGE_REG) {
398 ret_val = e1000_write_phy_reg_mdic(hw,
399 IGP01E1000_PHY_PAGE_SELECT,
400 (u16)offset);
401 if (ret_val) {
402 hw->phy.ops.release(hw);
403 goto out;
404 }
405 }
406
407 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
408 data);
409
410 hw->phy.ops.release(hw);
411
412 out:
413 return ret_val;
414 }
415
416 /**
417 * e1000_write_phy_reg_igp - Write igp PHY register
418 * @hw: pointer to the HW structure
419 * @offset: register offset to write to
420 * @data: data to write at register offset
421 *
422 * Acquires semaphore, if necessary, then writes the data to PHY register
423 * at the offset. Release any acquired semaphores before exiting.
424 **/
425 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
426 {
427 s32 ret_val = E1000_SUCCESS;
428
429 DEBUGFUNC("e1000_write_phy_reg_igp");
430
431 if (!(hw->phy.ops.acquire))
432 goto out;
433
434 ret_val = hw->phy.ops.acquire(hw);
435 if (ret_val)
436 goto out;
437
438 if (offset > MAX_PHY_MULTI_PAGE_REG) {
439 ret_val = e1000_write_phy_reg_mdic(hw,
440 IGP01E1000_PHY_PAGE_SELECT,
441 (u16)offset);
442 if (ret_val) {
443 hw->phy.ops.release(hw);
444 goto out;
445 }
446 }
447
448 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
449 data);
450
451 hw->phy.ops.release(hw);
452
453 out:
454 return ret_val;
455 }
456
457 /**
458 * e1000_read_kmrn_reg_generic - Read kumeran register
459 * @hw: pointer to the HW structure
460 * @offset: register offset to be read
461 * @data: pointer to the read data
462 *
463 * Acquires semaphore, if necessary. Then reads the PHY register at offset
464 * using the kumeran interface. The information retrieved is stored in data.
465 * Release any acquired semaphores before exiting.
466 **/
467 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
468 {
469 u32 kmrnctrlsta;
470 s32 ret_val = E1000_SUCCESS;
471
472 DEBUGFUNC("e1000_read_kmrn_reg_generic");
473
474 if (!(hw->phy.ops.acquire))
475 goto out;
476
477 ret_val = hw->phy.ops.acquire(hw);
478 if (ret_val)
479 goto out;
480
481 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
482 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
483 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
484
485 usec_delay(2);
486
487 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
488 *data = (u16)kmrnctrlsta;
489
490 hw->phy.ops.release(hw);
491
492 out:
493 return ret_val;
494 }
495
496 /**
497 * e1000_write_kmrn_reg_generic - Write kumeran register
498 * @hw: pointer to the HW structure
499 * @offset: register offset to write to
500 * @data: data to write at register offset
501 *
502 * Acquires semaphore, if necessary. Then write the data to PHY register
503 * at the offset using the kumeran interface. Release any acquired semaphores
504 * before exiting.
505 **/
506 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
507 {
508 u32 kmrnctrlsta;
509 s32 ret_val = E1000_SUCCESS;
510
511 DEBUGFUNC("e1000_write_kmrn_reg_generic");
512
513 if (!(hw->phy.ops.acquire))
514 goto out;
515
516 ret_val = hw->phy.ops.acquire(hw);
517 if (ret_val)
518 goto out;
519
520 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
521 E1000_KMRNCTRLSTA_OFFSET) | data;
522 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
523
524 usec_delay(2);
525 hw->phy.ops.release(hw);
526
527 out:
528 return ret_val;
529 }
530
531 /**
532 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
533 * @hw: pointer to the HW structure
534 *
535 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
536 * and downshift values are set also.
537 **/
538 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
539 {
540 struct e1000_phy_info *phy = &hw->phy;
541 s32 ret_val;
542 u16 phy_data;
543
544 DEBUGFUNC("e1000_copper_link_setup_m88");
545
546 if (phy->reset_disable) {
547 ret_val = E1000_SUCCESS;
548 goto out;
549 }
550
551 /* Enable CRS on TX. This must be set for half-duplex operation. */
552 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
553 if (ret_val)
554 goto out;
555
556 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
557
558 /*
559 * Options:
560 * MDI/MDI-X = 0 (default)
561 * 0 - Auto for all speeds
562 * 1 - MDI mode
563 * 2 - MDI-X mode
564 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
565 */
566 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
567
568 switch (phy->mdix) {
569 case 1:
570 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
571 break;
572 case 2:
573 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
574 break;
575 case 3:
576 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
577 break;
578 case 0:
579 default:
580 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
581 break;
582 }
583
584 /*
585 * Options:
586 * disable_polarity_correction = 0 (default)
587 * Automatic Correction for Reversed Cable Polarity
588 * 0 - Disabled
589 * 1 - Enabled
590 */
591 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
592 if (phy->disable_polarity_correction == 1)
593 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
594
595 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
596 if (ret_val)
597 goto out;
598
599 if (phy->revision < E1000_REVISION_4) {
600 /*
601 * Force TX_CLK in the Extended PHY Specific Control Register
602 * to 25MHz clock.
603 */
604 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
605 &phy_data);
606 if (ret_val)
607 goto out;
608
609 phy_data |= M88E1000_EPSCR_TX_CLK_25;
610
611 if ((phy->revision == E1000_REVISION_2) &&
612 (phy->id == M88E1111_I_PHY_ID)) {
613 /* 82573L PHY - set the downshift counter to 5x. */
614 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
615 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
616 } else {
617 /* Configure Master and Slave downshift values */
618 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
619 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
620 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
621 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
622 }
623 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
624 phy_data);
625 if (ret_val)
626 goto out;
627 }
628
629 /* Commit the changes. */
630 ret_val = phy->ops.commit(hw);
631 if (ret_val) {
632 DEBUGOUT("Error committing the PHY changes\n");
633 goto out;
634 }
635
636 out:
637 return ret_val;
638 }
639
640 /**
641 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
642 * @hw: pointer to the HW structure
643 *
644 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
645 * igp PHY's.
646 **/
647 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
648 {
649 struct e1000_phy_info *phy = &hw->phy;
650 s32 ret_val;
651 u16 data;
652
653 DEBUGFUNC("e1000_copper_link_setup_igp");
654
655 if (phy->reset_disable) {
656 ret_val = E1000_SUCCESS;
657 goto out;
658 }
659
660 ret_val = hw->phy.ops.reset(hw);
661 if (ret_val) {
662 DEBUGOUT("Error resetting the PHY.\n");
663 goto out;
664 }
665
666 /*
667 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
668 * timeout issues when LFS is enabled.
669 */
670 msec_delay(100);
671
672 /*
673 * The NVM settings will configure LPLU in D3 for
674 * non-IGP1 PHYs.
675 */
676 if (phy->type == e1000_phy_igp) {
677 /* disable lplu d3 during driver init */
678 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
679 if (ret_val) {
680 DEBUGOUT("Error Disabling LPLU D3\n");
681 goto out;
682 }
683 }
684
685 /* disable lplu d0 during driver init */
686 if (hw->phy.ops.set_d0_lplu_state) {
687 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
688 if (ret_val) {
689 DEBUGOUT("Error Disabling LPLU D0\n");
690 goto out;
691 }
692 }
693 /* Configure mdi-mdix settings */
694 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
695 if (ret_val)
696 goto out;
697
698 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
699
700 switch (phy->mdix) {
701 case 1:
702 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
703 break;
704 case 2:
705 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
706 break;
707 case 0:
708 default:
709 data |= IGP01E1000_PSCR_AUTO_MDIX;
710 break;
711 }
712 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
713 if (ret_val)
714 goto out;
715
716 /* set auto-master slave resolution settings */
717 if (hw->mac.autoneg) {
718 /*
719 * when autonegotiation advertisement is only 1000Mbps then we
720 * should disable SmartSpeed and enable Auto MasterSlave
721 * resolution as hardware default.
722 */
723 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
724 /* Disable SmartSpeed */
725 ret_val = phy->ops.read_reg(hw,
726 IGP01E1000_PHY_PORT_CONFIG,
727 &data);
728 if (ret_val)
729 goto out;
730
731 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
732 ret_val = phy->ops.write_reg(hw,
733 IGP01E1000_PHY_PORT_CONFIG,
734 data);
735 if (ret_val)
736 goto out;
737
738 /* Set auto Master/Slave resolution process */
739 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
740 if (ret_val)
741 goto out;
742
743 data &= ~CR_1000T_MS_ENABLE;
744 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
745 if (ret_val)
746 goto out;
747 }
748
749 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
750 if (ret_val)
751 goto out;
752
753 /* load defaults for future use */
754 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
755 ((data & CR_1000T_MS_VALUE) ?
756 e1000_ms_force_master :
757 e1000_ms_force_slave) :
758 e1000_ms_auto;
759
760 switch (phy->ms_type) {
761 case e1000_ms_force_master:
762 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
763 break;
764 case e1000_ms_force_slave:
765 data |= CR_1000T_MS_ENABLE;
766 data &= ~(CR_1000T_MS_VALUE);
767 break;
768 case e1000_ms_auto:
769 data &= ~CR_1000T_MS_ENABLE;
770 default:
771 break;
772 }
773 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
774 if (ret_val)
775 goto out;
776 }
777
778 out:
779 return ret_val;
780 }
781
782 /**
783 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
784 * @hw: pointer to the HW structure
785 *
786 * Performs initial bounds checking on autoneg advertisement parameter, then
787 * configure to advertise the full capability. Setup the PHY to autoneg
788 * and restart the negotiation process between the link partner. If
789 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
790 **/
791 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
792 {
793 struct e1000_phy_info *phy = &hw->phy;
794 s32 ret_val;
795 u16 phy_ctrl;
796
797 DEBUGFUNC("e1000_copper_link_autoneg");
798
799 /*
800 * Perform some bounds checking on the autoneg advertisement
801 * parameter.
802 */
803 phy->autoneg_advertised &= phy->autoneg_mask;
804
805 /*
806 * If autoneg_advertised is zero, we assume it was not defaulted
807 * by the calling code so we set to advertise full capability.
808 */
809 if (phy->autoneg_advertised == 0)
810 phy->autoneg_advertised = phy->autoneg_mask;
811
812 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
813 ret_val = e1000_phy_setup_autoneg(hw);
814 if (ret_val) {
815 DEBUGOUT("Error Setting up Auto-Negotiation\n");
816 goto out;
817 }
818 DEBUGOUT("Restarting Auto-Neg\n");
819
820 /*
821 * Restart auto-negotiation by setting the Auto Neg Enable bit and
822 * the Auto Neg Restart bit in the PHY control register.
823 */
824 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
825 if (ret_val)
826 goto out;
827
828 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
829 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
830 if (ret_val)
831 goto out;
832
833 /*
834 * Does the user want to wait for Auto-Neg to complete here, or
835 * check at a later time (for example, callback routine).
836 */
837 if (phy->autoneg_wait_to_complete) {
838 ret_val = hw->mac.ops.wait_autoneg(hw);
839 if (ret_val) {
840 DEBUGOUT("Error while waiting for "
841 "autoneg to complete\n");
842 goto out;
843 }
844 }
845
846 hw->mac.get_link_status = true;
847
848 out:
849 return ret_val;
850 }
851
852 /**
853 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
854 * @hw: pointer to the HW structure
855 *
856 * Reads the MII auto-neg advertisement register and/or the 1000T control
857 * register and if the PHY is already setup for auto-negotiation, then
858 * return successful. Otherwise, setup advertisement and flow control to
859 * the appropriate values for the wanted auto-negotiation.
860 **/
861 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
862 {
863 struct e1000_phy_info *phy = &hw->phy;
864 s32 ret_val;
865 u16 mii_autoneg_adv_reg;
866 u16 mii_1000t_ctrl_reg = 0;
867
868 DEBUGFUNC("e1000_phy_setup_autoneg");
869
870 phy->autoneg_advertised &= phy->autoneg_mask;
871
872 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
873 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
874 if (ret_val)
875 goto out;
876
877 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
878 /* Read the MII 1000Base-T Control Register (Address 9). */
879 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
880 &mii_1000t_ctrl_reg);
881 if (ret_val)
882 goto out;
883 }
884
885 /*
886 * Need to parse both autoneg_advertised and fc and set up
887 * the appropriate PHY registers. First we will parse for
888 * autoneg_advertised software override. Since we can advertise
889 * a plethora of combinations, we need to check each bit
890 * individually.
891 */
892
893 /*
894 * First we clear all the 10/100 mb speed bits in the Auto-Neg
895 * Advertisement Register (Address 4) and the 1000 mb speed bits in
896 * the 1000Base-T Control Register (Address 9).
897 */
898 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
899 NWAY_AR_100TX_HD_CAPS |
900 NWAY_AR_10T_FD_CAPS |
901 NWAY_AR_10T_HD_CAPS);
902 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
903
904 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
905
906 /* Do we want to advertise 10 Mb Half Duplex? */
907 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
908 DEBUGOUT("Advertise 10mb Half duplex\n");
909 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
910 }
911
912 /* Do we want to advertise 10 Mb Full Duplex? */
913 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
914 DEBUGOUT("Advertise 10mb Full duplex\n");
915 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
916 }
917
918 /* Do we want to advertise 100 Mb Half Duplex? */
919 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
920 DEBUGOUT("Advertise 100mb Half duplex\n");
921 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
922 }
923
924 /* Do we want to advertise 100 Mb Full Duplex? */
925 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
926 DEBUGOUT("Advertise 100mb Full duplex\n");
927 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
928 }
929
930 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
931 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
932 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
933
934 /* Do we want to advertise 1000 Mb Full Duplex? */
935 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
936 DEBUGOUT("Advertise 1000mb Full duplex\n");
937 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
938 }
939
940 /*
941 * Check for a software override of the flow control settings, and
942 * setup the PHY advertisement registers accordingly. If
943 * auto-negotiation is enabled, then software will have to set the
944 * "PAUSE" bits to the correct value in the Auto-Negotiation
945 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
946 * negotiation.
947 *
948 * The possible values of the "fc" parameter are:
949 * 0: Flow control is completely disabled
950 * 1: Rx flow control is enabled (we can receive pause frames
951 * but not send pause frames).
952 * 2: Tx flow control is enabled (we can send pause frames
953 * but we do not support receiving pause frames).
954 * 3: Both Rx and Tx flow control (symmetric) are enabled.
955 * other: No software override. The flow control configuration
956 * in the EEPROM is used.
957 */
958 switch (hw->fc.current_mode) {
959 case e1000_fc_none:
960 /*
961 * Flow control (Rx & Tx) is completely disabled by a
962 * software over-ride.
963 */
964 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
965 break;
966 case e1000_fc_rx_pause:
967 /*
968 * Rx Flow control is enabled, and Tx Flow control is
969 * disabled, by a software over-ride.
970 *
971 * Since there really isn't a way to advertise that we are
972 * capable of Rx Pause ONLY, we will advertise that we
973 * support both symmetric and asymmetric Rx PAUSE. Later
974 * (in e1000_config_fc_after_link_up) we will disable the
975 * hw's ability to send PAUSE frames.
976 */
977 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
978 break;
979 case e1000_fc_tx_pause:
980 /*
981 * Tx Flow control is enabled, and Rx Flow control is
982 * disabled, by a software over-ride.
983 */
984 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
985 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
986 break;
987 case e1000_fc_full:
988 /*
989 * Flow control (both Rx and Tx) is enabled by a software
990 * over-ride.
991 */
992 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
993 break;
994 default:
995 DEBUGOUT("Flow control param set incorrectly\n");
996 ret_val = -E1000_ERR_CONFIG;
997 goto out;
998 }
999
1000 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1001 if (ret_val)
1002 goto out;
1003
1004 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1005
1006 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1007 ret_val = phy->ops.write_reg(hw,
1008 PHY_1000T_CTRL,
1009 mii_1000t_ctrl_reg);
1010 if (ret_val)
1011 goto out;
1012 }
1013
1014 out:
1015 return ret_val;
1016 }
1017
1018 /**
1019 * e1000_setup_copper_link_generic - Configure copper link settings
1020 * @hw: pointer to the HW structure
1021 *
1022 * Calls the appropriate function to configure the link for auto-neg or forced
1023 * speed and duplex. Then we check for link, once link is established calls
1024 * to configure collision distance and flow control are called. If link is
1025 * not established, we return -E1000_ERR_PHY (-2).
1026 **/
1027 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1028 {
1029 s32 ret_val;
1030 bool link;
1031
1032 DEBUGFUNC("e1000_setup_copper_link_generic");
1033
1034 if (hw->mac.autoneg) {
1035 /*
1036 * Setup autoneg and flow control advertisement and perform
1037 * autonegotiation.
1038 */
1039 ret_val = e1000_copper_link_autoneg(hw);
1040 if (ret_val)
1041 goto out;
1042 } else {
1043 /*
1044 * PHY will be set to 10H, 10F, 100H or 100F
1045 * depending on user settings.
1046 */
1047 DEBUGOUT("Forcing Speed and Duplex\n");
1048 ret_val = hw->phy.ops.force_speed_duplex(hw);
1049 if (ret_val) {
1050 DEBUGOUT("Error Forcing Speed and Duplex\n");
1051 goto out;
1052 }
1053 }
1054
1055 /*
1056 * Check link status. Wait up to 100 microseconds for link to become
1057 * valid.
1058 */
1059 ret_val = e1000_phy_has_link_generic(hw,
1060 COPPER_LINK_UP_LIMIT,
1061 10,
1062 &link);
1063 if (ret_val)
1064 goto out;
1065
1066 if (link) {
1067 DEBUGOUT("Valid link established!!!\n");
1068 e1000_config_collision_dist_generic(hw);
1069 ret_val = e1000_config_fc_after_link_up_generic(hw);
1070 } else {
1071 DEBUGOUT("Unable to establish link!!!\n");
1072 }
1073
1074 out:
1075 return ret_val;
1076 }
1077
1078 /**
1079 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1080 * @hw: pointer to the HW structure
1081 *
1082 * Calls the PHY setup function to force speed and duplex. Clears the
1083 * auto-crossover to force MDI manually. Waits for link and returns
1084 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1085 **/
1086 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1087 {
1088 struct e1000_phy_info *phy = &hw->phy;
1089 s32 ret_val;
1090 u16 phy_data;
1091 bool link;
1092
1093 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1094
1095 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1096 if (ret_val)
1097 goto out;
1098
1099 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1100
1101 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1102 if (ret_val)
1103 goto out;
1104
1105 /*
1106 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1107 * forced whenever speed and duplex are forced.
1108 */
1109 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1110 if (ret_val)
1111 goto out;
1112
1113 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1114 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1115
1116 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1117 if (ret_val)
1118 goto out;
1119
1120 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1121
1122 usec_delay(1);
1123
1124 if (phy->autoneg_wait_to_complete) {
1125 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1126
1127 ret_val = e1000_phy_has_link_generic(hw,
1128 PHY_FORCE_LIMIT,
1129 100000,
1130 &link);
1131 if (ret_val)
1132 goto out;
1133
1134 if (!link)
1135 DEBUGOUT("Link taking longer than expected.\n");
1136
1137 /* Try once more */
1138 ret_val = e1000_phy_has_link_generic(hw,
1139 PHY_FORCE_LIMIT,
1140 100000,
1141 &link);
1142 if (ret_val)
1143 goto out;
1144 }
1145
1146 out:
1147 return ret_val;
1148 }
1149
1150 /**
1151 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1152 * @hw: pointer to the HW structure
1153 *
1154 * Calls the PHY setup function to force speed and duplex. Clears the
1155 * auto-crossover to force MDI manually. Resets the PHY to commit the
1156 * changes. If time expires while waiting for link up, we reset the DSP.
1157 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1158 * successful completion, else return corresponding error code.
1159 **/
1160 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1161 {
1162 struct e1000_phy_info *phy = &hw->phy;
1163 s32 ret_val;
1164 u16 phy_data;
1165 bool link;
1166
1167 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1168
1169 /*
1170 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1171 * forced whenever speed and duplex are forced.
1172 */
1173 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1174 if (ret_val)
1175 goto out;
1176
1177 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1179 if (ret_val)
1180 goto out;
1181
1182 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1183
1184 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1185 if (ret_val)
1186 goto out;
1187
1188 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1189
1190 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1191 if (ret_val)
1192 goto out;
1193
1194 /* Reset the phy to commit changes. */
1195 ret_val = hw->phy.ops.commit(hw);
1196 if (ret_val)
1197 goto out;
1198
1199 if (phy->autoneg_wait_to_complete) {
1200 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1201
1202 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1203 100000, &link);
1204 if (ret_val)
1205 goto out;
1206
1207 if (!link) {
1208 /*
1209 * We didn't get link.
1210 * Reset the DSP and cross our fingers.
1211 */
1212 ret_val = phy->ops.write_reg(hw,
1213 M88E1000_PHY_PAGE_SELECT,
1214 0x001d);
1215 if (ret_val)
1216 goto out;
1217 ret_val = e1000_phy_reset_dsp_generic(hw);
1218 if (ret_val)
1219 goto out;
1220 }
1221
1222 /* Try once more */
1223 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1224 100000, &link);
1225 if (ret_val)
1226 goto out;
1227 }
1228
1229 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1230 if (ret_val)
1231 goto out;
1232
1233 /*
1234 * Resetting the phy means we need to re-force TX_CLK in the
1235 * Extended PHY Specific Control Register to 25MHz clock from
1236 * the reset value of 2.5MHz.
1237 */
1238 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1239 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1240 if (ret_val)
1241 goto out;
1242
1243 /*
1244 * In addition, we must re-enable CRS on Tx for both half and full
1245 * duplex.
1246 */
1247 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1248 if (ret_val)
1249 goto out;
1250
1251 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1252 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1253
1254 out:
1255 return ret_val;
1256 }
1257
1258 /**
1259 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1260 * @hw: pointer to the HW structure
1261 * @phy_ctrl: pointer to current value of PHY_CONTROL
1262 *
1263 * Forces speed and duplex on the PHY by doing the following: disable flow
1264 * control, force speed/duplex on the MAC, disable auto speed detection,
1265 * disable auto-negotiation, configure duplex, configure speed, configure
1266 * the collision distance, write configuration to CTRL register. The
1267 * caller must write to the PHY_CONTROL register for these settings to
1268 * take affect.
1269 **/
1270 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1271 {
1272 struct e1000_mac_info *mac = &hw->mac;
1273 u32 ctrl;
1274
1275 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1276
1277 /* Turn off flow control when forcing speed/duplex */
1278 hw->fc.current_mode = e1000_fc_none;
1279
1280 /* Force speed/duplex on the mac */
1281 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1282 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1283 ctrl &= ~E1000_CTRL_SPD_SEL;
1284
1285 /* Disable Auto Speed Detection */
1286 ctrl &= ~E1000_CTRL_ASDE;
1287
1288 /* Disable autoneg on the phy */
1289 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1290
1291 /* Forcing Full or Half Duplex? */
1292 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1293 ctrl &= ~E1000_CTRL_FD;
1294 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1295 DEBUGOUT("Half Duplex\n");
1296 } else {
1297 ctrl |= E1000_CTRL_FD;
1298 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1299 DEBUGOUT("Full Duplex\n");
1300 }
1301
1302 /* Forcing 10mb or 100mb? */
1303 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1304 ctrl |= E1000_CTRL_SPD_100;
1305 *phy_ctrl |= MII_CR_SPEED_100;
1306 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1307 DEBUGOUT("Forcing 100mb\n");
1308 } else {
1309 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1310 *phy_ctrl |= MII_CR_SPEED_10;
1311 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1312 DEBUGOUT("Forcing 10mb\n");
1313 }
1314
1315 e1000_config_collision_dist_generic(hw);
1316
1317 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1318 }
1319
1320 /**
1321 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1322 * @hw: pointer to the HW structure
1323 * @active: boolean used to enable/disable lplu
1324 *
1325 * Success returns 0, Failure returns 1
1326 *
1327 * The low power link up (lplu) state is set to the power management level D3
1328 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1329 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1330 * is used during Dx states where the power conservation is most important.
1331 * During driver activity, SmartSpeed should be enabled so performance is
1332 * maintained.
1333 **/
1334 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1335 {
1336 struct e1000_phy_info *phy = &hw->phy;
1337 s32 ret_val = E1000_SUCCESS;
1338 u16 data;
1339
1340 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1341
1342 if (!(hw->phy.ops.read_reg))
1343 goto out;
1344
1345 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1346 if (ret_val)
1347 goto out;
1348
1349 if (!active) {
1350 data &= ~IGP02E1000_PM_D3_LPLU;
1351 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1352 data);
1353 if (ret_val)
1354 goto out;
1355 /*
1356 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1357 * during Dx states where the power conservation is most
1358 * important. During driver activity we should enable
1359 * SmartSpeed, so performance is maintained.
1360 */
1361 if (phy->smart_speed == e1000_smart_speed_on) {
1362 ret_val = phy->ops.read_reg(hw,
1363 IGP01E1000_PHY_PORT_CONFIG,
1364 &data);
1365 if (ret_val)
1366 goto out;
1367
1368 data |= IGP01E1000_PSCFR_SMART_SPEED;
1369 ret_val = phy->ops.write_reg(hw,
1370 IGP01E1000_PHY_PORT_CONFIG,
1371 data);
1372 if (ret_val)
1373 goto out;
1374 } else if (phy->smart_speed == e1000_smart_speed_off) {
1375 ret_val = phy->ops.read_reg(hw,
1376 IGP01E1000_PHY_PORT_CONFIG,
1377 &data);
1378 if (ret_val)
1379 goto out;
1380
1381 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1382 ret_val = phy->ops.write_reg(hw,
1383 IGP01E1000_PHY_PORT_CONFIG,
1384 data);
1385 if (ret_val)
1386 goto out;
1387 }
1388 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1389 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1390 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1391 data |= IGP02E1000_PM_D3_LPLU;
1392 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1393 data);
1394 if (ret_val)
1395 goto out;
1396
1397 /* When LPLU is enabled, we should disable SmartSpeed */
1398 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1399 &data);
1400 if (ret_val)
1401 goto out;
1402
1403 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1404 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1405 data);
1406 }
1407
1408 out:
1409 return ret_val;
1410 }
1411
1412 /**
1413 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1414 * @hw: pointer to the HW structure
1415 *
1416 * Success returns 0, Failure returns 1
1417 *
1418 * A downshift is detected by querying the PHY link health.
1419 **/
1420 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1421 {
1422 struct e1000_phy_info *phy = &hw->phy;
1423 s32 ret_val;
1424 u16 phy_data, offset, mask;
1425
1426 DEBUGFUNC("e1000_check_downshift_generic");
1427
1428 switch (phy->type) {
1429 case e1000_phy_m88:
1430 case e1000_phy_gg82563:
1431 offset = M88E1000_PHY_SPEC_STATUS;
1432 mask = M88E1000_PSSR_DOWNSHIFT;
1433 break;
1434 case e1000_phy_igp_2:
1435 case e1000_phy_igp:
1436 case e1000_phy_igp_3:
1437 offset = IGP01E1000_PHY_LINK_HEALTH;
1438 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1439 break;
1440 default:
1441 /* speed downshift not supported */
1442 phy->speed_downgraded = false;
1443 ret_val = E1000_SUCCESS;
1444 goto out;
1445 }
1446
1447 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1448
1449 if (!ret_val)
1450 phy->speed_downgraded = (phy_data & mask) ? true : false;
1451
1452 out:
1453 return ret_val;
1454 }
1455
1456 /**
1457 * e1000_check_polarity_m88 - Checks the polarity.
1458 * @hw: pointer to the HW structure
1459 *
1460 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1461 *
1462 * Polarity is determined based on the PHY specific status register.
1463 **/
1464 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1465 {
1466 struct e1000_phy_info *phy = &hw->phy;
1467 s32 ret_val;
1468 u16 data;
1469
1470 DEBUGFUNC("e1000_check_polarity_m88");
1471
1472 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1473
1474 if (!ret_val)
1475 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1476 ? e1000_rev_polarity_reversed
1477 : e1000_rev_polarity_normal;
1478
1479 return ret_val;
1480 }
1481
1482 /**
1483 * e1000_check_polarity_igp - Checks the polarity.
1484 * @hw: pointer to the HW structure
1485 *
1486 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1487 *
1488 * Polarity is determined based on the PHY port status register, and the
1489 * current speed (since there is no polarity at 100Mbps).
1490 **/
1491 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1492 {
1493 struct e1000_phy_info *phy = &hw->phy;
1494 s32 ret_val;
1495 u16 data, offset, mask;
1496
1497 DEBUGFUNC("e1000_check_polarity_igp");
1498
1499 /*
1500 * Polarity is determined based on the speed of
1501 * our connection.
1502 */
1503 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1504 if (ret_val)
1505 goto out;
1506
1507 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1508 IGP01E1000_PSSR_SPEED_1000MBPS) {
1509 offset = IGP01E1000_PHY_PCS_INIT_REG;
1510 mask = IGP01E1000_PHY_POLARITY_MASK;
1511 } else {
1512 /*
1513 * This really only applies to 10Mbps since
1514 * there is no polarity for 100Mbps (always 0).
1515 */
1516 offset = IGP01E1000_PHY_PORT_STATUS;
1517 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1518 }
1519
1520 ret_val = phy->ops.read_reg(hw, offset, &data);
1521
1522 if (!ret_val)
1523 phy->cable_polarity = (data & mask)
1524 ? e1000_rev_polarity_reversed
1525 : e1000_rev_polarity_normal;
1526
1527 out:
1528 return ret_val;
1529 }
1530
1531 /**
1532 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1533 * @hw: pointer to the HW structure
1534 *
1535 * Waits for auto-negotiation to complete or for the auto-negotiation time
1536 * limit to expire, which ever happens first.
1537 **/
1538 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1539 {
1540 s32 ret_val = E1000_SUCCESS;
1541 u16 i, phy_status;
1542
1543 DEBUGFUNC("e1000_wait_autoneg_generic");
1544
1545 if (!(hw->phy.ops.read_reg))
1546 return E1000_SUCCESS;
1547
1548 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1549 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1550 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1551 if (ret_val)
1552 break;
1553 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1554 if (ret_val)
1555 break;
1556 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1557 break;
1558 msec_delay(100);
1559 }
1560
1561 /*
1562 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1563 * has completed.
1564 */
1565 return ret_val;
1566 }
1567
1568 /**
1569 * e1000_phy_has_link_generic - Polls PHY for link
1570 * @hw: pointer to the HW structure
1571 * @iterations: number of times to poll for link
1572 * @usec_interval: delay between polling attempts
1573 * @success: pointer to whether polling was successful or not
1574 *
1575 * Polls the PHY status register for link, 'iterations' number of times.
1576 **/
1577 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1578 u32 usec_interval, bool *success)
1579 {
1580 s32 ret_val = E1000_SUCCESS;
1581 u16 i, phy_status;
1582
1583 DEBUGFUNC("e1000_phy_has_link_generic");
1584
1585 if (!(hw->phy.ops.read_reg))
1586 return E1000_SUCCESS;
1587
1588 for (i = 0; i < iterations; i++) {
1589 /*
1590 * Some PHYs require the PHY_STATUS register to be read
1591 * twice due to the link bit being sticky. No harm doing
1592 * it across the board.
1593 */
1594 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1595 if (ret_val)
1596 break;
1597 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1598 if (ret_val)
1599 break;
1600 if (phy_status & MII_SR_LINK_STATUS)
1601 break;
1602 if (usec_interval >= 1000)
1603 msec_delay_irq(usec_interval/1000);
1604 else
1605 usec_delay(usec_interval);
1606 }
1607
1608 *success = (i < iterations) ? true : false;
1609
1610 return ret_val;
1611 }
1612
1613 /**
1614 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1615 * @hw: pointer to the HW structure
1616 *
1617 * Reads the PHY specific status register to retrieve the cable length
1618 * information. The cable length is determined by averaging the minimum and
1619 * maximum values to get the "average" cable length. The m88 PHY has four
1620 * possible cable length values, which are:
1621 * Register Value Cable Length
1622 * 0 < 50 meters
1623 * 1 50 - 80 meters
1624 * 2 80 - 110 meters
1625 * 3 110 - 140 meters
1626 * 4 > 140 meters
1627 **/
1628 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
1629 {
1630 struct e1000_phy_info *phy = &hw->phy;
1631 s32 ret_val;
1632 u16 phy_data, index;
1633
1634 DEBUGFUNC("e1000_get_cable_length_m88");
1635
1636 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1637 if (ret_val)
1638 goto out;
1639
1640 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1641 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1642 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) {
1643 ret_val = E1000_ERR_PHY;
1644 goto out;
1645 }
1646
1647 phy->min_cable_length = e1000_m88_cable_length_table[index];
1648 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1649
1650 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1651
1652 out:
1653 return ret_val;
1654 }
1655
1656 /**
1657 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1658 * @hw: pointer to the HW structure
1659 *
1660 * The automatic gain control (agc) normalizes the amplitude of the
1661 * received signal, adjusting for the attenuation produced by the
1662 * cable. By reading the AGC registers, which represent the
1663 * combination of coarse and fine gain value, the value can be put
1664 * into a lookup table to obtain the approximate cable length
1665 * for each channel.
1666 **/
1667 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
1668 {
1669 struct e1000_phy_info *phy = &hw->phy;
1670 s32 ret_val = E1000_SUCCESS;
1671 u16 phy_data, i, agc_value = 0;
1672 u16 cur_agc_index, max_agc_index = 0;
1673 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1674 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1675 {IGP02E1000_PHY_AGC_A,
1676 IGP02E1000_PHY_AGC_B,
1677 IGP02E1000_PHY_AGC_C,
1678 IGP02E1000_PHY_AGC_D};
1679
1680 DEBUGFUNC("e1000_get_cable_length_igp_2");
1681
1682 /* Read the AGC registers for all channels */
1683 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1684 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1685 if (ret_val)
1686 goto out;
1687
1688 /*
1689 * Getting bits 15:9, which represent the combination of
1690 * coarse and fine gain values. The result is a number
1691 * that can be put into the lookup table to obtain the
1692 * approximate cable length.
1693 */
1694 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1695 IGP02E1000_AGC_LENGTH_MASK;
1696
1697 /* Array index bound check. */
1698 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1699 (cur_agc_index == 0)) {
1700 ret_val = -E1000_ERR_PHY;
1701 goto out;
1702 }
1703
1704 /* Remove min & max AGC values from calculation. */
1705 if (e1000_igp_2_cable_length_table[min_agc_index] >
1706 e1000_igp_2_cable_length_table[cur_agc_index])
1707 min_agc_index = cur_agc_index;
1708 if (e1000_igp_2_cable_length_table[max_agc_index] <
1709 e1000_igp_2_cable_length_table[cur_agc_index])
1710 max_agc_index = cur_agc_index;
1711
1712 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1713 }
1714
1715 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1716 e1000_igp_2_cable_length_table[max_agc_index]);
1717 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1718
1719 /* Calculate cable length with the error range of +/- 10 meters. */
1720 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1721 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1722 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1723
1724 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1725
1726 out:
1727 return ret_val;
1728 }
1729
1730 /**
1731 * e1000_get_phy_info_m88 - Retrieve PHY information
1732 * @hw: pointer to the HW structure
1733 *
1734 * Valid for only copper links. Read the PHY status register (sticky read)
1735 * to verify that link is up. Read the PHY special control register to
1736 * determine the polarity and 10base-T extended distance. Read the PHY
1737 * special status register to determine MDI/MDIx and current speed. If
1738 * speed is 1000, then determine cable length, local and remote receiver.
1739 **/
1740 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
1741 {
1742 struct e1000_phy_info *phy = &hw->phy;
1743 s32 ret_val;
1744 u16 phy_data;
1745 bool link;
1746
1747 DEBUGFUNC("e1000_get_phy_info_m88");
1748
1749 if (hw->phy.media_type != e1000_media_type_copper) {
1750 DEBUGOUT("Phy info is only valid for copper media\n");
1751 ret_val = -E1000_ERR_CONFIG;
1752 goto out;
1753 }
1754
1755 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1756 if (ret_val)
1757 goto out;
1758
1759 if (!link) {
1760 DEBUGOUT("Phy info is only valid if link is up\n");
1761 ret_val = -E1000_ERR_CONFIG;
1762 goto out;
1763 }
1764
1765 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1766 if (ret_val)
1767 goto out;
1768
1769 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1770 ? true : false;
1771
1772 ret_val = e1000_check_polarity_m88(hw);
1773 if (ret_val)
1774 goto out;
1775
1776 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1777 if (ret_val)
1778 goto out;
1779
1780 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1781
1782 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1783 ret_val = hw->phy.ops.get_cable_length(hw);
1784 if (ret_val)
1785 goto out;
1786
1787 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1788 if (ret_val)
1789 goto out;
1790
1791 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1792 ? e1000_1000t_rx_status_ok
1793 : e1000_1000t_rx_status_not_ok;
1794
1795 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1796 ? e1000_1000t_rx_status_ok
1797 : e1000_1000t_rx_status_not_ok;
1798 } else {
1799 /* Set values to "undefined" */
1800 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1801 phy->local_rx = e1000_1000t_rx_status_undefined;
1802 phy->remote_rx = e1000_1000t_rx_status_undefined;
1803 }
1804
1805 out:
1806 return ret_val;
1807 }
1808
1809 /**
1810 * e1000_get_phy_info_igp - Retrieve igp PHY information
1811 * @hw: pointer to the HW structure
1812 *
1813 * Read PHY status to determine if link is up. If link is up, then
1814 * set/determine 10base-T extended distance and polarity correction. Read
1815 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1816 * determine on the cable length, local and remote receiver.
1817 **/
1818 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
1819 {
1820 struct e1000_phy_info *phy = &hw->phy;
1821 s32 ret_val;
1822 u16 data;
1823 bool link;
1824
1825 DEBUGFUNC("e1000_get_phy_info_igp");
1826
1827 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1828 if (ret_val)
1829 goto out;
1830
1831 if (!link) {
1832 DEBUGOUT("Phy info is only valid if link is up\n");
1833 ret_val = -E1000_ERR_CONFIG;
1834 goto out;
1835 }
1836
1837 phy->polarity_correction = true;
1838
1839 ret_val = e1000_check_polarity_igp(hw);
1840 if (ret_val)
1841 goto out;
1842
1843 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1844 if (ret_val)
1845 goto out;
1846
1847 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1848
1849 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1850 IGP01E1000_PSSR_SPEED_1000MBPS) {
1851 ret_val = hw->phy.ops.get_cable_length(hw);
1852 if (ret_val)
1853 goto out;
1854
1855 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
1856 if (ret_val)
1857 goto out;
1858
1859 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1860 ? e1000_1000t_rx_status_ok
1861 : e1000_1000t_rx_status_not_ok;
1862
1863 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1864 ? e1000_1000t_rx_status_ok
1865 : e1000_1000t_rx_status_not_ok;
1866 } else {
1867 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1868 phy->local_rx = e1000_1000t_rx_status_undefined;
1869 phy->remote_rx = e1000_1000t_rx_status_undefined;
1870 }
1871
1872 out:
1873 return ret_val;
1874 }
1875
1876 /**
1877 * e1000_phy_sw_reset_generic - PHY software reset
1878 * @hw: pointer to the HW structure
1879 *
1880 * Does a software reset of the PHY by reading the PHY control register and
1881 * setting/write the control register reset bit to the PHY.
1882 **/
1883 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1884 {
1885 s32 ret_val = E1000_SUCCESS;
1886 u16 phy_ctrl;
1887
1888 DEBUGFUNC("e1000_phy_sw_reset_generic");
1889
1890 if (!(hw->phy.ops.read_reg))
1891 goto out;
1892
1893 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1894 if (ret_val)
1895 goto out;
1896
1897 phy_ctrl |= MII_CR_RESET;
1898 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1899 if (ret_val)
1900 goto out;
1901
1902 usec_delay(1);
1903
1904 out:
1905 return ret_val;
1906 }
1907
1908 /**
1909 * e1000_phy_hw_reset_generic - PHY hardware reset
1910 * @hw: pointer to the HW structure
1911 *
1912 * Verify the reset block is not blocking us from resetting. Acquire
1913 * semaphore (if necessary) and read/set/write the device control reset
1914 * bit in the PHY. Wait the appropriate delay time for the device to
1915 * reset and release the semaphore (if necessary).
1916 **/
1917 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
1918 {
1919 struct e1000_phy_info *phy = &hw->phy;
1920 s32 ret_val = E1000_SUCCESS;
1921 u32 ctrl;
1922
1923 DEBUGFUNC("e1000_phy_hw_reset_generic");
1924
1925 ret_val = phy->ops.check_reset_block(hw);
1926 if (ret_val) {
1927 ret_val = E1000_SUCCESS;
1928 goto out;
1929 }
1930
1931 ret_val = phy->ops.acquire(hw);
1932 if (ret_val)
1933 goto out;
1934
1935 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1936 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1937 E1000_WRITE_FLUSH(hw);
1938
1939 usec_delay(phy->reset_delay_us);
1940
1941 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1942 E1000_WRITE_FLUSH(hw);
1943
1944 usec_delay(150);
1945
1946 phy->ops.release(hw);
1947
1948 ret_val = phy->ops.get_cfg_done(hw);
1949
1950 out:
1951 return ret_val;
1952 }
1953
1954 /**
1955 * e1000_get_cfg_done_generic - Generic configuration done
1956 * @hw: pointer to the HW structure
1957 *
1958 * Generic function to wait 10 milli-seconds for configuration to complete
1959 * and return success.
1960 **/
1961 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
1962 {
1963 DEBUGFUNC("e1000_get_cfg_done_generic");
1964
1965 msec_delay_irq(10);
1966
1967 return E1000_SUCCESS;
1968 }
1969
1970 /**
1971 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1972 * @hw: pointer to the HW structure
1973 *
1974 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1975 **/
1976 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
1977 {
1978 DEBUGOUT("Running IGP 3 PHY init script\n");
1979
1980 /* PHY init IGP 3 */
1981 /* Enable rise/fall, 10-mode work in class-A */
1982 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
1983 /* Remove all caps from Replica path filter */
1984 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
1985 /* Bias trimming for ADC, AFE and Driver (Default) */
1986 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
1987 /* Increase Hybrid poly bias */
1988 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
1989 /* Add 4% to Tx amplitude in Gig mode */
1990 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
1991 /* Disable trimming (TTT) */
1992 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
1993 /* Poly DC correction to 94.6% + 2% for all channels */
1994 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
1995 /* ABS DC correction to 95.9% */
1996 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
1997 /* BG temp curve trim */
1998 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
1999 /* Increasing ADC OPAMP stage 1 currents to max */
2000 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2001 /* Force 1000 ( required for enabling PHY regs configuration) */
2002 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2003 /* Set upd_freq to 6 */
2004 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2005 /* Disable NPDFE */
2006 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2007 /* Disable adaptive fixed FFE (Default) */
2008 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2009 /* Enable FFE hysteresis */
2010 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2011 /* Fixed FFE for short cable lengths */
2012 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2013 /* Fixed FFE for medium cable lengths */
2014 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2015 /* Fixed FFE for long cable lengths */
2016 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2017 /* Enable Adaptive Clip Threshold */
2018 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2019 /* AHT reset limit to 1 */
2020 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2021 /* Set AHT master delay to 127 msec */
2022 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2023 /* Set scan bits for AHT */
2024 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2025 /* Set AHT Preset bits */
2026 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2027 /* Change integ_factor of channel A to 3 */
2028 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2029 /* Change prop_factor of channels BCD to 8 */
2030 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2031 /* Change cg_icount + enable integbp for channels BCD */
2032 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2033 /*
2034 * Change cg_icount + enable integbp + change prop_factor_master
2035 * to 8 for channel A
2036 */
2037 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2038 /* Disable AHT in Slave mode on channel A */
2039 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2040 /*
2041 * Enable LPLU and disable AN to 1000 in non-D0a states,
2042 * Enable SPD+B2B
2043 */
2044 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2045 /* Enable restart AN on an1000_dis change */
2046 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2047 /* Enable wh_fifo read clock in 10/100 modes */
2048 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2049 /* Restart AN, Speed selection is 1000 */
2050 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2051
2052 return E1000_SUCCESS;
2053 }
2054
2055 /**
2056 * e1000_get_phy_type_from_id - Get PHY type from id
2057 * @phy_id: phy_id read from the phy
2058 *
2059 * Returns the phy type from the id.
2060 **/
2061 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2062 {
2063 enum e1000_phy_type phy_type = e1000_phy_unknown;
2064
2065 switch (phy_id) {
2066 case M88E1000_I_PHY_ID:
2067 case M88E1000_E_PHY_ID:
2068 case M88E1111_I_PHY_ID:
2069 case M88E1011_I_PHY_ID:
2070 phy_type = e1000_phy_m88;
2071 break;
2072 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2073 phy_type = e1000_phy_igp_2;
2074 break;
2075 case GG82563_E_PHY_ID:
2076 phy_type = e1000_phy_gg82563;
2077 break;
2078 case IGP03E1000_E_PHY_ID:
2079 phy_type = e1000_phy_igp_3;
2080 break;
2081 case IFE_E_PHY_ID:
2082 case IFE_PLUS_E_PHY_ID:
2083 case IFE_C_E_PHY_ID:
2084 phy_type = e1000_phy_ife;
2085 break;
2086 default:
2087 phy_type = e1000_phy_unknown;
2088 break;
2089 }
2090 return phy_type;
2091 }
2092
2093 /**
2094 * e1000_determine_phy_address - Determines PHY address.
2095 * @hw: pointer to the HW structure
2096 *
2097 * This uses a trial and error method to loop through possible PHY
2098 * addresses. It tests each by reading the PHY ID registers and
2099 * checking for a match.
2100 **/
2101 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2102 {
2103 s32 ret_val = -E1000_ERR_PHY_TYPE;
2104 u32 phy_addr = 0;
2105 u32 i;
2106 enum e1000_phy_type phy_type = e1000_phy_unknown;
2107
2108 hw->phy.id = phy_type;
2109
2110 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2111 hw->phy.addr = phy_addr;
2112 i = 0;
2113
2114 do {
2115 e1000_get_phy_id(hw);
2116 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2117
2118 /*
2119 * If phy_type is valid, break - we found our
2120 * PHY address
2121 */
2122 if (phy_type != e1000_phy_unknown) {
2123 ret_val = E1000_SUCCESS;
2124 goto out;
2125 }
2126 msec_delay(1);
2127 i++;
2128 } while (i < 10);
2129 }
2130
2131 out:
2132 return ret_val;
2133 }
2134
2135 /**
2136 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2137 * @hw: pointer to the HW structure
2138 *
2139 * In the case of a PHY power down to save power, or to turn off link during a
2140 * driver unload, or wake on lan is not enabled, restore the link to previous
2141 * settings.
2142 **/
2143 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2144 {
2145 u16 mii_reg = 0;
2146
2147 /* The PHY will retain its settings across a power down/up cycle */
2148 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2149 mii_reg &= ~MII_CR_POWER_DOWN;
2150 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2151 }
2152
2153 /**
2154 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2155 * @hw: pointer to the HW structure
2156 *
2157 * In the case of a PHY power down to save power, or to turn off link during a
2158 * driver unload, or wake on lan is not enabled, restore the link to previous
2159 * settings.
2160 **/
2161 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2162 {
2163 u16 mii_reg = 0;
2164
2165 /* The PHY will retain its settings across a power down/up cycle */
2166 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2167 mii_reg |= MII_CR_POWER_DOWN;
2168 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2169 msec_delay(1);
2170 }
Mirror of AROS' svn.