workbench/devs/networks/nForce/nforce.h

   1 #ifndef _NFORCE_H
   2 #define _NFORCE_H
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful, but
  15     WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17     General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22     MA 02111-1307, USA.
  23 */
  24
  25 #include <exec/types.h>
  26 #include <exec/libraries.h>
  27 #include <exec/semaphores.h>
  28 #include <exec/devices.h>
  29 #include <exec/interrupts.h>
  30 #include <dos/bptr.h>
  31
  32 #include <oop/oop.h>
  33
  34 #include <hidd/pci.h>
  35
  36 #include <devices/timer.h>
  37 #include <devices/sana2.h>
  38 #include <devices/sana2specialstats.h>
  39
  40 #include <proto/exec.h>
  41
  42 #include LC_LIBDEFS_FILE
  43
  44 #define NFORCE_TASK_NAME        "NForce task"
  45 #define NFORCE_PORT_NAME        "NForce port"
  46
  47 struct NFBase {
  48     struct Device       nf_Device;
  49     struct MsgPort      *nf_syncport;
  50
  51     OOP_Object          *nf_pci;
  52     OOP_Object          *nf_irq;
  53     OOP_AttrBase        nf_pciDeviceAttrBase;
  54
  55     struct Sana2DeviceQuery nf_Sana2Info;
  56     struct NFUnit       *nf_unit;
  57 };
  58
  59 #undef HiddPCIDeviceAttrBase
  60 #define HiddPCIDeviceAttrBase   (LIBBASE->nf_pciDeviceAttrBase)
  61
  62 enum {
  63     WRITE_QUEUE,
  64     ADOPT_QUEUE,
  65     EVENT_QUEUE,
  66     GENERAL_QUEUE,
  67     REQUEST_QUEUE_COUNT
  68 };
  69
  70 struct Opener
  71 {
  72     struct MinNode  node;
  73     struct MsgPort  read_port;
  74     BOOL            (*rx_function)(APTR, APTR, ULONG);
  75     BOOL            (*tx_function)(APTR, APTR, ULONG);
  76     struct Hook     *filter_hook;
  77     struct MinList  initial_stats;
  78 };
  79
  80 struct TypeStats
  81 {
  82     struct MinNode node;
  83     ULONG packet_type;
  84     struct Sana2PacketTypeStats stats;
  85 };
  86
  87
  88 struct TypeTracker
  89 {
  90     struct MinNode node;
  91     ULONG packet_type;
  92     struct Sana2PacketTypeStats stats;
  93     ULONG user_count;
  94 };
  95
  96
  97 struct AddressRange
  98 {
  99     struct MinNode node;
 100     ULONG add_count;
 101     ULONG lower_bound_left;
 102     ULONG upper_bound_left;
 103     UWORD lower_bound_right;
 104     UWORD upper_bound_right;
 105 };
 106
 107 /* Big endian: should work, but is untested */
 108 struct ring_desc {
 109     IPTR PacketBuffer;
 110     IPTR FlagLen;
 111 };
 112
 113
 114 #define STAT_COUNT 3
 115
 116 struct NFUnit {
 117     struct MinNode          *nu_Node;
 118     struct MinList          nu_Openers;
 119     struct MinList          multicast_ranges;
 120     struct MinList          type_trackers;
 121     ULONG                   nu_UnitNum;
 122     LONG                    range_count;
 123
 124     OOP_Object              *nu_PCIDevice;
 125     OOP_Object              *nu_PCIDriver;
 126
 127     struct timeval          nu_toutPOLL;
 128     BOOL                    nu_toutNEED;
 129     BOOL                    nu_IntsAdded;
 130
 131     struct MsgPort          *nu_TimerSlowPort;
 132     struct timerequest      *nu_TimerSlowReq;
 133
 134     struct MsgPort          *nu_TimerFastPort;
 135     struct timerequest      *nu_TimerFastReq;
 136
 137     struct Sana2DeviceStats stats;
 138     ULONG                   special_stats[STAT_COUNT];
 139
 140     void                    (*initialize)(struct NFUnit *);
 141     void                    (*deinitialize)(struct NFUnit *);
 142     int                     (*start)(struct NFUnit *);
 143     int                     (*stop)(struct NFUnit *);
 144     int                     (*alloc_rx)(struct NFUnit *);
 145     void                    (*set_mac_address)(struct NFUnit *);
 146     void                    (*linkchange)(struct NFUnit *);
 147     void                    (*linkirq)(struct NFUnit *);
 148     ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 149     void                    (*set_multicast)(struct NFUnit *);
 150
 151     int                     open_count;
 152     struct SignalSemaphore  unit_lock;
 153
 154     struct Process          *nu_Process;
 155
 156     struct NFBase           *nu_device;
 157     struct Interrupt        nu_irqhandler;
 158     struct Interrupt        nu_touthandler;
 159     IPTR                        nu_DeviceID;
 160     IPTR                    nu_DriverFlags;
 161     IPTR                    nu_IRQ;
 162     IPTR                    nu_BaseMem;
 163     IPTR                    nu_SizeMem;
 164     IPTR                        nu_BaseIO;
 165
 166     BYTE                    nu_signal_0;
 167     BYTE                    nu_signal_1;
 168     BYTE                    nu_signal_2;
 169     BYTE                    nu_signal_3;
 170
 171     struct MsgPort          *nu_input_port;
 172
 173     struct MsgPort          *request_ports[REQUEST_QUEUE_COUNT];
 174
 175     struct Interrupt        rx_int;
 176     struct Interrupt        tx_int;
 177     struct Interrupt        tx_end_int;
 178
 179     STRPTR                  name;
 180     ULONG                   mtu;
 181     ULONG                   flags;
 182     ULONG                   state;
 183     APTR                    mc_list;
 184     UBYTE                   dev_addr[6];
 185     UBYTE                   org_addr[6];
 186     struct fe_priv          *nu_fe_priv;
 187 };
 188
 189 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 190
 191 /* Media selection options. */
 192 enum {
 193         IF_PORT_UNKNOWN = 0,
 194         IF_PORT_10BASE2,
 195         IF_PORT_10BASET,
 196         IF_PORT_AUI,
 197         IF_PORT_100BASET,
 198         IF_PORT_100BASETX,
 199         IF_PORT_100BASEFX
 200 };
 201
 202 /* These flag bits are private to the generic network queueing
 203  * layer, they may not be explicitly referenced by any other
 204  * code.
 205  */
 206
 207 enum netdev_state_t
 208 {
 209         __LINK_STATE_XOFF=0,
 210         __LINK_STATE_START,
 211         __LINK_STATE_PRESENT,
 212         __LINK_STATE_SCHED,
 213         __LINK_STATE_NOCARRIER,
 214         __LINK_STATE_RX_SCHED,
 215         __LINK_STATE_LINKWATCH_PENDING
 216 };
 217
 218 static inline int test_bit(int nr, const volatile ULONG *addr)
 219 {
 220     return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 221 }
 222
 223 static inline void set_bit(int nr, volatile ULONG *addr)
 224 {
 225     addr[nr >> 5] |= 1UL << (nr & 31);
 226 }
 227
 228 static inline void clear_bit(int nr, volatile ULONG *addr)
 229 {
 230     addr[nr >> 5] &= ~(1UL << (nr & 31));
 231 }
 232
 233 static inline int test_and_set_bit(int nr, volatile ULONG *addr)
 234 {
 235     int oldbit = test_bit(nr, addr);
 236     set_bit(nr, addr);
 237     return oldbit;
 238 }
 239
 240 static inline int test_and_clear_bit(int nr, volatile ULONG *addr)
 241 {
 242     int oldbit = test_bit(nr, addr);
 243     clear_bit(nr, addr);
 244     return oldbit;
 245 }
 246
 247 static inline void netif_schedule(struct NFUnit *dev)
 248 {
 249     if (!test_bit(__LINK_STATE_XOFF, &dev->state)) {
 250         Cause(&dev->tx_int);
 251     }
 252 }
 253
 254
 255 static inline void netif_start_queue(struct NFUnit *dev)
 256 {
 257     clear_bit(__LINK_STATE_XOFF, &dev->state);
 258 }
 259
 260 static inline void netif_wake_queue(struct NFUnit *dev)
 261 {
 262     if (test_and_clear_bit(__LINK_STATE_XOFF, &dev->state)) {
 263         Cause(&dev->tx_int);
 264     }
 265 }
 266
 267 static inline void netif_stop_queue(struct NFUnit *dev)
 268 {
 269     set_bit(__LINK_STATE_XOFF, &dev->state);
 270 }
 271
 272 static inline int netif_queue_stopped(const struct NFUnit *dev)
 273 {
 274     return test_bit(__LINK_STATE_XOFF, &dev->state);
 275 }
 276
 277 static inline int netif_running(const struct NFUnit *dev)
 278 {
 279     return test_bit(__LINK_STATE_START, &dev->state);
 280 }
 281
 282 static inline int netif_carrier_ok(const struct NFUnit *dev)
 283 {
 284     return !test_bit(__LINK_STATE_NOCARRIER, &dev->state);
 285 }
 286
 287 extern void __netdev_watchdog_up(struct NFUnit *dev);
 288
 289 static inline void netif_carrier_on(struct NFUnit *dev)
 290 {
 291     if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->state)) {
 292 //                linkwatch_fire_event(dev);
 293     }
 294     if (netif_running(dev)) {
 295 //                __netdev_watchdog_up(dev);
 296     }
 297 }
 298
 299 static inline void netif_carrier_off(struct NFUnit *dev)
 300 {
 301     if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->state)) {
 302 //                linkwatch_fire_event(dev);
 303     }
 304 }
 305
 306 /* Standard interface flags (netdevice->flags). */
 307 #define IFF_UP          0x1             /* interface is up              */
 308 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 309 #define IFF_DEBUG       0x4             /* turn on debugging            */
 310 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 311 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 312 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 313 #define IFF_RUNNING     0x40            /* resources allocated          */
 314 #define IFF_NOARP       0x80            /* no ARP protocol              */
 315 #define IFF_PROMISC     0x100           /* receive all packets          */
 316 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 317
 318 #define IFF_MASTER      0x400           /* master of a load balancer    */
 319 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 320
 321 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 322
 323 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 324
 325 #define IFF_PORTSEL     0x2000          /* can set media type           */
 326 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 327 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 328 #define IFF_SHARED      0x10000         /* interface may be shared */
 329 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 330
 331 /*
 332  *      We tag multicasts with these structures.
 333  */
 334
 335 #define MAX_ADDR_LEN    32
 336
 337 struct dev_mc_list
 338 {
 339     struct dev_mc_list      *next;
 340     UBYTE                   dmi_addr[MAX_ADDR_LEN];
 341     unsigned char           dmi_addrlen;
 342     int                     dmi_users;
 343     int                     dmi_gusers;
 344 };
 345
 346 struct fe_priv {
 347     struct NFUnit   *pci_dev;
 348     int in_shutdown;
 349     ULONG linkspeed;
 350     int duplex;
 351     int autoneg;
 352     int fixed_mode;
 353     int phyaddr;
 354     int wolenabled;
 355     unsigned int phy_oui;
 356     UWORD gigabit;
 357     ULONG desc_ver;
 358     struct SignalSemaphore  lock;
 359
 360     IPTR ring_addr;
 361     struct eth_frame *rx_buffer;
 362     struct eth_frame *tx_buffer;
 363
 364     struct ring_desc *rx_ring;
 365     ULONG cur_rx, refill_rx;
 366
 367     struct ring_desc *tx_ring;
 368     ULONG next_tx, nic_tx;
 369     ULONG tx_flags;
 370
 371     ULONG irqmask;
 372     ULONG need_linktimer;
 373     struct timeval link_timeout;
 374     ULONG orig_mac[2];
 375 };
 376
 377 #define pci_name(unit)  (unit->name)
 378
 379 /* NFORCE ENET defines */
 380
 381 #define HZ              1000000
 382 #define ETH_DATA_LEN    1500
 383
 384 #define ETH_ADDRESSSIZE 6
 385 #define ETH_HEADERSIZE 14
 386 #define ETH_MTU (ETH_DATA_LEN)
 387 #define ETH_MAXPACKETSIZE ((ETH_HEADERSIZE) + (ETH_MTU))
 388
 389 #define ETH_PACKET_DEST 0
 390 #define ETH_PACKET_SOURCE 6
 391 #define ETH_PACKET_TYPE 12
 392 #define ETH_PACKET_IEEELEN 12
 393 #define ETH_PACKET_SNAPTYPE 20
 394 #define ETH_PACKET_DATA 14
 395
 396 #define NFORCE_MCPNET1_ID       0x01c3
 397 #define NFORCE_MCPNET2_ID       0x0066
 398 #define NFORCE_MCPNET3_ID       0x00d6
 399 #define NFORCE_MCPNET4_ID       0x0086
 400 #define NFORCE_MCPNET5_ID       0x008c
 401 #define NFORCE_MCPNET6_ID       0x00e6
 402 #define NFORCE_MCPNET7_ID       0x00df
 403 #define NFORCE_MCPNET8_ID       0x0056
 404 #define NFORCE_MCPNET9_ID       0x0057
 405 #define NFORCE_MCPNET10_ID      0x0037
 406 #define NFORCE_MCPNET11_ID      0x0038
 407
 408 /*
 409  * Hardware access:
 410  */
 411
 412 #define DEV_NEED_LASTPACKET1    0x0001  /* set LASTPACKET1 in tx flags */
 413 #define DEV_IRQMASK_1           0x0002  /* use NVREG_IRQMASK_WANTED_1 for irq mask */
 414 #define DEV_IRQMASK_2           0x0004  /* use NVREG_IRQMASK_WANTED_2 for irq mask */
 415 #define DEV_NEED_TIMERIRQ       0x0008  /* set the timer irq flag in the irq mask */
 416 #define DEV_NEED_LINKTIMER      0x0010  /* poll link settings. Relies on the timer irq */
 417
 418 enum {
 419         NvRegIrqStatus = 0x000,
 420 #define NVREG_IRQSTAT_MIIEVENT  0x040
 421 #define NVREG_IRQSTAT_MASK              0x1ff
 422         NvRegIrqMask = 0x004,
 423 #define NVREG_IRQ_RX_ERROR              0x0001
 424 #define NVREG_IRQ_RX                    0x0002
 425 #define NVREG_IRQ_RX_NOBUF              0x0004
 426 #define NVREG_IRQ_TX_ERR                0x0008
 427 #define NVREG_IRQ_TX2                   0x0010
 428 #define NVREG_IRQ_TIMER                 0x0020
 429 #define NVREG_IRQ_LINK                  0x0040
 430 #define NVREG_IRQ_TX1                   0x0100
 431 #define NVREG_IRQMASK_WANTED_1          0x005f
 432 #define NVREG_IRQMASK_WANTED_2          0x0147
 433 #define NVREG_IRQ_UNKNOWN               (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
 434
 435         NvRegUnknownSetupReg6 = 0x008,
 436 #define NVREG_UNKSETUP6_VAL             3
 437
 438 /*
 439  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 440  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 441  */
 442         NvRegPollingInterval = 0x00c,
 443 #define NVREG_POLL_DEFAULT      970
 444         NvRegMisc1 = 0x080,
 445 #define NVREG_MISC1_HD          0x02
 446 #define NVREG_MISC1_FORCE       0x3b0f3c
 447
 448         NvRegTransmitterControl = 0x084,
 449 #define NVREG_XMITCTL_START     0x01
 450         NvRegTransmitterStatus = 0x088,
 451 #define NVREG_XMITSTAT_BUSY     0x01
 452
 453         NvRegPacketFilterFlags = 0x8c,
 454 #define NVREG_PFF_ALWAYS        0x7F0008
 455 #define NVREG_PFF_PROMISC       0x80
 456 #define NVREG_PFF_MYADDR        0x20
 457
 458         NvRegOffloadConfig = 0x90,
 459 #define NVREG_OFFLOAD_HOMEPHY   0x601
 460 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 461         NvRegReceiverControl = 0x094,
 462 #define NVREG_RCVCTL_START      0x01
 463         NvRegReceiverStatus = 0x98,
 464 #define NVREG_RCVSTAT_BUSY      0x01
 465
 466         NvRegRandomSeed = 0x9c,
 467 #define NVREG_RNDSEED_MASK      0x00ff
 468 #define NVREG_RNDSEED_FORCE     0x7f00
 469 #define NVREG_RNDSEED_FORCE2    0x2d00
 470 #define NVREG_RNDSEED_FORCE3    0x7400
 471         NvRegUnknownSetupReg1 = 0xA0,
 472 #define NVREG_UNKSETUP1_VAL     0x16070f
 473         NvRegUnknownSetupReg2 = 0xA4,
 474 #define NVREG_UNKSETUP2_VAL     0x16
 475         NvRegMacAddrA = 0xA8,
 476         NvRegMacAddrB = 0xAC,
 477         NvRegMulticastAddrA = 0xB0,
 478 #define NVREG_MCASTADDRA_FORCE  0x01
 479         NvRegMulticastAddrB = 0xB4,
 480         NvRegMulticastMaskA = 0xB8,
 481         NvRegMulticastMaskB = 0xBC,
 482
 483         NvRegPhyInterface = 0xC0,
 484 #define PHY_RGMII               0x10000000
 485
 486         NvRegTxRingPhysAddr = 0x100,
 487         NvRegRxRingPhysAddr = 0x104,
 488         NvRegRingSizes = 0x108,
 489 #define NVREG_RINGSZ_TXSHIFT 0
 490 #define NVREG_RINGSZ_RXSHIFT 16
 491         NvRegUnknownTransmitterReg = 0x10c,
 492         NvRegLinkSpeed = 0x110,
 493 #define NVREG_LINKSPEED_FORCE 0x10000
 494 #define NVREG_LINKSPEED_10      1000
 495 #define NVREG_LINKSPEED_100     100
 496 #define NVREG_LINKSPEED_1000    50
 497 #define NVREG_LINKSPEED_MASK    (0xFFF)
 498         NvRegUnknownSetupReg5 = 0x130,
 499 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 500         NvRegUnknownSetupReg3 = 0x13c,
 501 #define NVREG_UNKSETUP3_VAL1    0x200010
 502         NvRegTxRxControl = 0x144,
 503 #define NVREG_TXRXCTL_KICK      0x0001
 504 #define NVREG_TXRXCTL_BIT1      0x0002
 505 #define NVREG_TXRXCTL_BIT2      0x0004
 506 #define NVREG_TXRXCTL_IDLE      0x0008
 507 #define NVREG_TXRXCTL_RESET     0x0010
 508 #define NVREG_TXRXCTL_RXCHECK   0x0400
 509         NvRegMIIStatus = 0x180,
 510 #define NVREG_MIISTAT_ERROR             0x0001
 511 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 512 #define NVREG_MIISTAT_MASK              0x000f
 513 #define NVREG_MIISTAT_MASK2             0x000f
 514         NvRegUnknownSetupReg4 = 0x184,
 515 #define NVREG_UNKSETUP4_VAL     8
 516
 517         NvRegAdapterControl = 0x188,
 518 #define NVREG_ADAPTCTL_START    0x02
 519 #define NVREG_ADAPTCTL_LINKUP   0x04
 520 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 521 #define NVREG_ADAPTCTL_RUNNING  0x100000
 522 #define NVREG_ADAPTCTL_PHYSHIFT 24
 523         NvRegMIISpeed = 0x18c,
 524 #define NVREG_MIISPEED_BIT8     (1<<8)
 525 #define NVREG_MIIDELAY  5
 526         NvRegMIIControl = 0x190,
 527 #define NVREG_MIICTL_INUSE      0x08000
 528 #define NVREG_MIICTL_WRITE      0x00400
 529 #define NVREG_MIICTL_ADDRSHIFT  5
 530         NvRegMIIData = 0x194,
 531         NvRegWakeUpFlags = 0x200,
 532 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 533 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 534 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 535 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 536 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 537 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 538 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 539 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 540 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 541 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 542 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 543
 544         NvRegPatternCRC = 0x204,
 545         NvRegPatternMask = 0x208,
 546         NvRegPowerCap = 0x268,
 547 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 548 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 549 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 550         NvRegPowerState = 0x26c,
 551 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 552 #define NVREG_POWERSTATE_VALID          0x0100
 553 #define NVREG_POWERSTATE_MASK           0x0003
 554 #define NVREG_POWERSTATE_D0             0x0000
 555 #define NVREG_POWERSTATE_D1             0x0001
 556 #define NVREG_POWERSTATE_D2             0x0002
 557 #define NVREG_POWERSTATE_D3             0x0003
 558 };
 559
 560 #define FLAG_MASK_V1 0xffff0000
 561 #define FLAG_MASK_V2 0xffffc000
 562 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 563 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 564
 565 #define NV_TX_LASTPACKET        (1<<16)
 566 #define NV_TX_RETRYERROR        (1<<19)
 567 #define NV_TX_LASTPACKET1       (1<<24)
 568 #define NV_TX_DEFERRED          (1<<26)
 569 #define NV_TX_CARRIERLOST       (1<<27)
 570 #define NV_TX_LATECOLLISION     (1<<28)
 571 #define NV_TX_UNDERFLOW         (1<<29)
 572 #define NV_TX_ERROR             (1<<30)
 573 #define NV_TX_VALID             (1<<31)
 574
 575 #define NV_TX2_LASTPACKET       (1<<29)
 576 #define NV_TX2_RETRYERROR       (1<<18)
 577 #define NV_TX2_LASTPACKET1      (1<<23)
 578 #define NV_TX2_DEFERRED         (1<<25)
 579 #define NV_TX2_CARRIERLOST      (1<<26)
 580 #define NV_TX2_LATECOLLISION    (1<<27)
 581 #define NV_TX2_UNDERFLOW        (1<<28)
 582 /* error and valid are the same for both */
 583 #define NV_TX2_ERROR            (1<<30)
 584 #define NV_TX2_VALID            (1<<31)
 585
 586 #define NV_RX_DESCRIPTORVALID   (1<<16)
 587 #define NV_RX_MISSEDFRAME       (1<<17)
 588 #define NV_RX_SUBSTRACT1        (1<<18)
 589 #define NV_RX_ERROR1            (1<<23)
 590 #define NV_RX_ERROR2            (1<<24)
 591 #define NV_RX_ERROR3            (1<<25)
 592 #define NV_RX_ERROR4            (1<<26)
 593 #define NV_RX_CRCERR            (1<<27)
 594 #define NV_RX_OVERFLOW          (1<<28)
 595 #define NV_RX_FRAMINGERR        (1<<29)
 596 #define NV_RX_ERROR             (1<<30)
 597 #define NV_RX_AVAIL             (1<<31)
 598
 599 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 600 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 601 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 602 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 603 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 604 #define NV_RX2_SUBSTRACT1       (1<<25)
 605 #define NV_RX2_ERROR1           (1<<18)
 606 #define NV_RX2_ERROR2           (1<<19)
 607 #define NV_RX2_ERROR3           (1<<20)
 608 #define NV_RX2_ERROR4           (1<<21)
 609 #define NV_RX2_CRCERR           (1<<22)
 610 #define NV_RX2_OVERFLOW         (1<<23)
 611 #define NV_RX2_FRAMINGERR       (1<<24)
 612 /* error and avail are the same for both */
 613 #define NV_RX2_ERROR            (1<<30)
 614 #define NV_RX2_AVAIL            (1<<31)
 615
 616 /* Miscelaneous hardware related defines: */
 617 #define NV_PCI_REGSZ            0x270
 618
 619 /* various timeout delays: all in usec */
 620 #define NV_TXRX_RESET_DELAY     4
 621 #define NV_TXSTOP_DELAY1        10
 622 #define NV_TXSTOP_DELAY1MAX     500000
 623 #define NV_TXSTOP_DELAY2        100
 624 #define NV_RXSTOP_DELAY1        10
 625 #define NV_RXSTOP_DELAY1MAX     500000
 626 #define NV_RXSTOP_DELAY2        100
 627 #define NV_SETUP5_DELAY         5
 628 #define NV_SETUP5_DELAYMAX      50000
 629 #define NV_POWERUP_DELAY        5
 630 #define NV_POWERUP_DELAYMAX     5000
 631 #define NV_MIIBUSY_DELAY        50
 632 #define NV_MIIPHY_DELAY 10
 633 #define NV_MIIPHY_DELAYMAX      10000
 634
 635 #define NV_WAKEUPPATTERNS       5
 636 #define NV_WAKEUPMASKENTRIES    4
 637
 638 /* General driver defaults */
 639 #define NV_WATCHDOG_TIMEO       (5*HZ)
 640
 641 #define RX_RING         128
 642 #define TX_RING         64
 643 /*
 644  * If your nic mysteriously hangs then try to reduce the limits
 645  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 646  * last valid ring entry. But this would be impossible to
 647  * implement - probably a disassembly error.
 648  */
 649 #define TX_LIMIT_STOP   63
 650 #define TX_LIMIT_START  62
 651
 652 /* rx/tx mac addr + type + vlan + align + slack*/
 653 #define RX_NIC_BUFSIZE          (ETH_DATA_LEN + 64)
 654 /* even more slack */
 655 //#define RX_ALLOC_BUFSIZE        (ETH_DATA_LEN + 128)
 656 #define RX_ALLOC_BUFSIZE        (ETH_DATA_LEN + 164)
 657
 658 #define OOM_REFILL      (HZ/20)
 659 #define POLL_WAIT       (HZ/100)
 660 #define LINK_TIMEOUT    (3*HZ)
 661
 662 /*
 663  * desc_ver values:
 664  * This field has two purposes:
 665  * - Newer nics uses a different ring layout. The layout is selected by
 666  *   comparing np->desc_ver with DESC_VER_xy.
 667  * - It contains bits that are forced on when writing to NvRegTxRxControl.
 668  */
 669 #define DESC_VER_1      0x0
 670 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
 671
 672 /* PHY defines */
 673 #define PHY_OUI_MARVELL 0x5043
 674 #define PHY_OUI_CICADA  0x03f1
 675 #define PHYID1_OUI_MASK 0x03ff
 676 #define PHYID1_OUI_SHFT 6
 677 #define PHYID2_OUI_MASK 0xfc00
 678 #define PHYID2_OUI_SHFT 10
 679 #define PHY_INIT1       0x0f000
 680 #define PHY_INIT2       0x0e00
 681 #define PHY_INIT3       0x01000
 682 #define PHY_INIT4       0x0200
 683 #define PHY_INIT5       0x0004
 684 #define PHY_INIT6       0x02000
 685 #define PHY_GIGABIT     0x0100
 686
 687 #define PHY_TIMEOUT     0x1
 688 #define PHY_ERROR       0x2
 689
 690 #define PHY_100 0x1
 691 #define PHY_1000        0x2
 692 #define PHY_HALF        0x100
 693
 694 /* FIXME: MII defines that should be added to <linux/mii.h> */
 695 #define MII_1000BT_CR   0x09
 696 #define MII_1000BT_SR   0x0a
 697 #define ADVERTISE_1000FULL      0x0200
 698 #define ADVERTISE_1000HALF      0x0100
 699 #define LPA_1000FULL    0x0800
 700 #define LPA_1000HALF    0x0400
 701
 702 /* MII defines from linux/mii.h */
 703
 704 /* Generic MII registers. */
 705
 706 #define MII_BMCR            0x00        /* Basic mode control register */
 707 #define MII_BMSR            0x01        /* Basic mode status register  */
 708 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
 709 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
 710 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
 711 #define MII_LPA             0x05        /* Link partner ability reg    */
 712 #define MII_EXPANSION       0x06        /* Expansion register          */
 713 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 714 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 715 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
 716 #define MII_RERRCOUNTER     0x15        /* Receive error counter       */
 717 #define MII_SREVISION       0x16        /* Silicon revision            */
 718 #define MII_RESV1           0x17        /* Reserved...                 */
 719 #define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
 720 #define MII_PHYADDR         0x19        /* PHY address                 */
 721 #define MII_RESV2           0x1a        /* Reserved...                 */
 722 #define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
 723 #define MII_NCONFIG         0x1c        /* Network interface config    */
 724
 725 /* Basic mode control register. */
 726 #define BMCR_RESV               0x003f  /* Unused...                   */
 727 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 728 #define BMCR_CTST               0x0080  /* Collision test              */
 729 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 730 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
 731 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
 732 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
 733 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
 734 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
 735 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
 736 #define BMCR_RESET              0x8000  /* Reset the DP83840           */
 737
 738 /* Basic mode status register. */
 739 #define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
 740 #define BMSR_JCD                0x0002  /* Jabber detected             */
 741 #define BMSR_LSTATUS            0x0004  /* Link status                 */
 742 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
 743 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 744 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 745 #define BMSR_RESV               0x07c0  /* Unused...                   */
 746 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 747 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 748 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
 749 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
 750 #define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
 751
 752 /* Advertisement control register. */
 753 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
 754 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
 755 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
 756 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
 757 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
 758 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
 759 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
 760 #define ADVERTISE_RESV          0x1c00  /* Unused...                   */
 761 #define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
 762 #define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
 763 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 764
 765 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
 766                         ADVERTISE_CSMA)
 767 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
 768                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 769
 770 /* Link partner ability register. */
 771 #define LPA_SLCT                0x001f  /* Same as advertise selector  */
 772 #define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
 773 #define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
 774 #define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
 775 #define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
 776 #define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
 777 #define LPA_RESV                0x1c00  /* Unused...                   */
 778 #define LPA_RFAULT              0x2000  /* Link partner faulted        */
 779 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 780 #define LPA_NPAGE               0x8000  /* Next page bit               */
 781
 782 #define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
 783 #define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 784
 785 /* Expansion register for auto-negotiation. */
 786 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
 787 #define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
 788 #define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
 789 #define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
 790 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 791 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 792
 793 /* N-way test register. */
 794 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
 795 #define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
 796 #define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
 797
 798 struct eth_frame {
 799     UBYTE eth_packet_dest[6];
 800     UBYTE eth_packet_source[6];
 801     UWORD eth_packet_type;
 802     UBYTE eth_packet_data[ETH_MTU];
 803     UBYTE eth_pad[RX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 804 } __attribute__((packed));
 805 #define eth_packet_ieeelen eth_packet_type
 806
 807 void nv_get_functions(struct NFUnit *Unit);
 808
 809 #endif
 810