workbench/devs/networks/rtl8168/rtl8168.h

   1 #ifndef _RTL8168_H
   2 #define _RTL8168_H
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9         This program is free software; you can redistribute it and/or modify
  10         it under the terms of the GNU General Public License as published by
  11         the Free Software Foundation; either version 2 of the License, or
  12         (at your option) any later version.
  13
  14         This program is distributed in the hope that it will be useful, but
  15         WITHOUT ANY WARRANTY; without even the implied warranty of
  16         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17         General Public License for more details.
  18
  19         You should have received a copy of the GNU General Public License
  20         along with this program; if not, write to the Free Software
  21         Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22         MA 02111-1307, USA.
  23 */
  24
  25 #include <aros/debug.h>
  26
  27 #if DEBUG > 0
  28 #define RTL_DEBUG
  29 //#define RTL_DEBUG_PACKET
  30 #endif
  31
  32 #define RTLD(d) \
  33         if (unit->rtl8168u_flags & IFF_DEBUG) \
  34         { \
  35                 d; \
  36         }
  37
  38 #if defined(RTL_DEBUG_PACKET)
  39 #define RTLDP(d) \
  40         if (unit->rtl8168u_flags & IFF_DEBUG) \
  41         { \
  42                 d; \
  43         }
  44 #else
  45 #define RTLDP(d)
  46 #endif
  47
  48 //#define HAVE__PCI_MWI
  49
  50 #include <exec/types.h>
  51 #include <exec/libraries.h>
  52 #include <exec/semaphores.h>
  53 #include <exec/devices.h>
  54 #include <exec/interrupts.h>
  55 #include <dos/bptr.h>
  56
  57 #include <oop/oop.h>
  58
  59 #include <hidd/pci.h>
  60
  61 #include <devices/timer.h>
  62 #include <devices/sana2.h>
  63 #include <devices/sana2specialstats.h>
  64
  65 #include <proto/exec.h>
  66
  67 #include LC_LIBDEFS_FILE
  68
  69 #define net_device RTL8168Unit
  70
  71 #define RTL8168_TASK_NAME       "%s.task"
  72 #define RTL8168_PORT_NAME       "%s.port"
  73
  74 /** Operational parameters that are set at compile time **/
  75 #define ETH_ZLEN  60 // Min. octets in frame sans FCS
  76
  77 // Maximum size of the in-memory receive ring (smaller if no memory)
  78 #define RX_FIFO_THRESH  4         // Rx buffer level before first PCI xfer
  79
  80 // Size of the Tx bounce buffers -- must be at least (mtu+14+4)
  81 #define TX_BUF_SIZE     1536
  82 #define TX_FIFO_THRESH  256       // In bytes, rounded down to 32 byte units
  83 #define TX_DMA_BURST    4         // Calculate as 16 << val
  84
  85 /** Device Driver Structures **/
  86
  87 extern struct Library *OOPBase;
  88
  89 struct RTL8168Base {
  90     struct Device       rtl8168b_Device;
  91
  92     OOP_Object          *rtl8168b_PCI;
  93     OOP_AttrBase        rtl8168b_PCIDeviceAttrBase;
  94
  95     ULONG               rtl8168b_UnitCount;
  96     struct List         rtl8168b_Units;
  97
  98 /* TODO: move into a config block */
  99     /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 100     int                 rtl8168b_MaxIntWork;
 101
 102     /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 103     The RTL chips use a 64 element hash table based on the Ethernet CRC. */
 104     int                 rtl8168b_MulticastFilterLimit;
 105
 106     /* media options */
 107     #define MAX_UNITS 8
 108     int                 speed[MAX_UNITS];
 109     int                 duplex[MAX_UNITS];
 110     int                 autoneg[MAX_UNITS];
 111 };
 112
 113 #undef HiddPCIDeviceAttrBase
 114 #define HiddPCIDeviceAttrBase   (LIBBASE->rtl8168b_PCIDeviceAttrBase)
 115
 116 struct RTL8168Startup
 117 {
 118     struct MsgPort           *rtl8168sm_SyncPort;
 119     struct RTL8168Unit       *rtl8168sm_Unit;
 120 };
 121
 122 enum {
 123     WRITE_QUEUE,
 124     ADOPT_QUEUE,
 125     EVENT_QUEUE,
 126     GENERAL_QUEUE,
 127     REQUEST_QUEUE_COUNT
 128 };
 129
 130 struct Opener
 131 {
 132     struct MinNode  node;
 133     struct MsgPort  read_port;
 134     BOOL            (*rx_function)(APTR, APTR, ULONG);
 135     BOOL            (*tx_function)(APTR, APTR, ULONG);
 136     struct Hook     *filter_hook;
 137     struct MinList  initial_stats;
 138 };
 139
 140 struct TypeStats
 141 {
 142     struct MinNode node;
 143     ULONG packet_type;
 144     struct Sana2PacketTypeStats stats;
 145 };
 146
 147
 148 struct TypeTracker
 149 {
 150     struct MinNode node;
 151     ULONG packet_type;
 152     struct Sana2PacketTypeStats stats;
 153     ULONG user_count;
 154 };
 155
 156
 157 struct AddressRange
 158 {
 159     struct MinNode node;
 160     ULONG add_count;
 161     ULONG lower_bound_left;
 162     ULONG upper_bound_left;
 163     UWORD lower_bound_right;
 164     UWORD upper_bound_right;
 165 };
 166
 167 #define STAT_COUNT 3
 168
 169 struct RTL8168Unit {
 170     struct MinNode          rtl8168u_Node;
 171
 172     struct RTL8168Base    *rtl8168u_device;
 173
 174     STRPTR                  rtl8168u_name;
 175
 176     ULONG                   rtl8168u_UnitNum;
 177     IPTR                    rtl8168u_DriverFlags;
 178
 179     OOP_Object              *rtl8168u_PCIDevice;
 180     OOP_Object              *rtl8168u_PCIDriver;
 181     IPTR                    rtl8168u_IRQ;
 182
 183     int                     rtl8168u_open_count;
 184     struct SignalSemaphore  rtl8168u_unit_lock;
 185
 186     LONG                    rtl8168u_range_count;
 187     struct MinList          rtl8168u_Openers;
 188     struct MinList          rtl8168u_multicast_ranges;
 189     struct MinList          rtl8168u_type_trackers;
 190
 191     struct timeval          rtl8168u_toutPOLL;
 192     BOOL                    rtl8168u_toutNEED;
 193     BOOL                    rtl8168u_IntsAdded;
 194
 195     struct MsgPort          *rtl8168u_TimerSlowPort;
 196     struct timerequest      *rtl8168u_TimerSlowReq;
 197
 198     struct MsgPort          *rtl8168u_TimerFastPort;
 199     struct timerequest      *rtl8168u_TimerFastReq;
 200
 201     struct MsgPort          rtl8168u_DelayPort;
 202     struct timerequest      rtl8168u_DelayReq;
 203
 204     ULONG                   rtl8168u_mtu;
 205     ULONG                   rtl8168u_flags;
 206     struct Sana2DeviceQuery  rtl8168u_Sana2Info;
 207     struct Sana2DeviceStats rtl8168u_stats;
 208     ULONG                   rtl8168u_special_stats[STAT_COUNT];
 209
 210     char                    *rtl8168u_rtl_cardname;
 211     const char              *rtl8168u_rtl_chipname;
 212     ULONG                  rtl8168u_rtl_chipcapabilities;
 213
 214     ULONG                  rtl8168u_rtl_LinkSpeed;
 215 #define support_fdx     (1 << 0) // Supports Full Duplex
 216 #define support_mii     (1 << 1)
 217 #define support_fset    (1 << 2)
 218 #define support_ltint   (1 << 3)
 219 #define support_dxsuflo (1 << 4)
 220 /* Card Funcs */
 221     void                    (*initialize)(struct RTL8168Unit *);
 222     void                    (*deinitialize)(struct RTL8168Unit *);
 223     int                     (*start)(struct RTL8168Unit *);
 224     int                     (*stop)(struct RTL8168Unit *);
 225     int                     (*alloc_rx)(struct RTL8168Unit *);
 226     void                    (*set_mac_address)(struct RTL8168Unit *);
 227     void                    (*linkchange)(struct RTL8168Unit *);
 228     void                    (*linkirq)(struct RTL8168Unit *);
 229 //    ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 230     void                    (*set_multicast)(struct RTL8168Unit *);
 231
 232     struct Process              *rtl8168u_Process;
 233
 234     struct Interrupt            rtl8168u_irqhandler;
 235     struct Interrupt            rtl8168u_touthandler;
 236     IPTR                        rtl8168u_DeviceID;
 237     APTR                        rtl8168u_BaseMem;
 238     IPTR                        rtl8168u_SizeMem;
 239     APTR                        rtl8168u_BaseIO;
 240
 241     BYTE                    rtl8168u_signal_0;
 242     BYTE                    rtl8168u_signal_1;
 243     BYTE                    rtl8168u_signal_2;
 244     BYTE                    rtl8168u_signal_3;
 245
 246     struct MsgPort              *rtl8168u_input_port;
 247
 248     struct MsgPort              *rtl8168u_request_ports[REQUEST_QUEUE_COUNT];
 249
 250     struct Interrupt    rtl8168u_rx_int;
 251     struct Interrupt    rtl8168u_tx_int;
 252
 253     ULONG                       rtl8168u_state;
 254     APTR                        rtl8168u_mc_list;
 255     int                 rtl8168u_mc_count;
 256
 257     UBYTE                       rtl8168u_dev_addr[6];
 258     UBYTE                       rtl8168u_org_addr[6];
 259     struct rtl8168_priv *rtl8168u_priv;
 260
 261     UWORD                       rtl8168u_intr_mask;
 262 };
 263
 264 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 265
 266 /* Media selection options. */
 267 enum {
 268     IF_PORT_UNKNOWN = 0,
 269     IF_PORT_10BASE2,
 270     IF_PORT_10BASET,
 271     IF_PORT_AUI,
 272     IF_PORT_100BASET,
 273     IF_PORT_100BASETX,
 274     IF_PORT_100BASEFX
 275 };
 276
 277 /* Standard interface flags (netdevice->flags). */
 278 #define IFF_UP          0x1             /* interface is up              */
 279 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 280 #define IFF_DEBUG       0x4             /* turn on debugging            */
 281 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 282 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 283 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 284 #define IFF_RUNNING     0x40            /* resources allocated          */
 285 #define IFF_NOARP       0x80            /* no ARP protocol              */
 286 #define IFF_PROMISC     0x100           /* receive all packets          */
 287 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 288
 289 #define IFF_MASTER      0x400           /* master of a load balancer    */
 290 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 291
 292 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 293
 294 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 295
 296 #define IFF_PORTSEL     0x2000          /* can set media type           */
 297 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 298 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 299 #define IFF_SHARED      0x10000         /* interface may be shared */
 300 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 301
 302 /* These flag bits are private to the generic network queueing
 303  * layer, they may not be explicitly referenced by any other
 304  * code.
 305  */
 306
 307 enum netdev_state_t
 308 {
 309     __LINK_STATE_XOFF=0,
 310     __LINK_STATE_START,
 311     __LINK_STATE_PRESENT,
 312     __LINK_STATE_SCHED,
 313     __LINK_STATE_NOCARRIER,
 314     __LINK_STATE_RX_SCHED,
 315     __LINK_STATE_LINKWATCH_PENDING
 316 };
 317
 318 static inline int test_bit(int nr, const volatile ULONG *addr)
 319 {
 320     return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 321 }
 322
 323 static inline void set_bit(int nr, volatile ULONG *addr)
 324 {
 325     addr[nr >> 5] |= 1UL << (nr & 31);
 326 }
 327
 328 static inline void clear_bit(int nr, volatile ULONG *addr)
 329 {
 330     addr[nr >> 5] &= ~(1UL << (nr & 31));
 331 }
 332
 333 static inline int test_and_set_bit(int nr, volatile ULONG *addr)
 334 {
 335     int oldbit = test_bit(nr, addr);
 336     set_bit(nr, addr);
 337     return oldbit;
 338 }
 339
 340 static inline int test_and_clear_bit(int nr, volatile ULONG *addr)
 341 {
 342     int oldbit = test_bit(nr, addr);
 343     clear_bit(nr, addr);
 344     return oldbit;
 345 }
 346
 347 static inline void netif_schedule(struct RTL8168Unit *unit)
 348 {
 349     if (!test_bit(__LINK_STATE_XOFF, &unit->rtl8168u_state)) {
 350             Cause(&unit->rtl8168u_tx_int);
 351     }
 352 }
 353
 354 static inline void netif_start_queue(struct RTL8168Unit *unit)
 355 {
 356     clear_bit(__LINK_STATE_XOFF, &unit->rtl8168u_state);
 357 }
 358
 359 static inline void netif_wake_queue(struct RTL8168Unit *unit)
 360 {
 361     if (test_and_clear_bit(__LINK_STATE_XOFF, &unit->rtl8168u_state)) {
 362         Cause(&unit->rtl8168u_tx_int);
 363     }
 364 }
 365
 366 static inline void netif_stop_queue(struct RTL8168Unit *unit)
 367 {
 368     set_bit(__LINK_STATE_XOFF, &unit->rtl8168u_state);
 369 }
 370
 371 static inline int netif_queue_stopped(const struct RTL8168Unit *unit)
 372 {
 373     return test_bit(__LINK_STATE_XOFF, &unit->rtl8168u_state);
 374 }
 375
 376 static inline int netif_running(const struct RTL8168Unit *unit)
 377 {
 378     return test_bit(__LINK_STATE_START, &unit->rtl8168u_state);
 379 }
 380
 381 static inline int netif_carrier_ok(const struct RTL8168Unit *unit)
 382 {
 383     return !test_bit(__LINK_STATE_NOCARRIER, &unit->rtl8168u_state);
 384 }
 385
 386 extern VOID ReportEvents(struct RTL8168Base *, struct RTL8168Unit *, ULONG);
 387
 388 static inline void netif_carrier_on(struct RTL8168Unit *unit)
 389 {
 390     if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &unit->rtl8168u_state)) {
 391         unit->rtl8168u_flags |= IFF_UP;
 392 RTLD(bug("[%s] %s: Device set as ONLINE\n",unit->rtl8168u_name, __PRETTY_FUNCTION__))
 393         ReportEvents(unit->rtl8168u_device, unit, S2EVENT_ONLINE);
 394     }
 395 }
 396
 397 static inline void netif_carrier_off(struct RTL8168Unit *unit)
 398 {
 399     if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &unit->rtl8168u_state)) {
 400         unit->rtl8168u_flags &= ~IFF_UP;
 401 RTLD(bug("[%s] %s: Device set as OFFLINE\n",unit->rtl8168u_name, __PRETTY_FUNCTION__))
 402         ReportEvents(unit->rtl8168u_device, unit, S2EVENT_OFFLINE);
 403     }
 404 }
 405
 406 /*
 407  *      We tag multicasts with these structures.
 408  */
 409
 410 #define MAX_ADDR_LEN    32
 411
 412 struct dev_mc_list
 413 {
 414     struct dev_mc_list      *next;
 415     UBYTE                   dmi_addr[MAX_ADDR_LEN];
 416     unsigned char           dmi_addrlen;
 417     int                     dmi_users;
 418     int                     dmi_gusers;
 419 };
 420
 421 struct pci_resource {
 422     UBYTE                       cmd;
 423     UBYTE                       cls;
 424     UWORD                       io_base_h;
 425     UWORD                       io_base_l;
 426     UWORD                       mem_base_h;
 427     UWORD                       mem_base_l;
 428     UBYTE                       ilr;
 429     UWORD                       resv_0x20_h;
 430     UWORD                       resv_0x20_l;
 431     UWORD                       resv_0x24_h;
 432     UWORD                       resv_0x24_l;
 433 };
 434
 435 struct rtl8168_priv {
 436     struct RTL8168Unit          *pci_dev;
 437
 438     int                         chipset;
 439     int                         mcfg;
 440     UWORD                       cp_cmd;
 441     unsigned                    features;
 442
 443     UWORD                       intr_mask;
 444
 445     int                         phy_auto_nego_reg;
 446     int                         phy_1000_ctrl_reg;
 447
 448     UBYTE                       autoneg;
 449     UWORD                       speed;
 450     UBYTE                       duplex;
 451
 452     struct TxDesc               *TxDescArray;   /* 256-aligned Tx descriptor ring */
 453     struct RxDesc               *RxDescArray;   /* 256-aligned Rx descriptor ring */
 454     APTR                        TxPhyAddr;
 455     APTR                        RxPhyAddr;
 456
 457     unsigned int                rtl8168_rx_config;
 458
 459     unsigned                    rx_buf_sz;
 460
 461     int                         rx_fifo_overflow;
 462
 463     ULONG                       tx_tcp_csum_cmd;
 464     ULONG                       tx_udp_csum_cmd;
 465     ULONG                       tx_ip_csum_cmd;
 466
 467     struct pci_resource         pci_cfg_space;
 468
 469     unsigned int                pci_cfg_is_read;
 470
 471     ULONG                       cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 472     ULONG                       cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 473     ULONG                       dirty_rx;
 474     ULONG                       dirty_tx;
 475
 476     struct SignalSemaphore      lock;
 477
 478     UBYTE                       orig_mac[6];
 479 };
 480
 481 #define pci_name(unit)  (unit->rtl8168u_name)
 482
 483 /* ENET defines */
 484
 485 #define HZ                  1000000
 486 #define ETH_DATA_LEN        1500
 487
 488 #define ETH_ADDRESSSIZE     6
 489 #define ETH_HEADERSIZE      14
 490 #define ETH_CRCSIZE         4
 491 #define ETH_MTU             (ETH_DATA_LEN)
 492 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 493
 494 #define ETH_PACKET_DEST     0
 495 #define ETH_PACKET_SOURCE   6
 496 #define ETH_PACKET_TYPE     12
 497 #define ETH_PACKET_IEEELEN  12
 498 #define ETH_PACKET_SNAPTYPE 20
 499 #define ETH_PACKET_DATA     14
 500 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 501
 502 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 503
 504 #define TX_LIMIT_STOP   63
 505 #define TX_LIMIT_START  62
 506
 507 struct eth_frame {
 508     UBYTE eth_packet_dest[6];
 509     UBYTE eth_packet_source[6];
 510     UWORD eth_packet_type;
 511     UBYTE eth_packet_data[ETH_MTU];
 512     UBYTE eth_packet_crc[4];
 513     UBYTE eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 514 } __attribute__((packed));
 515 #define eth_packet_ieeelen eth_packet_type
 516
 517 /* ***************************** */
 518 /*       RTL8168 DEFINES         */
 519 /* ***************************** */
 520
 521 #ifndef DMA_64BIT_MASK
 522 #define DMA_64BIT_MASK          0xffffffffffffffffULL
 523 #endif
 524 #ifndef DMA_32BIT_MASK
 525 #define DMA_32BIT_MASK          0x00000000ffffffffULL
 526 #endif
 527
 528 #ifndef PCI_COMMAND
 529 #define PCI_COMMAND             0x04
 530 #endif
 531 #ifndef PCI_CACHE_LINE_SIZE
 532 #define PCI_CACHE_LINE_SIZE     0x0c
 533 #endif
 534 #ifndef PCI_LATENCY_TIMER
 535 #define PCI_LATENCY_TIMER       0x0d
 536 #endif
 537 #ifndef PCI_BASE_ADDRESS_0
 538 #define PCI_BASE_ADDRESS_0      0x10
 539 #endif
 540 #ifndef PCI_BASE_ADDRESS_2
 541 #define PCI_BASE_ADDRESS_2      0x18
 542 #endif
 543 #ifndef PCI_BASE_ADDRESS_4
 544 #define PCI_BASE_ADDRESS_4      0x20
 545 #endif
 546 #ifndef PCI_BASE_ADDRESS_5
 547 #define PCI_BASE_ADDRESS_5      0x24
 548 #endif
 549 #ifndef PCI_INTERRUPT_LINE
 550 #define PCI_INTERRUPT_LINE      0x32
 551 #endif
 552
 553 #ifndef ETH_ALEN
 554 #define ETH_ALEN                ETH_ADDRESSSIZE
 555 #endif
 556 #ifndef ETH_HLEN
 557 #define ETH_HLEN                ETH_HEADERSIZE
 558 #endif
 559
 560 #ifndef ADVERTISED_Pause
 561 #define ADVERTISED_Pause        (1 << 13)
 562 #endif
 563 #ifndef ADVERTISED_Asym_Pause
 564 #define ADVERTISED_Asym_Pause   (1 << 14)
 565 #endif
 566 #ifndef ADVERTISE_PAUSE_CAP
 567 #define ADVERTISE_PAUSE_CAP     0x400
 568 #endif
 569 #ifndef ADVERTISE_PAUSE_ASYM
 570 #define ADVERTISE_PAUSE_ASYM    0x800
 571 #endif
 572 #ifndef MII_CTRL1000
 573 #define MII_CTRL1000            0x09
 574 #endif
 575 #ifndef ADVERTISE_1000FULL
 576 #define ADVERTISE_1000FULL      0x200
 577 #endif
 578 #ifndef ADVERTISE_1000HALF
 579 #define ADVERTISE_1000HALF      0x100
 580 #endif
 581
 582 /** Generic MII Registers - TODO: should be in MII header file **/
 583
 584 #ifndef MII_BMCR
 585 // Basic Mode Control Register
 586 #define MII_BMCR                0x00
 587 #endif
 588 #ifndef MII_ADVERTISE
 589 // Advertisement Control Register
 590 #define MII_ADVERTISE           0x04
 591 #endif
 592
 593 /** Basic Mode Control Register - TODO: should be in MII header file **/
 594
 595 #ifndef BMCR_FULLDPLX
 596 // Full Duplex
 597 #define BMCR_FULLDPLX           0x0100
 598 #endif
 599 #ifndef BMCR_ANRESTART
 600 // AutoNeg Restart
 601 #define BMCR_ANRESTART          0x0200
 602 #endif
 603 #ifndef BMCR_ANENABLE
 604 // AutoNeg Enable
 605 #define BMCR_ANENABLE           0x1000
 606 #endif
 607 #ifndef BMCR_RESET
 608 #define BMCR_RESET              0x8000
 609 #endif
 610
 611 /** Advertisement Control Register - TODO: should be in MII header file **/
 612
 613 #ifndef ADVERTISE_10HALF
 614 #define ADVERTISE_10HALF        0x0020
 615 #endif
 616 #ifndef ADVERTISE_10FULL
 617 #define ADVERTISE_10FULL        0x0040
 618 #endif
 619 #ifndef ADVERTISE_100HALF
 620 #define ADVERTISE_100HALF       0x0080
 621 #endif
 622 #ifndef ADVERTISE_100FULL
 623 #define ADVERTISE_100FULL       0x0100
 624 #endif
 625
 626 /* These should also have an own header */
 627
 628 #ifndef AUTONEG_DISABLE
 629 #define AUTONEG_DISABLE         0x00
 630 #endif
 631 #ifndef AUTONEG_ENABLE
 632 #define AUTONEG_ENABLE          0x01
 633 #endif
 634 #ifndef SPEED_10
 635 #define SPEED_10                10
 636 #endif
 637 #ifndef SPEED_100
 638 #define SPEED_100               100
 639 #endif
 640 #ifndef SPEED_1000
 641 #define SPEED_1000              1000
 642 #endif
 643 #ifndef DUPLEX_HALF
 644 #define DUPLEX_HALF             0x00
 645 #endif
 646 #ifndef DUPLEX_FULL
 647 #define DUPLEX_FULL             0x01
 648 #endif
 649
 650 /* write/read MMIO register */
 651 #define RTL_R8(addr)            (*((volatile UBYTE *)(addr)))
 652 #define RTL_R16(addr)           (*((volatile UWORD *)(addr)))
 653 #define RTL_R32(addr)           (*((volatile ULONG *)(addr)))
 654 #define RTL_W8(addr, val8)      MMIO_W8(addr, val8)
 655 #define RTL_W16(addr, val16)    MMIO_W16(addr, val16)
 656 #define RTL_W32(addr, val32)    MMIO_W32(addr, val32)
 657
 658 #define R8168_REGS_SIZE         256
 659
 660 #define MAC_ADDR_LEN            6
 661
 662 #define Reserved2_data  7
 663 #define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
 664 #define TX_DMA_BURST_unlimited  7
 665 #define TX_DMA_BURST_1024       6
 666 #define TX_DMA_BURST_512        5
 667 #define TX_DMA_BURST_256        4
 668 #define TX_DMA_BURST_128        3
 669 #define TX_DMA_BURST_64         2
 670 #define TX_DMA_BURST_32         1
 671 #define TX_DMA_BURST_16         0
 672 #define Reserved1_data  0x3F
 673 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
 674 #define Jumbo_Frame_2k  (2 * 1024)
 675 #define Jumbo_Frame_3k  (3 * 1024)
 676 #define Jumbo_Frame_4k  (4 * 1024)
 677 #define Jumbo_Frame_5k  (5 * 1024)
 678 #define Jumbo_Frame_6k  (6 * 1024)
 679 #define Jumbo_Frame_7k  (7 * 1024)
 680 #define Jumbo_Frame_8k  (8 * 1024)
 681 #define Jumbo_Frame_9k  (9 * 1024)
 682 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
 683
 684 #define RX_BUF_SIZE     0x05F3  /* 0x05F3 = 1523 Rx Buffer size */
 685 #define R8168_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
 686 #define R8168_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
 687
 688 #define NUM_TX_DESC     1024    /* Number of Tx descriptor registers */
 689 #define NUM_RX_DESC     1024    /* Number of Rx descriptor registers */
 690
 691 enum mcfg {
 692     CFG_METHOD_1 = 0x01,
 693     CFG_METHOD_2 = 0x02,
 694     CFG_METHOD_3 = 0x03,
 695     CFG_METHOD_4 = 0x04,
 696     CFG_METHOD_5 = 0x05,
 697     CFG_METHOD_6 = 0x06,
 698     CFG_METHOD_7 = 0x07,
 699     CFG_METHOD_8 = 0x08,
 700     CFG_METHOD_9 = 0x09,
 701     CFG_METHOD_10 = 0x0a,
 702     CFG_METHOD_11 = 0x0b,
 703 };
 704
 705 enum RTL8168_DSM_STATE {
 706     DSM_MAC_INIT = 1,
 707     DSM_NIC_GOTO_D3 = 2,
 708     DSM_IF_DOWN = 3,
 709     DSM_NIC_RESUME_D3 = 4,
 710     DSM_IF_UP = 5,
 711 };
 712
 713 enum RTL8168_registers {
 714     MAC0 = 0,           /* Ethernet hardware address. */
 715     MAC4 = 0x04,
 716     MAR0 = 8,           /* Multicast filter. */
 717     CounterAddrLow = 0x10,
 718     CounterAddrHigh = 0x14,
 719     TxDescStartAddrLow = 0x20,
 720     TxDescStartAddrHigh = 0x24,
 721     TxHDescStartAddrLow = 0x28,
 722     TxHDescStartAddrHigh = 0x2c,
 723     FLASH = 0x30,
 724     ERSR = 0x36,
 725     ChipCmd = 0x37,
 726     TxPoll = 0x38,
 727     IntrMask = 0x3C,
 728     IntrStatus = 0x3E,
 729     TxConfig = 0x40,
 730     RxConfig = 0x44,
 731     TCTR = 0x48,
 732     Cfg9346 = 0x50,
 733     Config0 = 0x51,
 734     Config1 = 0x52,
 735     Config2 = 0x53,
 736     Config3 = 0x54,
 737     Config4 = 0x55,
 738     Config5 = 0x56,
 739     TimeIntr = 0x58,
 740     PHYAR = 0x60,
 741     CSIDR = 0x64,
 742     CSIAR = 0x68,
 743     PHYstatus = 0x6C,
 744     MACDBG = 0x6D,
 745     GPIO = 0x6E,
 746     EPHYAR = 0x80,
 747     DBG_reg = 0xD1,
 748     RxMaxSize = 0xDA,
 749     CPlusCmd = 0xE0,
 750     IntrMitigate = 0xE2,
 751     RxDescAddrLow = 0xE4,
 752     RxDescAddrHigh = 0xE8,
 753     Reserved1 = 0xEC,
 754     FuncEvent = 0xF0,
 755     FuncEventMask = 0xF4,
 756     FuncPresetState = 0xF8,
 757     FuncForceEvent = 0xFC,
 758 };
 759
 760 enum RTL8168_register_content {
 761     /* InterruptStatusBits */
 762     SYSErr              = 0x8000,
 763     PCSTimeout  = 0x4000,
 764     SWInt               = 0x0100,
 765     TxDescUnavail       = 0x0080,
 766     RxFIFOOver  = 0x0040,
 767     LinkChg             = 0x0020,
 768     RxDescUnavail       = 0x0010,
 769     TxErr               = 0x0008,
 770     TxOK                = 0x0004,
 771     RxErr               = 0x0002,
 772     RxOK                = 0x0001,
 773
 774     /* RxStatusDesc */
 775     RxRWT = (1 << 22),
 776     RxRES = (1 << 21),
 777     RxRUNT = (1 << 20),
 778     RxCRC = (1 << 19),
 779
 780     /* ChipCmdBits */
 781     StopReq  = 0x80,
 782     CmdReset = 0x10,
 783     CmdRxEnb = 0x08,
 784     CmdTxEnb = 0x04,
 785     RxBufEmpty = 0x01,
 786
 787     /* Cfg9346Bits */
 788     Cfg9346_Lock = 0x00,
 789     Cfg9346_Unlock = 0xC0,
 790
 791     /* rx_mode_bits */
 792     AcceptErr = 0x20,
 793     AcceptRunt = 0x10,
 794     AcceptBroadcast = 0x08,
 795     AcceptMulticast = 0x04,
 796     AcceptMyPhys = 0x02,
 797     AcceptAllPhys = 0x01,
 798
 799     /* Transmit Priority Polling*/
 800     HPQ = 0x80,
 801     NPQ = 0x40,
 802     FSWInt = 0x01,
 803
 804     /* RxConfigBits */
 805     Reserved2_shift = 13,
 806     RxCfgDMAShift = 8,
 807     RxCfg_128_int_en = (1 << 15),
 808     RxCfg_fet_multi_en = (1 << 14),
 809     RxCfg_half_refetch = (1 << 13),
 810
 811     /* TxConfigBits */
 812     TxInterFrameGapShift = 24,
 813     TxDMAShift = 8,     /* DMA burst value (0-7) is shift this many bits */
 814     TxMACLoopBack = (1 << 17),  /* MAC loopback */
 815
 816     /* Config1 register p.24 */
 817     LEDS1               = (1 << 7),
 818     LEDS0               = (1 << 6),
 819     Speed_down  = (1 << 4),
 820     MEMMAP              = (1 << 3),
 821     IOMAP               = (1 << 2),
 822     VPD         = (1 << 1),
 823     PMEnable    = (1 << 0),     /* Power Management Enable */
 824
 825     /* Config3 register */
 826     MagicPacket = (1 << 5),     /* Wake up when receives a Magic Packet */
 827     LinkUp              = (1 << 4),     /* This bit is reserved in RTL8168B.*/
 828                                     /* Wake up when the cable connection is re-established */
 829     ECRCEN              = (1 << 3),     /* This bit is reserved in RTL8168B*/
 830     Jumbo_En0   = (1 << 2),     /* This bit is reserved in RTL8168B*/
 831     RDY_TO_L23  = (1 << 1),     /* This bit is reserved in RTL8168B*/
 832     Beacon_en   = (1 << 0),     /* This bit is reserved in RTL8168B*/
 833
 834     /* Config4 register */
 835     Jumbo_En1   = (1 << 1),     /* This bit is reserved in RTL8168B*/
 836
 837     /* Config5 register */
 838     BWF         = (1 << 6),     /* Accept Broadcast wakeup frame */
 839     MWF         = (1 << 5),     /* Accept Multicast wakeup frame */
 840     UWF         = (1 << 4),     /* Accept Unicast wakeup frame */
 841     LanWake             = (1 << 1),     /* LanWake enable/disable */
 842     PMEStatus   = (1 << 0),     /* PME status can be reset by PCI RST# */
 843
 844     /* CPlusCmd */
 845     EnableBist  = (1 << 15),
 846     Macdbgo_oe  = (1 << 14),
 847     Normal_mode = (1 << 13),
 848     Force_halfdup       = (1 << 12),
 849     Force_rxflow_en     = (1 << 11),
 850     Force_txflow_en     = (1 << 10),
 851     Cxpl_dbg_sel        = (1 << 9),//This bit is reserved in RTL8168B
 852     ASF         = (1 << 8),//This bit is reserved in RTL8168C
 853     PktCntrDisable      = (1 << 7),
 854     RxVlan              = (1 << 6),
 855     RxChkSum    = (1 << 5),
 856     Macdbgo_sel = 0x001C,
 857     INTT_0              = 0x0000,
 858     INTT_1              = 0x0001,
 859     INTT_2              = 0x0002,
 860     INTT_3              = 0x0003,
 861
 862     /* rtl8168_PHYstatus */
 863     TxFlowCtrl = 0x40,
 864     RxFlowCtrl = 0x20,
 865     _1000bpsF = 0x10,
 866     _100bps = 0x08,
 867     _10bps = 0x04,
 868     LinkStatus = 0x02,
 869     FullDup = 0x01,
 870
 871     /* DBG_reg */
 872     Fix_Nak_1 = (1 << 4),
 873     Fix_Nak_2 = (1 << 3),
 874     DBGPIN_E2 = (1 << 0),
 875
 876     /* DumpCounterCommand */
 877     CounterDump = 0x8,
 878
 879     /* PHY access */
 880     PHYAR_Flag = 0x80000000,
 881     PHYAR_Write = 0x80000000,
 882     PHYAR_Read = 0x00000000,
 883     PHYAR_Reg_Mask = 0x1f,
 884     PHYAR_Reg_shift = 16,
 885     PHYAR_Data_Mask = 0xffff,
 886
 887     /* EPHY access */
 888     EPHYAR_Flag = 0x80000000,
 889     EPHYAR_Write = 0x80000000,
 890     EPHYAR_Read = 0x00000000,
 891     EPHYAR_Reg_Mask = 0x1f,
 892     EPHYAR_Reg_shift = 16,
 893     EPHYAR_Data_Mask = 0xffff,
 894
 895     /* CSI access */
 896     CSIAR_Flag = 0x80000000,
 897     CSIAR_Write = 0x80000000,
 898     CSIAR_Read = 0x00000000,
 899     CSIAR_ByteEn = 0x0f,
 900     CSIAR_ByteEn_shift = 12,
 901     CSIAR_Addr_Mask = 0x0fff,
 902
 903     /* GPIO */
 904     GPIO_en = (1 << 0),
 905 };
 906
 907 enum _DescStatusBit {
 908     DescOwn             = (1 << 31), /* Descriptor is owned by NIC */
 909     RingEnd             = (1 << 30), /* End of descriptor ring */
 910     FirstFrag   = (1 << 29), /* First segment of a packet */
 911     LastFrag    = (1 << 28), /* Final segment of a packet */
 912
 913     /* Tx private */
 914     /*------ offset 0 of tx descriptor ------*/
 915     LargeSend   = (1 << 27), /* TCP Large Send Offload (TSO) */
 916     MSSShift    = 16,        /* MSS value position */
 917     MSSMask             = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 918     TxIPCS              = (1 << 18), /* Calculate IP checksum */
 919     TxUDPCS             = (1 << 17), /* Calculate UDP/IP checksum */
 920     TxTCPCS             = (1 << 16), /* Calculate TCP/IP checksum */
 921     TxVlanTag   = (1 << 17), /* Add VLAN tag */
 922
 923     /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
 924     TxUDPCS_C   = (1 << 31), /* Calculate UDP/IP checksum */
 925     TxTCPCS_C   = (1 << 30), /* Calculate TCP/IP checksum */
 926     TxIPCS_C    = (1 << 29), /* Calculate IP checksum */
 927     /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
 928
 929
 930     /* Rx private */
 931     /*------ offset 0 of rx descriptor ------*/
 932     PID1                = (1 << 18), /* Protocol ID bit 1/2 */
 933     PID0                = (1 << 17), /* Protocol ID bit 2/2 */
 934
 935 #define RxProtoUDP      (PID1)
 936 #define RxProtoTCP      (PID0)
 937 #define RxProtoIP       (PID1 | PID0)
 938 #define RxProtoMask     RxProtoIP
 939
 940     RxIPF               = (1 << 16), /* IP checksum failed */
 941     RxUDPF              = (1 << 15), /* UDP/IP checksum failed */
 942     RxTCPF              = (1 << 14), /* TCP/IP checksum failed */
 943     RxVlanTag   = (1 << 16), /* VLAN tag available */
 944
 945     /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
 946     RxUDPT              = (1 << 18),
 947     RxTCPT              = (1 << 17),
 948     /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
 949
 950     /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
 951     RxV6F               = (1 << 31),
 952     RxV4F               = (1 << 30),
 953     /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
 954 };
 955
 956 enum features {
 957 //    RTL_FEATURE_WOL   = (1 << 0),
 958     RTL_FEATURE_MSI     = (1 << 1),
 959 };
 960
 961 #define RsvdMask        0x3fffc000
 962
 963 struct TxDesc {
 964     ULONG opts1;
 965     ULONG opts2;
 966     UQUAD addr;
 967 };
 968
 969 struct RxDesc {
 970     ULONG opts1;
 971     ULONG opts2;
 972     UQUAD addr;
 973 };
 974
 975 void rtl8168nic_get_functions(struct RTL8168Unit *Unit);
 976 void rtl8168nic_USecDelay(struct net_device *, ULONG);
 977 #define udelay(usec)     rtl8168nic_USecDelay(unit, usec)
 978 #endif