Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / rtl8169 / rtl8101_hw.c
blob3dee1936fa76a858896b406df3fd05d8bca7cd4c
1 #include "rtl8101_hw.h"
3 void rtl_hw_start_8101(struct net_device *unit)
5 struct rtl8169_priv *np = get_pcnpriv(unit);
6 APTR base = get_hwbase(unit);
8 if ((np->mcfg == RTL_GIGA_MAC_VER_13) ||
9 (np->mcfg == RTL_GIGA_MAC_VER_16))
11 HIDD_PCIDevice_WriteConfigWord(unit->rtl8169u_PCIDevice, 0x68, 0x00);
12 HIDD_PCIDevice_WriteConfigWord(unit->rtl8169u_PCIDevice, 0x69, 0x09);
15 RTL_W8(base + Cfg9346, Cfg9346_Unlock);
17 RTL_W8(base + EarlyTxThres, EarlyTxThld);
19 rtl_set_rx_max_size(unit);
21 np->cp_cmd |= rtl_rw_cpluscmd(unit) | PCIMulRW;
23 RTL_W16(base + CPlusCmd, np->cp_cmd);
25 RTL_W16(base + IntrMitigate, 0x0000);
27 rtl_set_rx_tx_desc_registers(unit);
29 RTL_W8(base + ChipCmd, CmdTxEnb | CmdRxEnb);
30 rtl_set_rx_tx_config_registers(unit);
32 RTL_W8(base + Cfg9346, Cfg9346_Lock);
34 RTL_R8(base + IntrMask);
36 RTL_W32(base + RxMissed, 0);
38 rtl_set_rx_mode(unit);
40 RTL_W8(base + ChipCmd, CmdTxEnb | CmdRxEnb);
42 RTL_W16(base + MultiIntr, RTL_R16(base + MultiIntr) & 0xf000);
44 RTL_W16(base + IntrMask, np->intr_event);