workbench/devs/networks/rtl8169/rtl8169.h

   1 #ifndef _RTL8169_H_
   2 #define _RTL8169_H_
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9         This program is free software; you can redistribute it and/or modify
  10         it under the terms of the GNU General Public License as published by
  11         the Free Software Foundation; either version 2 of the License, or
  12         (at your option) any later version.
  13
  14         This program is distributed in the hope that it will be useful, but
  15         WITHOUT ANY WARRANTY; without even the implied warranty of
  16         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17         General Public License for more details.
  18
  19         You should have received a copy of the GNU General Public License
  20         along with this program; if not, write to the Free Software
  21         Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22         MA 02111-1307, USA.
  23 */
  24 #ifndef DEBUG
  25 #define DEBUG 0
  26 #endif
  27 #include <aros/debug.h>
  28
  29 #if DEBUG > 0
  30 #define RTL_DEBUG
  31 #define RTL_DEBUG_PACKET
  32 #endif
  33
  34 #define RTLD(d) \
  35         if (unit->rtl8169u_flags & IFF_DEBUG) \
  36         { \
  37                 d; \
  38         }
  39
  40 #if defined(RTL_DEBUG_PACKET)
  41 #define RTLDP(d) \
  42         if (unit->rtl8169u_flags & IFF_DEBUG) \
  43         { \
  44                 d; \
  45         }
  46 #else
  47 #define RTLDP(d)
  48 #endif
  49
  50 //#define HAVE__PCI_MWI
  51
  52 #include <exec/types.h>
  53 #include <exec/libraries.h>
  54 #include <exec/semaphores.h>
  55 #include <exec/devices.h>
  56 #include <exec/interrupts.h>
  57 #include <dos/bptr.h>
  58
  59 #include <oop/oop.h>
  60
  61 #include <hidd/pci.h>
  62
  63 #include <devices/timer.h>
  64 #include <devices/sana2.h>
  65 #include <devices/sana2specialstats.h>
  66
  67 #include <proto/exec.h>
  68
  69 #include LC_LIBDEFS_FILE
  70
  71 #define net_device RTL8169Unit
  72
  73 #define RTL8169_TASK_NAME       "%s.task"
  74 #define RTL8169_PORT_NAME       "%s.port"
  75
  76 #define PCI_VENDOR_ID_REALTEK 0x10ec
  77 #define PCI_VENDOR_ID_DLINK 0x1186
  78 #define PCI_VENDOR_ID_AT 0x1259
  79 #define PCI_VENDOR_ID_USROBOTICS 0x16ec
  80 #define PCI_VENDOR_ID_LINKSYS 0x11ad
  81
  82 /** Operational parameters that are set at compile time **/
  83 #define ETH_ZLEN  60 // Min. octets in frame sans FCS
  84
  85 #define PCI_ANY_ID (~0)
  86
  87 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  88
  89 #define swab32(x) \
  90  ((ULONG)( \
  91  (((ULONG)(x) & (ULONG) 0x000000ffUL) << 24) | \
  92  (((ULONG)(x) & (ULONG) 0x0000ff00UL) << 8) | \
  93  (((ULONG)(x) & (ULONG) 0x00ff0000UL) >> 8) | \
  94  (((ULONG)(x) & (ULONG) 0xff000000UL) >> 24) ))
  95
  96 // Maximum size of the in-memory receive ring (smaller if no memory)
  97 #define RX_FIFO_THRESH  7         // Rx buffer level before first PCI xfer
  98
  99 // Size of the Tx bounce buffers -- must be at least (mtu+14+4)
 100 #define TX_BUF_SIZE     1536
 101 #define TX_FIFO_THRESH  256       // In bytes, rounded down to 32 byte units
 102 #define TX_DMA_BURST    6         // Calculate as 16 << val
 103
 104 /** Device Driver Structures **/
 105
 106 extern struct Library *OOPBase;
 107
 108 struct RTL8169Base {
 109     struct Device       rtl8169b_Device;
 110
 111     OOP_Object          *rtl8169b_PCI;
 112     OOP_AttrBase        rtl8169b_PCIDeviceAttrBase;
 113
 114     ULONG               rtl8169b_UnitCount;
 115     struct List         rtl8169b_Units;
 116
 117     /* TODO: move into a config block */
 118     /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 119     int                 rtl8169b_MaxIntWork;
 120
 121     /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 122     The RTL chips use a 64 element hash table based on the Ethernet CRC. */
 123     int                 rtl8169b_MulticastFilterLimit;
 124
 125     /* media options */
 126     #define MAX_UNITS 8
 127     int                 speed[MAX_UNITS];
 128     int                 duplex[MAX_UNITS];
 129     int                 autoneg[MAX_UNITS];
 130 };
 131
 132 #undef HiddPCIDeviceAttrBase
 133 #define HiddPCIDeviceAttrBase   (LIBBASE->rtl8169b_PCIDeviceAttrBase)
 134
 135 struct RTL8169Startup
 136 {
 137     struct MsgPort           *rtl8169sm_SyncPort;
 138     struct RTL8169Unit       *rtl8169sm_Unit;
 139 };
 140
 141 enum cfg_version
 142 {
 143         RTL_CFG_0 = 0x00,
 144         RTL_CFG_1,
 145         RTL_CFG_2,
 146         UNKNOWN_CFG
 147 };
 148
 149 enum mac_version
 150 {
 151         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 152         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 153         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 154         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 155         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 156         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 157         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 158         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 159         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 160         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 161         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 162         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 163         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 164         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 165         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 166         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
 167 };
 168
 169 enum
 170 {
 171     WRITE_QUEUE,
 172     ADOPT_QUEUE,
 173     EVENT_QUEUE,
 174     GENERAL_QUEUE,
 175     REQUEST_QUEUE_COUNT
 176 };
 177
 178 struct Opener
 179 {
 180     struct MinNode  node;
 181     struct MsgPort  read_port;
 182     BOOL            (*rx_function)(APTR, APTR, ULONG);
 183     BOOL            (*tx_function)(APTR, APTR, ULONG);
 184     struct Hook     *filter_hook;
 185     struct MinList  initial_stats;
 186 };
 187
 188 struct TypeStats
 189 {
 190     struct MinNode node;
 191     ULONG packet_type;
 192     struct Sana2PacketTypeStats stats;
 193 };
 194
 195
 196 struct TypeTracker
 197 {
 198     struct MinNode node;
 199     ULONG packet_type;
 200     struct Sana2PacketTypeStats stats;
 201     ULONG user_count;
 202 };
 203
 204
 205 struct AddressRange
 206 {
 207     struct MinNode node;
 208     ULONG add_count;
 209     ULONG lower_bound_left;
 210     ULONG upper_bound_left;
 211     UWORD lower_bound_right;
 212     UWORD upper_bound_right;
 213 };
 214
 215 #define STAT_COUNT 3
 216
 217 struct RTL8169Unit {
 218     struct MinNode          rtl8169u_Node;
 219
 220     struct RTL8169Base    *rtl8169u_device;
 221
 222     STRPTR                  rtl8169u_name;
 223
 224     ULONG                   rtl8169u_UnitNum;
 225     IPTR                    rtl8169u_DriverFlags;
 226
 227     OOP_Object              *rtl8169u_PCIDevice;
 228     OOP_Object              *rtl8169u_PCIDriver;
 229     IPTR                    rtl8169u_IRQ;
 230
 231     int                     rtl8169u_open_count;
 232     struct SignalSemaphore  rtl8169u_unit_lock;
 233
 234     LONG                    rtl8169u_range_count;
 235     struct MinList          rtl8169u_Openers;
 236     struct MinList          rtl8169u_multicast_ranges;
 237     struct MinList          rtl8169u_type_trackers;
 238
 239     struct timeval          rtl8169u_toutPOLL;
 240     BOOL                    rtl8169u_toutNEED;
 241     BOOL                    rtl8169u_IntsAdded;
 242
 243     struct MsgPort          *rtl8169u_TimerSlowPort;
 244     struct timerequest      *rtl8169u_TimerSlowReq;
 245
 246     struct MsgPort          *rtl8169u_TimerFastPort;
 247     struct timerequest      *rtl8169u_TimerFastReq;
 248
 249     struct MsgPort          rtl8169u_DelayPort;
 250     struct timerequest      rtl8169u_DelayReq;
 251
 252     int                     rtl8169u_config;
 253     ULONG                   rtl8169u_mtu;
 254     ULONG                   rtl8169u_flags;
 255     struct Sana2DeviceQuery  rtl8169u_Sana2Info;
 256     struct Sana2DeviceStats rtl8169u_stats;
 257     ULONG                   rtl8169u_special_stats[STAT_COUNT];
 258
 259     char                    *rtl8169u_rtl_cardname;
 260     const char              *rtl8169u_rtl_chipname;
 261     ULONG                   rtl8169u_rtl_chipcapabilities;
 262
 263     ULONG                   rtl8169u_rtl_LinkSpeed;
 264 #define support_fdx     (1 << 0) // Supports Full Duplex
 265 #define support_mii     (1 << 1)
 266 #define support_fset    (1 << 2)
 267 #define support_ltint   (1 << 3)
 268 #define support_dxsuflo (1 << 4)
 269 /* Card Funcs */
 270     void                    (*initialize)(struct RTL8169Unit *);
 271     void                    (*deinitialize)(struct RTL8169Unit *);
 272     int                     (*start)(struct RTL8169Unit *);
 273     int                     (*stop)(struct RTL8169Unit *);
 274     int                     (*alloc_rx)(struct RTL8169Unit *);
 275     void                    (*set_mac_address)(struct RTL8169Unit *);
 276     void                    (*linkchange)(struct RTL8169Unit *);
 277     void                    (*linkirq)(struct RTL8169Unit *);
 278 //    ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 279     void                    (*set_multicast)(struct RTL8169Unit *);
 280
 281     struct Process              *rtl8169u_Process;
 282
 283     struct Interrupt            rtl8169u_irqhandler;
 284     struct Interrupt            rtl8169u_touthandler;
 285     IPTR                        rtl8169u_DeviceID;
 286     APTR                        rtl8169u_BaseMem;
 287     IPTR                        rtl8169u_SizeMem;
 288     APTR                        rtl8169u_BaseIO;
 289
 290     BYTE                    rtl8169u_signal_0;
 291     BYTE                    rtl8169u_signal_1;
 292     BYTE                    rtl8169u_signal_2;
 293     BYTE                    rtl8169u_signal_3;
 294
 295     struct MsgPort              *rtl8169u_input_port;
 296
 297     struct MsgPort              *rtl8169u_request_ports[REQUEST_QUEUE_COUNT];
 298
 299     struct Interrupt    rtl8169u_rx_int;
 300     struct Interrupt    rtl8169u_tx_int;
 301
 302     ULONG                       rtl8169u_state;
 303     APTR                        rtl8169u_mc_list;
 304     int                 rtl8169u_mc_count;
 305
 306     UBYTE                       rtl8169u_dev_addr[6];
 307     UBYTE                       rtl8169u_org_addr[6];
 308     struct rtl8169_priv *rtl8169u_priv;
 309
 310     UWORD                       rtl8169u_intr_event;
 311     UWORD                       rtl8169u_napi_event;
 312 };
 313
 314 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 315
 316 /* Media selection options. */
 317 enum {
 318     IF_PORT_UNKNOWN = 0,
 319     IF_PORT_10BASE2,
 320     IF_PORT_10BASET,
 321     IF_PORT_AUI,
 322     IF_PORT_100BASET,
 323     IF_PORT_100BASETX,
 324     IF_PORT_100BASEFX
 325 };
 326
 327 /* Standard interface flags (netdevice->flags). */
 328 #define IFF_UP          0x1             /* interface is up              */
 329 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 330 #define IFF_DEBUG       0x4             /* turn on debugging            */
 331 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 332 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 333 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 334 #define IFF_RUNNING     0x40            /* resources allocated          */
 335 #define IFF_NOARP       0x80            /* no ARP protocol              */
 336 #define IFF_PROMISC     0x100           /* receive all packets          */
 337 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 338
 339 #define IFF_MASTER      0x400           /* master of a load balancer    */
 340 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 341
 342 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 343
 344 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 345
 346 #define IFF_PORTSEL     0x2000          /* can set media type           */
 347 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 348 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 349 #define IFF_SHARED      0x10000         /* interface may be shared */
 350 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 351
 352 /* These flag bits are private to the generic network queueing
 353  * layer, they may not be explicitly referenced by any other
 354  * code.
 355  */
 356
 357 enum netdev_state_t
 358 {
 359     __LINK_STATE_XOFF=0,
 360     __LINK_STATE_START,
 361     __LINK_STATE_PRESENT,
 362     __LINK_STATE_SCHED,
 363     __LINK_STATE_NOCARRIER,
 364     __LINK_STATE_RX_SCHED,
 365     __LINK_STATE_LINKWATCH_PENDING
 366 };
 367
 368 static inline int test_bit(int nr, const volatile ULONG *addr)
 369 {
 370     return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 371 }
 372
 373 static inline void set_bit(int nr, volatile ULONG *addr)
 374 {
 375     addr[nr >> 5] |= 1UL << (nr & 31);
 376 }
 377
 378 static inline void clear_bit(int nr, volatile ULONG *addr)
 379 {
 380     addr[nr >> 5] &= ~(1UL << (nr & 31));
 381 }
 382
 383 static inline int test_and_set_bit(int nr, volatile ULONG *addr)
 384 {
 385     int oldbit = test_bit(nr, addr);
 386     set_bit(nr, addr);
 387     return oldbit;
 388 }
 389
 390 static inline int test_and_clear_bit(int nr, volatile ULONG *addr)
 391 {
 392     int oldbit = test_bit(nr, addr);
 393     clear_bit(nr, addr);
 394     return oldbit;
 395 }
 396
 397 static inline void netif_schedule(struct RTL8169Unit *unit)
 398 {
 399     if (!test_bit(__LINK_STATE_XOFF, &unit->rtl8169u_state)) {
 400             Cause(&unit->rtl8169u_tx_int);
 401     }
 402 }
 403
 404 static inline void netif_start_queue(struct RTL8169Unit *unit)
 405 {
 406     clear_bit(__LINK_STATE_XOFF, &unit->rtl8169u_state);
 407 }
 408
 409 static inline void netif_wake_queue(struct RTL8169Unit *unit)
 410 {
 411     if (test_and_clear_bit(__LINK_STATE_XOFF, &unit->rtl8169u_state)) {
 412         Cause(&unit->rtl8169u_tx_int);
 413     }
 414 }
 415
 416 static inline void netif_stop_queue(struct RTL8169Unit *unit)
 417 {
 418     set_bit(__LINK_STATE_XOFF, &unit->rtl8169u_state);
 419 }
 420
 421 static inline int netif_queue_stopped(const struct RTL8169Unit *unit)
 422 {
 423     return test_bit(__LINK_STATE_XOFF, &unit->rtl8169u_state);
 424 }
 425
 426 static inline int netif_running(const struct RTL8169Unit *unit)
 427 {
 428     return test_bit(__LINK_STATE_START, &unit->rtl8169u_state);
 429 }
 430
 431 static inline int netif_carrier_ok(const struct RTL8169Unit *unit)
 432 {
 433     return !test_bit(__LINK_STATE_NOCARRIER, &unit->rtl8169u_state);
 434 }
 435
 436 extern VOID ReportEvents(struct RTL8169Base *, struct RTL8169Unit *, ULONG);
 437
 438 static inline void netif_carrier_on(struct RTL8169Unit *unit)
 439 {
 440     if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &unit->rtl8169u_state)) {
 441         unit->rtl8169u_flags |= IFF_UP;
 442 RTLD(bug("[%s] %s: Device set as ONLINE\n",unit->rtl8169u_name, __PRETTY_FUNCTION__))
 443         ReportEvents(unit->rtl8169u_device, unit, S2EVENT_ONLINE);
 444     }
 445 }
 446
 447 static inline void netif_carrier_off(struct RTL8169Unit *unit)
 448 {
 449     if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &unit->rtl8169u_state)) {
 450         unit->rtl8169u_flags &= ~IFF_UP;
 451 RTLD(bug("[%s] %s: Device set as OFFLINE\n",unit->rtl8169u_name, __PRETTY_FUNCTION__))
 452         ReportEvents(unit->rtl8169u_device, unit, S2EVENT_OFFLINE);
 453     }
 454 }
 455
 456 /*
 457  *      We tag multicasts with these structures.
 458  */
 459
 460 #define MAX_ADDR_LEN    32
 461
 462 struct dev_mc_list
 463 {
 464     struct dev_mc_list      *next;
 465     UBYTE                   dmi_addr[MAX_ADDR_LEN];
 466     unsigned char           dmi_addrlen;
 467     int                     dmi_users;
 468     int                     dmi_gusers;
 469 };
 470
 471 struct pci_resource {
 472     UBYTE                       cmd;
 473     UBYTE                       cls;
 474     UWORD                       io_base_h;
 475     UWORD                       io_base_l;
 476     UWORD                       mem_base_h;
 477     UWORD                       mem_base_l;
 478     UBYTE                       ilr;
 479     UWORD                       resv_0x20_h;
 480     UWORD                       resv_0x20_l;
 481     UWORD                       resv_0x24_h;
 482     UWORD                       resv_0x24_l;
 483 };
 484
 485 struct rtl8169_priv {
 486     struct RTL8169Unit          *pci_dev;
 487
 488     int                         chipset;
 489     int                         mcfg;
 490     UWORD                       cp_cmd;
 491     unsigned                    features;
 492
 493     UWORD                       intr_mask;
 494     UWORD                       intr_event;
 495     UWORD                       napi_event;
 496
 497     int                         phy_auto_nego_reg;
 498     int                         phy_1000_ctrl_reg;
 499
 500     UBYTE                       autoneg;
 501     UWORD                       speed;
 502     UBYTE                       duplex;
 503
 504     struct TxDesc               *TxDescArray;   /* 256-aligned Tx descriptor ring */
 505     struct RxDesc               *RxDescArray;   /* 256-aligned Rx descriptor ring */
 506     APTR                        TxPhyAddr;
 507     APTR                        RxPhyAddr;
 508
 509     unsigned int                rtl8169_rx_config;
 510
 511     unsigned                    rx_buf_sz;
 512         unsigned                        tx_buf_sz;
 513
 514     int                         rx_fifo_overflow;
 515
 516     ULONG                       tx_tcp_csum_cmd;
 517     ULONG                       tx_udp_csum_cmd;
 518     ULONG                       tx_ip_csum_cmd;
 519
 520     struct pci_resource         pci_cfg_space;
 521
 522     unsigned int                pci_cfg_is_read;
 523
 524     ULONG                       cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 525     ULONG                       cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 526     ULONG                       dirty_rx;
 527     ULONG                       dirty_tx;
 528
 529     struct SignalSemaphore      lock;
 530
 531     UBYTE                       orig_mac[6];
 532 };
 533
 534 #define pci_name(unit)  (unit->rtl8169u_name)
 535
 536 /* ENET defines */
 537
 538 #define HZ                  1000000
 539 #define ETH_DATA_LEN        1500
 540
 541 #define ETH_ADDRESSSIZE     6
 542 #define ETH_HEADERSIZE      14
 543 #define ETH_CRCSIZE         4
 544 #define ETH_MTU             (ETH_DATA_LEN)
 545 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 546
 547 #define ETH_PACKET_DEST     0
 548 #define ETH_PACKET_SOURCE   6
 549 #define ETH_PACKET_TYPE     12
 550 #define ETH_PACKET_IEEELEN  12
 551 #define ETH_PACKET_SNAPTYPE 20
 552 #define ETH_PACKET_DATA     14
 553 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 554
 555 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 556
 557 #define TX_LIMIT_STOP   63
 558 #define TX_LIMIT_START  62
 559
 560 struct eth_frame {
 561     UBYTE eth_packet_dest[6];
 562     UBYTE eth_packet_source[6];
 563     UWORD eth_packet_type;
 564     UBYTE eth_packet_data[ETH_MTU];
 565     UBYTE eth_packet_crc[4];
 566     UBYTE eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 567 } __attribute__((packed));
 568 #define eth_packet_ieeelen eth_packet_type
 569
 570 /* ***************************** */
 571 /*       RTL8169 DEFINES         */
 572 /* ***************************** */
 573
 574 #ifndef DMA_64BIT_MASK
 575 #define DMA_64BIT_MASK          0xffffffffffffffffULL
 576 #endif
 577 #ifndef DMA_32BIT_MASK
 578 #define DMA_32BIT_MASK          0x00000000ffffffffULL
 579 #endif
 580
 581 #ifndef PCI_COMMAND
 582 #define PCI_COMMAND             0x04
 583 #endif
 584 #ifndef PCI_CACHE_LINE_SIZE
 585 #define PCI_CACHE_LINE_SIZE     0x0c
 586 #endif
 587 #ifndef PCI_LATENCY_TIMER
 588 #define PCI_LATENCY_TIMER       0x0d
 589 #endif
 590 #ifndef PCI_BASE_ADDRESS_0
 591 #define PCI_BASE_ADDRESS_0      0x10
 592 #endif
 593 #ifndef PCI_BASE_ADDRESS_2
 594 #define PCI_BASE_ADDRESS_2      0x18
 595 #endif
 596 #ifndef PCI_BASE_ADDRESS_4
 597 #define PCI_BASE_ADDRESS_4      0x20
 598 #endif
 599 #ifndef PCI_BASE_ADDRESS_5
 600 #define PCI_BASE_ADDRESS_5      0x24
 601 #endif
 602 #ifndef PCI_INTERRUPT_LINE
 603 #define PCI_INTERRUPT_LINE      0x32
 604 #endif
 605
 606 #ifndef ETH_ALEN
 607 #define ETH_ALEN                ETH_ADDRESSSIZE
 608 #endif
 609 #ifndef ETH_HLEN
 610 #define ETH_HLEN                ETH_HEADERSIZE
 611 #endif
 612
 613 #ifndef ADVERTISED_Pause
 614 #define ADVERTISED_Pause        (1 << 13)
 615 #endif
 616 #ifndef ADVERTISED_Asym_Pause
 617 #define ADVERTISED_Asym_Pause   (1 << 14)
 618 #endif
 619 #ifndef ADVERTISE_PAUSE_CAP
 620 #define ADVERTISE_PAUSE_CAP     0x400
 621 #endif
 622 #ifndef ADVERTISE_PAUSE_ASYM
 623 #define ADVERTISE_PAUSE_ASYM    0x800
 624 #endif
 625 #ifndef MII_CTRL1000
 626 #define MII_CTRL1000            0x09
 627 #endif
 628 #ifndef ADVERTISE_1000FULL
 629 #define ADVERTISE_1000FULL      0x200
 630 #endif
 631 #ifndef ADVERTISE_1000HALF
 632 #define ADVERTISE_1000HALF      0x100
 633 #endif
 634 #define ADVERTISE_SLCT 0x001f  /* Selector bits               */
 635 #define ADVERTISE_CSMA 0x0001  /* Only selector supported     */
 636 #define ADVERTISE_10HALF 0x0020  /* Try for 10mbps half-duplex  */
 637 #define ADVERTISE_10FULL 0x0040  /* Try for 10mbps full-duplex  */
 638 #define ADVERTISE_100HALF 0x0080  /* Try for 100mbps half-duplex */
 639 #define ADVERTISE_100FULL 0x0100  /* Try for 100mbps full-duplex */
 640 #define ADVERTISE_100BASE4 0x0200  /* Try for 100mbps 4k packets  */
 641 #define ADVERTISE_RESV 0x1c00  /* Unused...                   */
 642 #define ADVERTISE_RFAULT 0x2000  /* Say we can detect faults    */
 643 #define ADVERTISE_LPACK 0x4000  /* Ack link partners response  */
 644 #define ADVERTISE_NPAGE 0x8000  /* Next page bit               */
 645
 646 /** Generic MII Registers - TODO: should be in MII header file **/
 647
 648 #ifndef MII_BMCR
 649 // Basic Mode Control Register
 650 #define MII_BMCR                0x00
 651 #endif
 652 #ifndef MII_ADVERTISE
 653 // Advertisement Control Register
 654 #define MII_ADVERTISE           0x04
 655 #endif
 656
 657 /** Basic Mode Control Register - TODO: should be in MII header file **/
 658
 659 #ifndef BMCR_FULLDPLX
 660 // Full Duplex
 661 #define BMCR_FULLDPLX           0x0100
 662 #endif
 663 #ifndef BMCR_ANRESTART
 664 // AutoNeg Restart
 665 #define BMCR_ANRESTART          0x0200
 666 #endif
 667 #ifndef BMCR_ANENABLE
 668 // AutoNeg Enable
 669 #define BMCR_ANENABLE           0x1000
 670 #endif
 671 #ifndef BMCR_RESET
 672 #define BMCR_RESET              0x8000
 673 #endif
 674
 675 /** Advertisement Control Register - TODO: should be in MII header file **/
 676
 677 #ifndef ADVERTISE_10HALF
 678 #define ADVERTISE_10HALF        0x0020
 679 #endif
 680 #ifndef ADVERTISE_10FULL
 681 #define ADVERTISE_10FULL        0x0040
 682 #endif
 683 #ifndef ADVERTISE_100HALF
 684 #define ADVERTISE_100HALF       0x0080
 685 #endif
 686 #ifndef ADVERTISE_100FULL
 687 #define ADVERTISE_100FULL       0x0100
 688 #endif
 689
 690 /* These should also have an own header */
 691
 692 #ifndef AUTONEG_DISABLE
 693 #define AUTONEG_DISABLE         0x00
 694 #endif
 695 #ifndef AUTONEG_ENABLE
 696 #define AUTONEG_ENABLE          0x01
 697 #endif
 698 #ifndef SPEED_10
 699 #define SPEED_10                10
 700 #endif
 701 #ifndef SPEED_100
 702 #define SPEED_100               100
 703 #endif
 704 #ifndef SPEED_1000
 705 #define SPEED_1000              1000
 706 #endif
 707 #ifndef DUPLEX_HALF
 708 #define DUPLEX_HALF             0x00
 709 #endif
 710 #ifndef DUPLEX_FULL
 711 #define DUPLEX_FULL             0x01
 712 #endif
 713
 714 /* write/read MMIO register */
 715 #define RTL_R8(addr)            (*((volatile UBYTE *)(addr)))
 716 #define RTL_R16(addr)           (*((volatile UWORD *)(addr)))
 717 #define RTL_R32(addr)           (*((volatile ULONG *)(addr)))
 718 #define RTL_W8(addr, val8)      MMIO_W8(addr, val8)
 719 #define RTL_W16(addr, val16)    MMIO_W16(addr, val16)
 720 #define RTL_W32(addr, val32)    MMIO_W32(addr, val32)
 721
 722 #define R8169_REGS_SIZE         256
 723
 724 #define MAC_ADDR_LEN            6
 725
 726 #define Reserved2_data  7
 727 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 728 #define TX_DMA_BURST_unlimited  7
 729 #define TX_DMA_BURST_1024       6
 730 #define TX_DMA_BURST_512        5
 731 #define TX_DMA_BURST_256        4
 732 #define TX_DMA_BURST_128        3
 733 #define TX_DMA_BURST_64         2
 734 #define TX_DMA_BURST_32         1
 735 #define TX_DMA_BURST_16         0
 736 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
 737 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
 738 #define Jumbo_Frame_2k  (2 * 1024)
 739 #define Jumbo_Frame_3k  (3 * 1024)
 740 #define Jumbo_Frame_4k  (4 * 1024)
 741 #define Jumbo_Frame_5k  (5 * 1024)
 742 #define Jumbo_Frame_6k  (6 * 1024)
 743 #define Jumbo_Frame_7k  (7 * 1024)
 744 #define Jumbo_Frame_8k  (8 * 1024)
 745 #define Jumbo_Frame_9k  (9 * 1024)
 746 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
 747
 748 #define NUM_TX_DESC 64          /* Number of Tx descriptor registers */
 749 #define NUM_RX_DESC     256             /* Number of Rx descriptor registers */
 750
 751 #define R8169_NAPI_WEIGHT 64
 752 #define RX_BUF_SIZE     1536    /* 0x05F3 = 1523 Rx Buffer size */
 753 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
 754 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
 755
 756 enum RTL8169_DSM_STATE
 757 {
 758     DSM_MAC_INIT = 1,
 759     DSM_NIC_GOTO_D3 = 2,
 760     DSM_IF_DOWN = 3,
 761     DSM_NIC_RESUME_D3 = 4,
 762     DSM_IF_UP = 5,
 763 };
 764
 765 enum RTL8169_registers
 766 {
 767     MAC0 = 0,           /* Ethernet hardware address. */
 768     MAC4 = 0x04,
 769     MAR0 = 8,           /* Multicast filter. */
 770     CounterAddrLow = 0x10,
 771     CounterAddrHigh = 0x14,
 772     TxDescStartAddrLow = 0x20,
 773     TxDescStartAddrHigh = 0x24,
 774     TxHDescStartAddrLow = 0x28,
 775     TxHDescStartAddrHigh = 0x2c,
 776     FLASH = 0x30,
 777     ERSR = 0x36,
 778     ChipCmd = 0x37,
 779     TxPoll = 0x38,
 780     RxBufPtr = 0x3b,
 781     IntrMask = 0x3C,
 782     IntrStatus = 0x3E,
 783     TxConfig = 0x40,
 784     RxConfig = 0x44,
 785     TCTR = 0x48,
 786         RxMissed = 0x4C,
 787     Cfg9346 = 0x50,
 788     Config0 = 0x51,
 789     Config1 = 0x52,
 790     Config2 = 0x53,
 791     Config3 = 0x54,
 792     Config4 = 0x55,
 793     Config5 = 0x56,
 794     TimeIntr = 0x58,
 795         MultiIntr = 0x5c,
 796     PHYAR = 0x60,
 797     TBICSR = 0x64,
 798     TBI_ANAR = 0x68,
 799         TBI_LPAR = 0x6a,
 800     PHYstatus = 0x6C,
 801     MACDBG = 0x6D,
 802     GPIO = 0x6E,
 803     FIFOTMS = 0x70,
 804     CSCR = 0x74,
 805     PARA78 = 0x78,
 806     PARA7c = 0x7c,
 807     EPHYAR = 0x80,
 808     DBG_reg = 0xD1,
 809     RxMaxSize = 0xDA,
 810     CPlusCmd = 0xE0,
 811     IntrMitigate = 0xE2,
 812     RxDescAddrLow = 0xE4,
 813     RxDescAddrHigh = 0xE8,
 814         EarlyTxThres = 0xEC,
 815     FuncEvent = 0xF0,
 816     FuncEventMask = 0xF4,
 817     FuncPresetState = 0xF8,
 818     FuncForceEvent = 0xFC,
 819 };
 820
 821 enum RTL8169_CSCRbits
 822 {
 823         CSCR_LinkOKBit = 0x400,
 824         CSCR_LinkDownOffCmd = 0x3c0,
 825         CSCR_LinkChangeBit = 0x800,
 826         CSCR_LinkStatusBits = 0xf000,
 827         CSCR_LinkDownCmd = 0xf3c0
 828 };
 829
 830 enum RTL8169_register_content
 831 {
 832     /* InterruptStatusBits */
 833     TxOutOfWindow = 0x20000000,
 834     TxAborted     = 0x40000000,
 835     TxCarrierLost = 0x80000000,
 836     SYSErr              = 0x8000,
 837     PCIErr              = 0x8000,
 838     TxStatOK    = 0x8000,
 839     PCSTimeout  = 0x4000,
 840     TxUnderrun  = 0x4000,
 841     TxHostOwns  = 0x2000,
 842     SWInt               = 0x0100,
 843     TxDescUnavail = 0x0080,
 844     RxFIFOOver  = 0x0040,
 845     LinkChg             = 0x0020,
 846     RxUnderrun  = 0x0020,
 847     RxOverflow  = 0x0010,
 848     TxErr               = 0x0008,
 849     RxTooLong   = 0x0008,
 850     TxOK                = 0x0004,
 851     RxCRCErr    = 0x0004,
 852     RxErr               = 0x0002,
 853     RxBadAlign  = 0x0002,
 854     RxOK                = 0x0001,
 855     RxStatusOK  = 0x0001,
 856
 857     /* RxStatusDesc */
 858         RxFOVF = (1 << 23),
 859     RxRWT = (1 << 22),
 860     RxRES = (1 << 21),
 861     RxRUNT = (1 << 20),
 862     RxCRC = (1 << 19),
 863
 864     /* ChipCmdBits */
 865     StopReq  = 0x80,
 866     CmdReset = 0x10,
 867     CmdRxEnb = 0x08,
 868     CmdTxEnb = 0x04,
 869     RxBufEmpty = 0x01,
 870
 871     /* Cfg9346Bits */
 872     Cfg9346_Lock = 0x00,
 873     Cfg9346_Unlock = 0xC0,
 874
 875     /* rx_mode_bits */
 876     AcceptErr = 0x20,
 877     AcceptRunt = 0x10,
 878     AcceptBroadcast = 0x08,
 879     AcceptMulticast = 0x04,
 880     AcceptMyPhys = 0x02,
 881     AcceptAllPhys = 0x01,
 882
 883         /* Config2 register p. 25 */
 884         PCI_Clock_66MHz = 0x01,
 885         PCI_Clock_33MHz = 0x00,
 886
 887     /* Transmit Priority Polling*/
 888     HPQ = 0x80,
 889     NPQ = 0x40,
 890     FSWInt = 0x01,
 891
 892     /* RxConfigBits */
 893         RxCfgFIFOShift  = 13,
 894     RxCfgDMAShift = 8,
 895     RxCfg_128_int_en = (1 << 15),
 896     RxCfg_fet_multi_en = (1 << 14),
 897     RxCfg_half_refetch = (1 << 13),
 898
 899     /* TxConfigBits */
 900     TxInterFrameGapShift = 24,
 901     TxDMAShift = 8,     /* DMA burst value (0-7) is shift this many bits */
 902     TxMACLoopBack = (1 << 17),  /* MAC loopback */
 903
 904     /* Config1 register p.24 */
 905     LEDS1               = (1 << 7),
 906     LEDS0               = (1 << 6),
 907     Speed_down  = (1 << 4),
 908     MEMMAP              = (1 << 3),
 909     IOMAP               = (1 << 2),
 910     VPD         = (1 << 1),
 911         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 912     PMEnable    = (1 << 0),     /* Power Management Enable */
 913
 914     /* Config3 register */
 915     MagicPacket = (1 << 5),     /* Wake up when receives a Magic Packet */
 916     LinkUp              = (1 << 4),     /* This bit is reserved in RTL8168B.*/
 917                                     /* Wake up when the cable connection is re-established */
 918     ECRCEN              = (1 << 3),     /* This bit is reserved in RTL8168B*/
 919     Jumbo_En0   = (1 << 2),     /* This bit is reserved in RTL8168B*/
 920     RDY_TO_L23  = (1 << 1),     /* This bit is reserved in RTL8168B*/
 921     Beacon_en   = (1 << 0),     /* This bit is reserved in RTL8168B*/
 922
 923     /* Config4 register */
 924     Jumbo_En1   = (1 << 1),     /* This bit is reserved in RTL8168B*/
 925
 926     /* Config5 register */
 927     BWF         = (1 << 6),     /* Accept Broadcast wakeup frame */
 928     MWF         = (1 << 5),     /* Accept Multicast wakeup frame */
 929     UWF         = (1 << 4),     /* Accept Unicast wakeup frame */
 930     LanWake             = (1 << 1),     /* LanWake enable/disable */
 931     PMEStatus   = (1 << 0),     /* PME status can be reset by PCI RST# */
 932
 933         /* TBICSR p.28 */
 934         TBIReset = 0x80000000,
 935         TBILoopback     = 0x40000000,
 936         TBINwEnable     = 0x20000000,
 937         TBINwRestart = 0x10000000,
 938         TBILinkOk = 0x02000000,
 939         TBINwComplete = 0x01000000,
 940
 941     /* CPlusCmd */
 942     EnableBist  = (1 << 15),
 943     Macdbgo_oe  = (1 << 14),
 944     Normal_mode = (1 << 13),
 945     Force_halfdup       = (1 << 12),
 946     Force_rxflow_en     = (1 << 11),
 947     Force_txflow_en     = (1 << 10),
 948     Cxpl_dbg_sel        = (1 << 9),//This bit is reserved in RTL8168B
 949     ASF         = (1 << 8),//This bit is reserved in RTL8168C
 950     PktCntrDisable      = (1 << 7),
 951     RxVlan              = (1 << 6),
 952     RxChkSum    = (1 << 5),
 953         PCIDAC          = (1 << 4),
 954         PCIMulRW        = (1 << 3),
 955     Macdbgo_sel = 0x001C,
 956     INTT_0              = 0x0000,
 957     INTT_1              = 0x0001,
 958     INTT_2              = 0x0002,
 959     INTT_3              = 0x0003,
 960
 961     /* rtl8169_PHYstatus */
 962         TBI_Enable      = 0x80,
 963     TxFlowCtrl = 0x40,
 964     RxFlowCtrl = 0x20,
 965     _1000bpsF = 0x10,
 966     _100bps = 0x08,
 967     _10bps = 0x04,
 968     LinkStatus = 0x02,
 969     FullDup = 0x01,
 970
 971     /* DBG_reg */
 972     Fix_Nak_1 = (1 << 4),
 973     Fix_Nak_2 = (1 << 3),
 974     DBGPIN_E2 = (1 << 0),
 975
 976     /* DumpCounterCommand */
 977     CounterDump = 0x8,
 978
 979     /* PHY access */
 980     PHYAR_Flag = 0x80000000,
 981     PHYAR_Write = 0x80000000,
 982     PHYAR_Read = 0x00000000,
 983     PHYAR_Reg_Mask = 0x1f,
 984     PHYAR_Reg_shift = 16,
 985     PHYAR_Data_Mask = 0xffff,
 986
 987     /* EPHY access */
 988     EPHYAR_Flag = 0x80000000,
 989     EPHYAR_Write = 0x80000000,
 990     EPHYAR_Read = 0x00000000,
 991     EPHYAR_Reg_Mask = 0x1f,
 992     EPHYAR_Reg_shift = 16,
 993     EPHYAR_Data_Mask = 0xffff,
 994
 995     /* CSI access */
 996     CSIAR_Flag = 0x80000000,
 997     CSIAR_Write = 0x80000000,
 998     CSIAR_Read = 0x00000000,
 999     CSIAR_ByteEn = 0x0f,
1000     CSIAR_ByteEn_shift = 12,
1001     CSIAR_Addr_Mask = 0x0fff,
1002
1003     /* GPIO */
1004     GPIO_en = (1 << 0),
1005 };
1006
1007 enum _DescStatusBit
1008 {
1009     DescOwn             = (1 << 31), /* Descriptor is owned by NIC */
1010     RingEnd             = (1 << 30), /* End of descriptor ring */
1011     FirstFrag   = (1 << 29), /* First segment of a packet */
1012     LastFrag    = (1 << 28), /* Final segment of a packet */
1013
1014     /* Tx private */
1015     /*------ offset 0 of tx descriptor ------*/
1016     LargeSend   = (1 << 27), /* TCP Large Send Offload (TSO) */
1017     MSSShift    = 16,        /* MSS value position */
1018     MSSMask             = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
1019     TxIPCS              = (1 << 18), /* Calculate IP checksum */
1020     TxUDPCS             = (1 << 17), /* Calculate UDP/IP checksum */
1021     TxTCPCS             = (1 << 16), /* Calculate TCP/IP checksum */
1022     TxVlanTag   = (1 << 17), /* Add VLAN tag */
1023
1024     /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
1025     TxUDPCS_C   = (1 << 31), /* Calculate UDP/IP checksum */
1026     TxTCPCS_C   = (1 << 30), /* Calculate TCP/IP checksum */
1027     TxIPCS_C    = (1 << 29), /* Calculate IP checksum */
1028     /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
1029
1030
1031     /* Rx private */
1032     /*------ offset 0 of rx descriptor ------*/
1033     PID1                = (1 << 18), /* Protocol ID bit 1/2 */
1034     PID0                = (1 << 17), /* Protocol ID bit 2/2 */
1035
1036 #define RxProtoUDP      (PID1)
1037 #define RxProtoTCP      (PID0)
1038 #define RxProtoIP       (PID1 | PID0)
1039 #define RxProtoMask     RxProtoIP
1040
1041     RxIPF               = (1 << 16), /* IP checksum failed */
1042     RxUDPF              = (1 << 15), /* UDP/IP checksum failed */
1043     RxTCPF              = (1 << 14), /* TCP/IP checksum failed */
1044     RxVlanTag   = (1 << 16), /* VLAN tag available */
1045
1046     /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
1047     RxUDPT              = (1 << 18),
1048     RxTCPT              = (1 << 17),
1049     /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
1050
1051     /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only             begin @@@@@@*/
1052     RxV6F               = (1 << 31),
1053     RxV4F               = (1 << 30),
1054     /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only             end @@@@@@*/
1055 };
1056
1057 enum features
1058 {
1059     RTL_FEATURE_WOL     = (1 << 0),
1060     RTL_FEATURE_MSI     = (1 << 1),
1061 };
1062
1063 #define RsvdMask        0x3fffc000
1064
1065 struct TxDesc
1066 {
1067     ULONG opts1;
1068     ULONG opts2;
1069     UQUAD addr;
1070 };
1071
1072 struct RxDesc
1073 {
1074     ULONG opts1;
1075     ULONG opts2;
1076     UQUAD addr;
1077 };
1078
1079 struct phy_reg
1080 {
1081         UWORD reg;
1082         UWORD val;
1083 };
1084
1085 struct card_def
1086 {
1087     int vendorID;
1088     int productID;
1089     int sub_vendorID;
1090     int sub_productID;
1091     int config;
1092 };
1093
1094 #define NBR_CARDS 11
1095 struct card_def cards[NBR_CARDS];
1096
1097 void rtl8169_get_functions(struct RTL8169Unit *Unit);
1098 void rtl8169_USecDelay(struct net_device *, ULONG);
1099 ULONG mdio_read(struct net_device *unit, int RegAddr);
1100 void mdio_write(struct net_device *unit, int RegAddr, UWORD value);
1101 void rtl_phy_write(struct net_device *unit, struct phy_reg *regs, int len);
1102 void rtl_set_rx_mode(struct net_device *unit);
1103 UWORD rtl_rw_cpluscmd(struct net_device *unit);
1104 void rtl_set_rx_max_size(struct net_device *unit);
1105 void rtl_set_rx_tx_desc_registers(struct net_device *unit);
1106 void rtl_set_rx_tx_config_registers(struct net_device *unit);
1107 void rtl8169_write_gmii_reg_bit(struct net_device *unit, int reg, int bitnum, int bitval);
1108 UBYTE *get_hwbase(struct net_device *unit);
1109 struct rtl8169_priv *get_pcnpriv(struct net_device *unit);
1110 void MMIO_W32(APTR addr, ULONG val32);
1111 void MMIO_W16(APTR addr, UWORD val16);
1112 void MMIO_W8(APTR addr, UBYTE val8);
1113
1114 #define udelay(usec) rtl8169_USecDelay(unit, usec)
1115 #endif