workbench/devs/networks/via-rhine/via-rhine.h

   1 #ifndef _VIA_RHINE_H
   2 #define _VIA_RHINE_H
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful, but
  15     WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17     General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22     MA 02111-1307, USA.
  23 */
  24
  25 #include <exec/types.h>
  26 #include <exec/libraries.h>
  27 #include <exec/semaphores.h>
  28 #include <exec/devices.h>
  29 #include <exec/interrupts.h>
  30 #include <dos/bptr.h>
  31
  32 #include <oop/oop.h>
  33
  34 #include <hidd/pci.h>
  35
  36 #include <devices/timer.h>
  37 #include <devices/sana2.h>
  38 #include <devices/sana2specialstats.h>
  39
  40 #include <proto/exec.h>
  41 #include <aros/debug.h>
  42
  43 #include LC_LIBDEFS_FILE
  44
  45 #define VIARHINE_TASK_NAME      "VIA-RHINE task"
  46 #define VIARHINE_PORT_NAME      "VIA-RHINE port"
  47
  48 #define TX_BUFFERS        8
  49 #define RX_BUFFERS        16
  50
  51 #define BUFFER_SIZE       2048L              /* Enough to hold a 1536 Frame     */
  52 #define MAX_FRAME_SIZE    1536               /* 1536                            */
  53 #define MAX_MULTI         32                 /* Hardware Related, Do not change */
  54
  55 /** Device Driver Structures **/
  56
  57 struct VIARHINEBase {
  58     struct Device       rhineb_Device;
  59     struct MsgPort      *rhineb_syncport;
  60
  61     OOP_Object          *rhineb_pci;
  62     OOP_Object          *rhineb_irq;
  63     OOP_AttrBase        rhineb_pciDeviceAttrBase;
  64
  65     struct Sana2DeviceQuery  rhineb_Sana2Info;
  66     struct VIARHINEUnit            *rhineb_unit;
  67
  68     /* UnitCount is used to assign unit ID's to found hardware ..*/
  69     unsigned int                    rhineb_UnitCount;
  70 };
  71
  72 #undef HiddPCIDeviceAttrBase
  73 #define HiddPCIDeviceAttrBase   (LIBBASE->rhineb_pciDeviceAttrBase)
  74
  75 enum {
  76     WRITE_QUEUE,
  77     ADOPT_QUEUE,
  78     EVENT_QUEUE,
  79     GENERAL_QUEUE,
  80     REQUEST_QUEUE_COUNT
  81 };
  82
  83 struct Opener
  84 {
  85     struct MinNode  node;
  86     struct MsgPort  read_port;
  87     BOOL            (*rx_function)(APTR, APTR, ULONG);
  88     BOOL            (*tx_function)(APTR, APTR, ULONG);
  89     struct Hook     *filter_hook;
  90     struct MinList  initial_stats;
  91 };
  92
  93 struct TypeStats
  94 {
  95     struct MinNode node;
  96     ULONG packet_type;
  97     struct Sana2PacketTypeStats stats;
  98 };
  99
 100
 101 struct TypeTracker
 102 {
 103     struct MinNode node;
 104     ULONG packet_type;
 105     struct Sana2PacketTypeStats stats;
 106     ULONG user_count;
 107 };
 108
 109
 110 struct AddressRange
 111 {
 112     struct MinNode node;
 113     ULONG add_count;
 114     ULONG lower_bound_left;
 115     ULONG upper_bound_left;
 116     UWORD lower_bound_right;
 117     UWORD upper_bound_right;
 118 };
 119
 120 #define STAT_COUNT 3
 121
 122 struct VIARHINEUnit {
 123     struct MinNode          *rhineu_Node;
 124     struct MinList          rhineu_Openers;
 125     struct MinList          rhineu_multicast_ranges;
 126     struct MinList          rhineu_type_trackers;
 127     ULONG                   rhineu_UnitNum;
 128     LONG                    rhineu_range_count;
 129
 130     OOP_Object              *rhineu_PCIDevice;
 131     OOP_Object              *rhineu_PCIDriver;
 132
 133     struct timeval          rhineu_toutPOLL;
 134     BOOL                    rhineu_toutNEED;
 135     BOOL                    rhineu_IntsAdded;
 136
 137     struct MsgPort          *rhineu_TimerSlowPort;
 138     struct timerequest      *rhineu_TimerSlowReq;
 139
 140     struct MsgPort          *rhineu_TimerFastPort;
 141     struct timerequest      *rhineu_TimerFastReq;
 142
 143     struct Sana2DeviceStats rhineu_stats;
 144     ULONG                   rhineu_special_stats[STAT_COUNT];
 145
 146         char                    *rhineu_cardname;
 147         int                           rhineu_chipcapabilities;
 148
 149         ULONG                  rhineu_rtl_LinkSpeed;
 150 #define support_fdx     (1 << 0) // Supports Full Duplex
 151 #define support_mii     (1 << 1)
 152 #define support_fset    (1 << 2)
 153 #define support_ltint   (1 << 3)
 154 #define support_dxsuflo (1 << 4)
 155 /* Card Funcs */
 156     void                    (*initialize)(struct VIARHINEUnit *);
 157     void                    (*deinitialize)(struct VIARHINEUnit *);
 158     int                     (*start)(struct VIARHINEUnit *);
 159     int                     (*stop)(struct VIARHINEUnit *);
 160     int                     (*alloc_rx)(struct VIARHINEUnit *);
 161     void                    (*set_mac_address)(struct VIARHINEUnit *);
 162     void                    (*linkchange)(struct VIARHINEUnit *);
 163     void                    (*linkirq)(struct VIARHINEUnit *);
 164 //    ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 165     void                    (*set_multicast)(struct VIARHINEUnit *);
 166
 167     int                     rhineu_open_count;
 168     struct SignalSemaphore  rhineu_unit_lock;
 169
 170     struct Process          *rhineu_Process;
 171
 172     struct VIARHINEBase    *rhineu_device;
 173     struct Interrupt        rhineu_irqhandler;
 174     struct Interrupt        rhineu_touthandler;
 175     IPTR                        rhineu_DeviceID;
 176     IPTR                    rhineu_DriverFlags;
 177     IPTR                    rhineu_IRQ;
 178     IPTR                    rhineu_BaseMem;
 179     IPTR                    rhineu_SizeMem;
 180     IPTR                          rhineu_BaseIO;
 181
 182     BYTE                    rhineu_signal_0;
 183     BYTE                    rhineu_signal_1;
 184     BYTE                    rhineu_signal_2;
 185     BYTE                    rhineu_signal_3;
 186
 187     struct MsgPort          *rhineu_input_port;
 188
 189     struct MsgPort          *rhineu_request_ports[REQUEST_QUEUE_COUNT];
 190
 191     struct Interrupt        rhineu_rx_int;
 192     struct Interrupt        rhineu_tx_int;
 193
 194     STRPTR                  rhineu_name;
 195     ULONG                   rhineu_mtu;
 196     ULONG                   rhineu_flags;
 197     ULONG                   rhineu_state;
 198     APTR                    rhineu_mc_list;
 199     UBYTE                   rhineu_dev_addr[6];
 200     UBYTE                   rhineu_org_addr[6];
 201     struct fe_priv          *rhineu_fe_priv;
 202 };
 203
 204 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 205
 206 /* Media selection options. */
 207 enum {
 208         IF_PORT_UNKNOWN = 0,
 209         IF_PORT_10BASE2,
 210         IF_PORT_10BASET,
 211         IF_PORT_AUI,
 212         IF_PORT_100BASET,
 213         IF_PORT_100BASETX,
 214         IF_PORT_100BASEFX
 215 };
 216
 217 /* These flag bits are private to the generic network queueing
 218  * layer, they may not be explicitly referenced by any other
 219  * code.
 220  */
 221
 222 enum netdev_state_t
 223 {
 224         __LINK_STATE_XOFF=0,
 225         __LINK_STATE_START,
 226         __LINK_STATE_PRESENT,
 227         __LINK_STATE_SCHED,
 228         __LINK_STATE_NOCARRIER,
 229         __LINK_STATE_RX_SCHED,
 230         __LINK_STATE_LINKWATCH_PENDING
 231 };
 232
 233 static inline int test_bit(int nr, const volatile ULONG *addr)
 234 {
 235     return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 236 }
 237
 238 static inline void set_bit(int nr, volatile ULONG *addr)
 239 {
 240     addr[nr >> 5] |= 1UL << (nr & 31);
 241 }
 242
 243 static inline void clear_bit(int nr, volatile ULONG *addr)
 244 {
 245     addr[nr >> 5] &= ~(1UL << (nr & 31));
 246 }
 247
 248 static inline int test_and_set_bit(int nr, volatile ULONG *addr)
 249 {
 250     int oldbit = test_bit(nr, addr);
 251     set_bit(nr, addr);
 252     return oldbit;
 253 }
 254
 255 static inline int test_and_clear_bit(int nr, volatile ULONG *addr)
 256 {
 257     int oldbit = test_bit(nr, addr);
 258     clear_bit(nr, addr);
 259     return oldbit;
 260 }
 261
 262 static inline void netif_schedule(struct VIARHINEUnit *dev)
 263 {
 264     if (!test_bit(__LINK_STATE_XOFF, &dev->rhineu_state)) {
 265         Cause(&dev->rhineu_tx_int);
 266     }
 267 }
 268
 269
 270 static inline void netif_start_queue(struct VIARHINEUnit *dev)
 271 {
 272     clear_bit(__LINK_STATE_XOFF, &dev->rhineu_state);
 273 }
 274
 275 static inline void netif_wake_queue(struct VIARHINEUnit *dev)
 276 {
 277     if (test_and_clear_bit(__LINK_STATE_XOFF, &dev->rhineu_state)) {
 278         Cause(&dev->rhineu_tx_int);
 279     }
 280 }
 281
 282 static inline void netif_stop_queue(struct VIARHINEUnit *dev)
 283 {
 284     set_bit(__LINK_STATE_XOFF, &dev->rhineu_state);
 285 }
 286
 287 static inline int netif_queue_stopped(const struct VIARHINEUnit *dev)
 288 {
 289     return test_bit(__LINK_STATE_XOFF, &dev->rhineu_state);
 290 }
 291
 292 static inline int netif_running(const struct VIARHINEUnit *dev)
 293 {
 294     return test_bit(__LINK_STATE_START, &dev->rhineu_state);
 295 }
 296
 297 static inline int netif_carrier_ok(const struct VIARHINEUnit *dev)
 298 {
 299     return !test_bit(__LINK_STATE_NOCARRIER, &dev->rhineu_state);
 300 }
 301
 302 extern void __netdev_watchdog_up(struct VIARHINEUnit *dev);
 303
 304 static inline void netif_carrier_on(struct VIARHINEUnit *dev)
 305 {
 306     if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->rhineu_state)) {
 307 //                linkwatch_fire_event(dev);
 308     }
 309     if (netif_running(dev)) {
 310 //                __netdev_watchdog_up(dev);
 311     }
 312 }
 313
 314 static inline void netif_carrier_off(struct VIARHINEUnit *dev)
 315 {
 316     if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->rhineu_state)) {
 317 //                linkwatch_fire_event(dev);
 318     }
 319 }
 320
 321 /* Standard interface flags (netdevice->flags). */
 322 #define IFF_UP          0x1             /* interface is up              */
 323 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 324 #define IFF_DEBUG       0x4             /* turn on debugging            */
 325 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 326 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 327 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 328 #define IFF_RUNNING     0x40            /* resources allocated          */
 329 #define IFF_NOARP       0x80            /* no ARP protocol              */
 330 #define IFF_PROMISC     0x100           /* receive all packets          */
 331 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 332
 333 #define IFF_MASTER      0x400           /* master of a load balancer    */
 334 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 335
 336 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 337
 338 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 339
 340 #define IFF_PORTSEL     0x2000          /* can set media type           */
 341 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 342 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 343 #define IFF_SHARED      0x10000         /* interface may be shared */
 344 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 345
 346 /*
 347  *      We tag multicasts with these structures.
 348  */
 349
 350 #define MAX_ADDR_LEN    32
 351
 352 struct dev_mc_list
 353 {
 354     struct dev_mc_list      *next;
 355     UBYTE                   dmi_addr[MAX_ADDR_LEN];
 356     unsigned char           dmi_addrlen;
 357     int                     dmi_users;
 358     int                     dmi_gusers;
 359 };
 360
 361 /*
 362  * RX Descriptor
 363  */
 364 typedef struct
 365 {
 366         ULONG           rx_status;
 367         ULONG           desc_length;
 368
 369         ULONG           addr;
 370         ULONG           next;
 371 } viarhine_rx_desc;
 372
 373 /*
 374  * TX Descriptor
 375  */
 376 typedef struct
 377 {
 378         ULONG           tx_status;
 379         ULONG           desc_length;
 380
 381         ULONG           addr;
 382         ULONG           next;
 383 } viarhine_tx_desc;
 384
 385 struct fe_priv {
 386         /* Start - via rhine new */
 387         viarhine_rx_desc      rx_desc[RX_BUFFERS];  /* RX Frame Descriptors */
 388         viarhine_tx_desc       tx_desc[TX_BUFFERS];  /* TX Frame Descriptors */
 389
 390     struct   eth_frame   *rx_buffer;
 391         UBYTE                      rx_thresh;
 392         UBYTE                      rx_current;
 393
 394     struct   eth_frame    *tx_buffer;
 395         UBYTE                                       tx_thresh;
 396         UBYTE                      tx_current;
 397
 398     int                           full_duplex;
 399
 400         char                       mii_phys[4]; //MII device address
 401         unsigned short    mii_advertising;  //NWay media advertising
 402
 403         UWORD                                   cmd;
 404 /* End - via rhine new */
 405
 406     struct VIARHINEUnit   *pci_dev;
 407     int     in_shutdown;
 408     ULONG   linkspeed;
 409     int     duplex;
 410     int     autoneg;
 411     int     fixed_mode;
 412     int     phyaddr;
 413     int     wolenabled;
 414     unsigned int phy_oui;
 415     UWORD   gigabit;
 416     ULONG   desc_ver;
 417     struct SignalSemaphore  lock;
 418
 419     IPTR     ring_addr;
 420
 421
 422
 423     ULONG   cur_rx, refill_rx;
 424
 425     ULONG   next_tx, nic_tx;
 426     ULONG   tx_flags;
 427
 428     ULONG   irqmask;
 429     ULONG   need_linktimer;
 430     struct  timeval link_timeout;
 431     UBYTE   orig_mac[6];
 432 };
 433
 434 #define pci_name(unit)  (unit->rhineu_name)
 435
 436 /* ENET defines */
 437
 438 #define HZ                  1000000
 439 #define ETH_DATA_LEN        1500
 440
 441 #define ETH_ADDRESSSIZE     6
 442 #define ETH_HEADERSIZE      14
 443 #define ETH_CRCSIZE         4
 444 #define ETH_MTU             (ETH_DATA_LEN)
 445 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 446
 447 #define ETH_PACKET_DEST     0
 448 #define ETH_PACKET_SOURCE   6
 449 #define ETH_PACKET_TYPE     12
 450 #define ETH_PACKET_IEEELEN  12
 451 #define ETH_PACKET_SNAPTYPE 20
 452 #define ETH_PACKET_DATA     14
 453 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 454
 455 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 456
 457 #define TX_LIMIT_STOP   63
 458 #define TX_LIMIT_START  62
 459
 460 struct eth_frame {
 461     UBYTE eth_packet_dest[6];
 462     UBYTE eth_packet_source[6];
 463     UWORD eth_packet_type;
 464     UBYTE eth_packet_data[ETH_MTU];
 465     UBYTE eth_packet_crc[4];
 466     UBYTE eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 467 } __attribute__((packed));
 468 #define eth_packet_ieeelen eth_packet_type
 469
 470 void viarhinenic_get_functions(struct VIARHINEUnit *Unit);
 471
 472 /* **************************** */
 473 /*     OLD PCNET32 DEFINES       */
 474 /* **************************** */
 475
 476 #ifndef PCNET32_LOG_TX_BUFFERS
 477 #define PCNET32_LOG_TX_BUFFERS      3
 478 #define PCNET32_LOG_RX_BUFFERS      4
 479 #endif
 480
 481 #define TX_RING_SIZE                (1 << (PCNET32_LOG_TX_BUFFERS))
 482 #define TX_RING_MOD_MASK            (TX_RING_SIZE - 1)
 483 #define TX_RING_LEN_BITS            ((PCNET32_LOG_TX_BUFFERS) << 12)
 484
 485 #define RX_RING_SIZE                (1 << (PCNET32_LOG_RX_BUFFERS))
 486 #define RX_RING_MOD_MASK            (RX_RING_SIZE - 1)
 487 #define RX_RING_LEN_BITS            ((PCNET32_LOG_RX_BUFFERS) << 4)
 488
 489 /* ***************************** */
 490 /*     REAL VIA RHINE DEFINES       */
 491 /* ***************************** */
 492
 493 /*
 494  * Chip Compatibility
 495  */
 496 enum viarhine_chip_capability_flags
 497 {
 498         RTLc_CanHaveMII = 1
 499 };
 500
 501 /*
 502  * Registers Offsets
 503  */
 504 enum viarhine_register_offsets
 505 {
 506         VIAR_StationAddr      = 0x00,
 507         VIAR_RxConfig         = 0x06,
 508         VIAR_TxConfig         = 0x07,
 509         VIAR_ChipCmd          = 0x08,
 510         VIAR_IntrStatus       = 0x0C,
 511         VIAR_IntrEnable       = 0x0E,
 512         VIAR_MulticastFilter0 = 0x10,
 513         VIAR_MulticastFilter1 = 0x14,
 514         VIAR_RxRingPtr        = 0x18,
 515         VIAR_TxRingPtr        = 0x1C,
 516         VIAR_MIIPhyAddr       = 0x6C,
 517         VIAR_MIIStatus        = 0x6D,
 518         VIAR_PCIBusConfig     = 0x6E,
 519         VIAR_MIICmd           = 0x70,
 520         VIAR_MIIRegAddr       = 0x71,
 521         VIAR_MIIData          = 0x72,
 522         VIAR_Config           = 0x78,
 523         VIAR_RxMissed         = 0x7C,
 524         VIAR_RxCRCErrs        = 0x7E,
 525 };
 526
 527 /*
 528  * Command Bits
 529  */
 530 enum viarhine_chip_cmd_bits
 531 {
 532         CmdInit     = 0x0001,
 533         CmdStart    = 0x0002,
 534         CmdStop     = 0x0004,
 535         CmdRxOn     = 0x0008,
 536         CmdTxOn     = 0x0010,
 537         CmdTxDemand = 0x0020,
 538         CmdRxDemand = 0x0040,
 539         CmdEarlyRx  = 0x0100,
 540         CmdEarlyTx  = 0x0200,
 541         CmdFDuplex  = 0x0400,
 542         CmdNoTxPoll = 0x0800,
 543         CmdReset    = 0x8000
 544 };
 545
 546 /*
 547  * Interrupt Status Bits
 548  */
 549 enum viarhine_intr_status_bits
 550 {
 551         IntrRxDone          = 0x0001,
 552         IntrRxErr           = 0x0004,
 553         IntrRxEmpty         = 0x0020,
 554         IntrTxDone          = 0x0002,
 555         IntrTxAbort         = 0x0008,
 556         IntrTxUnderrun      = 0x0010,
 557         IntrPCIErr          = 0x0040,
 558         IntrStatsMax        = 0x0080,
 559         IntrRxEarly         = 0x0100,
 560         IntrMIIChange       = 0x0200,
 561         IntrRxOverflow      = 0x0400,
 562         IntrRxDropped       = 0x0800,
 563         IntrRxNoBuf         = 0x1000,
 564         IntrTxAborted       = 0x2000,
 565         IntrLinkChange      = 0x4000,
 566         IntrRxWakeUp        = 0x8000,
 567         IntrNormalSummary   = 0x0003,
 568         IntrAbnormalSummary = 0xC260,
 569 };
 570
 571 /*
 572  * RX Status Bits
 573  */
 574 enum viarhine_rx_status_bits
 575 {
 576         RxOK       = 0x8000,
 577         RxWholePkt = 0x0300,
 578         RxErr      = 0x008F
 579 };
 580
 581 /*
 582  * Desc Status Bits
 583  */
 584 enum viarhine_desc_status_bits
 585 {
 586         DescOwn       = 0x80000000,
 587         DescEndPacket = 0x4000,
 588         DescIntr      = 0x1000
 589 };
 590
 591 /** Serial EEPROM section **/
 592
 593 //  EEPROM_Ctrl bits
 594
 595 #define EE_SHIFT_CLK      0x04  // EEPROM shift clock
 596 #define EE_CS                  0x08  // EEPROM chip select
 597 #define EE_DATA_WRITE   0x02  // EEPROM chip data in
 598 #define EE_WRITE_0         0x00
 599 #define EE_WRITE_1         0x02
 600 #define EE_DATA_READ    0x01  // EEPROM chip data out
 601 #define EE_ENB               (0x80 | EE_CS)
 602
 603 // Delay between EEPROM clock transitions.
 604 // No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 605
 606 #define eeprom_delay(ee_addr)  LONGIN(ee_addr)
 607
 608 // The EEPROM commands include the alway-set leading bit
 609
 610 #define EE_WRITE_CMD  (5)
 611 #define EE_READ_CMD   (6)
 612 #define EE_ERASE_CMD  (7)
 613
 614 /** MII serial management **/
 615
 616 // Read and write the MII management registers using software-generated
 617 // serial MDIO protocol.
 618 // The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 619 // met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 620 // "overclocking" issues
 621
 622 #define MDIO_DIR              0x80
 623 #define MDIO_DATA_OUT  0x04
 624 #define MDIO_DATA_IN      0x02
 625 #define MDIO_CLK             0x01
 626 #define MDIO_WRITE0       (MDIO_DIR)
 627 #define MDIO_WRITE1       (MDIO_DIR | MDIO_DATA_OUT)
 628
 629 #define mdio_delay(mdio_addr) LONGIN(mdio_addr)
 630
 631 #endif
 632