workbench/hidds/vmwaresvga/vmwaresvgahardware.c

   1 /*
   2     Copyright © 1995-2008, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: vmware svga hardware functions
   6     Lang: English
   7 */
   8
   9 #define DEBUG 1 /* no SysBase */
  10 #include <aros/debug.h>
  11
  12 #include <asm/io.h>
  13
  14 #include "vmwaresvgahardware.h"
  15 #include "svga_reg.h"
  16 #include "vmwaresvgaclass.h"
  17
  18 ULONG vmwareReadReg(struct HWData *data, ULONG reg)
  19 {
  20     outl(reg, data->indexReg);
  21     return inl(data->valueReg);
  22 }
  23
  24 void vmwareWriteReg(struct HWData *data, ULONG reg, ULONG val)
  25 {
  26     outl(reg, data->indexReg);
  27     outl(val, data->valueReg);
  28 }
  29
  30 #undef SysBase
  31 extern struct ExecBase *SysBase;
  32
  33 ULONG getVMWareSVGAID(struct HWData *data)
  34 {
  35     ULONG id;
  36
  37     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_2);
  38     id = vmwareReadReg(data, SVGA_REG_ID);
  39     if (id == SVGA_ID_2)
  40         return id;
  41     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_1);
  42     id = vmwareReadReg(data, SVGA_REG_ID);
  43     if (id == SVGA_ID_1)
  44         return id;
  45     if (id == SVGA_ID_0)
  46         return id;
  47     return SVGA_ID_INVALID;
  48 }
  49
  50 VOID initVMWareSVGAFIFO(struct HWData *data)
  51 {
  52     ULONG *fifo;
  53     ULONG fifomin;
  54
  55     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 0);              //Stop vmware from reading the fifo
  56
  57     fifo = data->mmiobase = (APTR)(IPTR)vmwareReadReg(data, SVGA_REG_MEM_START);
  58     data->mmiosize = vmwareReadReg(data, SVGA_REG_MEM_SIZE) & ~3;
  59
  60     if (data->capabilities & SVGA_CAP_EXTENDED_FIFO)
  61         fifomin = vmwareReadReg(data, SVGA_REG_MEM_REGS);
  62     else
  63         fifomin =4;
  64
  65     fifo[SVGA_FIFO_MIN] = fifomin * sizeof(ULONG);
  66
  67     /* reduce size of FIFO queue to prevent VMWare from failing */
  68     fifo[SVGA_FIFO_MAX] = (data->mmiosize > 65536) ? 65536 : data->mmiosize;
  69     fifo[SVGA_FIFO_NEXT_CMD] = fifomin * sizeof(ULONG);
  70     fifo[SVGA_FIFO_STOP] = fifomin * sizeof(ULONG);
  71
  72     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 1);
  73 }
  74
  75 VOID syncVMWareSVGAFIFO(struct HWData *data)
  76 {
  77     vmwareWriteReg(data, SVGA_REG_SYNC, 1);
  78     while (vmwareReadReg(data, SVGA_REG_BUSY) != 0);
  79     /* FIXME: maybe wait (delay) some time */
  80 }
  81
  82 VOID writeVMWareSVGAFIFO(struct HWData *data, ULONG val)
  83 {
  84     ULONG *fifo;
  85
  86     fifo = data->mmiobase;
  87     if (
  88             (fifo[SVGA_FIFO_NEXT_CMD]+4 == fifo[SVGA_FIFO_STOP]) ||
  89             (
  90                 (fifo[SVGA_FIFO_NEXT_CMD] == (fifo[SVGA_FIFO_MAX]-4)) &&
  91                 (fifo[SVGA_FIFO_STOP] == fifo[SVGA_FIFO_MIN])
  92             )
  93         )
  94         syncVMWareSVGAFIFO(data);
  95
  96     fifo[fifo[SVGA_FIFO_NEXT_CMD] / 4] = val;
  97     fifo[SVGA_FIFO_NEXT_CMD] += 4;
  98
  99     if (fifo[SVGA_FIFO_NEXT_CMD] == fifo[SVGA_FIFO_MAX])
 100         fifo[SVGA_FIFO_NEXT_CMD] = fifo[SVGA_FIFO_MIN];
 101 }
 102
 103 BOOL initVMWareSVGAHW(struct HWData *data, OOP_Object *device)
 104 {
 105     ULONG id;
 106
 107     id = getVMWareSVGAID(data);
 108     if ((id == SVGA_ID_0) || (id == SVGA_ID_INVALID))
 109     {
 110         return FALSE;
 111     }
 112
 113     initVMWareSVGAFIFO(data);
 114
 115     data->capabilities = vmwareReadReg(data, SVGA_REG_CAPABILITIES);
 116
 117     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 118     {
 119         data->bitsperpixel = vmwareReadReg(data, SVGA_REG_HOST_BITS_PER_PIXEL);
 120         vmwareWriteReg(data,SVGA_REG_BITS_PER_PIXEL, data->bitsperpixel);
 121     }
 122     data->bitsperpixel = vmwareReadReg(data, SVGA_REG_BITS_PER_PIXEL);
 123
 124     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 125     data->maxwidth = vmwareReadReg(data, SVGA_REG_MAX_WIDTH);
 126     data->maxheight = vmwareReadReg(data, SVGA_REG_MAX_HEIGHT);
 127     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 128     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 129     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 130     data->bytesperpixel = 1;
 131
 132     if (data->depth>16)
 133         data->bytesperpixel = 4;
 134     else if (data->depth>8)
 135         data->bytesperpixel = 2;
 136
 137     if (data->capabilities & SVGA_CAP_MULTIMON)
 138     {
 139         data->displaycount = vmwareReadReg(data, SVGA_REG_NUM_DISPLAYS);
 140     }
 141     else
 142     {
 143         data->displaycount = 1;
 144     }
 145
 146     data->vramsize = vmwareReadReg(data, SVGA_REG_VRAM_SIZE);
 147     data->vrambase = (APTR)(IPTR)vmwareReadReg(data, SVGA_REG_FB_START);
 148     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 149
 150     D(bug("[VMWareSVGA] Init: VRAM at 0x%08x size %d\n",data->vrambase, data->vramsize));
 151     D(bug("[VMWareSVGA] Init: no.displays: %d\n",data->displaycount));
 152     D(bug("[VMWareSVGA] Init: caps : 0x%08x\n",data->capabilities));
 153     D(bug("[VMWareSVGA] Init: no.displays: %d\n",data->displaycount));
 154     D(bug("[VMWareSVGA] Init: depth: %d\n",data->depth));
 155     D(bug("[VMWareSVGA] Init: bpp  : %d\n",data->bitsperpixel));
 156     D(bug("[VMWareSVGA] Init: maxw: %d\n",data->maxwidth));
 157     D(bug("[VMWareSVGA] Init: maxh: %d\n",data->maxheight));
 158
 159     return TRUE;
 160 }
 161
 162 VOID setModeVMWareSVGA(struct HWData *data, ULONG width, ULONG height)
 163 {
 164     D(bug("[VMWareSVGA] SetMode: %dx%d\n",width,height));
 165     vmwareWriteReg(data, SVGA_REG_ENABLE, 0);
 166     vmwareWriteReg(data, SVGA_REG_WIDTH, width);
 167     vmwareWriteReg(data, SVGA_REG_HEIGHT, height);
 168
 169     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 170         vmwareWriteReg(data, SVGA_REG_BITS_PER_PIXEL,data->bitsperpixel);
 171
 172     vmwareWriteReg(data, SVGA_REG_ENABLE, 1);
 173
 174     data->fboffset = vmwareReadReg(data, SVGA_REG_FB_OFFSET);
 175     data->bytesperline = vmwareReadReg(data, SVGA_REG_BYTES_PER_LINE);
 176     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 177     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 178     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 179     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 180     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 181 }
 182
 183 VOID refreshAreaVMWareSVGA(struct HWData *data, struct Box *box)
 184 {
 185     writeVMWareSVGAFIFO(data, SVGA_CMD_UPDATE);
 186     writeVMWareSVGAFIFO(data, box->x1);
 187     writeVMWareSVGAFIFO(data, box->y1);
 188     writeVMWareSVGAFIFO(data, box->x2-box->x1+1);
 189     writeVMWareSVGAFIFO(data, box->y2-box->y1+1);
 190 }
 191
 192 VOID rectFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height)
 193 {
 194     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_FILL);
 195     writeVMWareSVGAFIFO(data, color);
 196     writeVMWareSVGAFIFO(data, x);
 197     writeVMWareSVGAFIFO(data, y);
 198     writeVMWareSVGAFIFO(data, width);
 199     writeVMWareSVGAFIFO(data, height);
 200     syncVMWareSVGAFIFO(data);
 201 }
 202
 203 VOID ropFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height, ULONG mode)
 204 {
 205     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_FILL);
 206     writeVMWareSVGAFIFO(data, color);
 207     writeVMWareSVGAFIFO(data, x);
 208     writeVMWareSVGAFIFO(data, y);
 209     writeVMWareSVGAFIFO(data, width);
 210     writeVMWareSVGAFIFO(data, height);
 211     writeVMWareSVGAFIFO(data, mode);
 212     syncVMWareSVGAFIFO(data);
 213 }
 214
 215 VOID ropCopyVMWareSVGA(struct HWData *data, LONG sx, LONG sy, LONG dx, LONG dy, ULONG width, ULONG height, ULONG mode)
 216 {
 217     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_COPY);
 218     writeVMWareSVGAFIFO(data, sx);
 219     writeVMWareSVGAFIFO(data, sy);
 220     writeVMWareSVGAFIFO(data, dx);
 221     writeVMWareSVGAFIFO(data, dy);
 222     writeVMWareSVGAFIFO(data, width);
 223     writeVMWareSVGAFIFO(data, height);
 224     writeVMWareSVGAFIFO(data, mode);
 225     syncVMWareSVGAFIFO(data);
 226 }
 227
 228 VOID defineCursorVMWareSVGA(struct HWData *data, struct MouseData *mouse)
 229 {
 230     int i;
 231     ULONG *cshape = mouse->shape;
 232     ULONG andmask[SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel)];
 233     ULONG *a, *b;
 234     UWORD *aw, *bw;
 235
 236     /* TODO: convert mouse shape to current depth */
 237     writeVMWareSVGAFIFO(data, SVGA_CMD_DEFINE_CURSOR);
 238     writeVMWareSVGAFIFO(data, 1);
 239     writeVMWareSVGAFIFO(data, 0); /* hot x value */
 240     writeVMWareSVGAFIFO(data, 0); /* hot y value */
 241     writeVMWareSVGAFIFO(data, mouse->width); /* width */
 242     writeVMWareSVGAFIFO(data, mouse->height); /* height */
 243     writeVMWareSVGAFIFO(data, data->bitsperpixel); /* bits per pixel */
 244     writeVMWareSVGAFIFO(data, data->bitsperpixel); /* bits per pixel */
 245     b = cshape;
 246     a = andmask;
 247     aw = (UWORD *)a;
 248     bw = (UWORD *)b;
 249     for (i = 0; i<(SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel)*2);i++)
 250     {
 251         *aw = *bw ? 0 : ~0;
 252
 253         aw++;
 254         bw++;
 255     }
 256     a = andmask;
 257     for (i = 0; i<SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel);i++) {
 258         writeVMWareSVGAFIFO(data, *a++);
 259     }
 260     for (i = 0; i<SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel);i++)
 261         writeVMWareSVGAFIFO(data, *cshape++);
 262     syncVMWareSVGAFIFO(data);
 263 }
 264
 265 VOID displayCursorVMWareSVGA(struct HWData *data, LONG mode)
 266 {
 267 #if 0
 268     writeVMWareSVGAFIFO(data, SVGA_CMD_DISPLAY_CURSOR);
 269     writeVMWareSVGAFIFO(data, 1);
 270     writeVMWareSVGAFIFO(data, mode);
 271     syncVMWareSVGAFIFO(data);
 272 #else
 273     vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
 274     vmwareWriteReg(data, SVGA_REG_CURSOR_ON, mode);
 275 #endif
 276 }
 277
 278 VOID moveCursorVMWareSVGA(struct HWData *data, LONG x, LONG y)
 279 {
 280 #if 0
 281     writeVMWareSVGAFIFO(data, SVGA_CMD_MOVE_CURSOR);
 282     writeVMWareSVGAFIFO(data, x);
 283     writeVMWareSVGAFIFO(data, y);
 284     syncVMWareSVGAFIFO(data);
 285 #else
 286     vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
 287     vmwareWriteReg(data, SVGA_REG_CURSOR_X, x);
 288     vmwareWriteReg(data, SVGA_REG_CURSOR_Y, y);
 289     vmwareWriteReg(data, SVGA_REG_CURSOR_ON, 1);
 290 #endif
 291 }