memory.v

   1 // Atosm Chip
   2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
   3 //
   4 // This program is free software; you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation; either version 2 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // You should have received a copy of the GNU General Public License
  15 // along with this program; if not, write to the Free Software
  16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17
  18 module ram(ack_o,
  19            clk_i,
  20            adr_i,
  21            dat_i,
  22            dat_o,
  23            rst_i,
  24            stb_i,
  25            we_i);
  26    parameter size = 1024;
  27    parameter adrbits = 10;
  28
  29    input clk_i;
  30    input adr_i;
  31    input dat_i;
  32    input rst_i;
  33    input stb_i;
  34    input we_i;
  35    output ack_o;
  36    output dat_o;
  37
  38    wire       clk_i;
  39    wire [adrbits - 1:0] adr_i;
  40    wire [7:0] dat_i;
  41    wire       rst_i;
  42    wire       stb_i;
  43    wire       we_i;
  44
  45    wire       ack_o;
  46    wire [7:0] dat_o;
  47
  48    reg [7:0]  memory [0:size - 1];
  49
  50    assign     ack_o = stb_i;
  51    assign     dat_o = memory[adr_i];
  52
  53    always @ (posedge clk_i)
  54      if (stb_i == 1'b1 && we_i == 1'b1)
  55        memory[adr_i] = dat_i;
  56
  57 endmodule
  58
  59 module rom(ack_o,
  60            clk_i,
  61            adr_i,
  62            dat_o,
  63            rst_i,
  64            stb_i);
  65    parameter size = 1024;
  66    parameter adrbits = 10;
  67
  68    input clk_i;
  69    input adr_i;
  70    input rst_i;
  71    input stb_i;
  72    output ack_o;
  73    output dat_o;
  74
  75    wire       clk_i;
  76    wire [adrbits - 1:0] adr_i;
  77    wire       rst_i;
  78    wire       stb_i;
  79
  80    wire       ack_o;
  81    wire [7:0] dat_o;
  82
  83    reg [7:0]  memory [0:size - 1];
  84
  85    assign     ack_o = stb_i;
  86    assign     dat_o = memory[adr_i];
  87
  88 endmodule