cpu6502_tb.v

   1 // Atosm Chip
   2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
   3 //
   4 // This program is free software; you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation; either version 2 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // You should have received a copy of the GNU General Public License
  15 // along with this program; if not, write to the Free Software
  16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17
  18 `include "cpu6502.v"
  19 `include "memory.v"
  20
  21
  22 module memory(ack_o,
  23               clk_i,
  24               adr_i,
  25               dat_i,
  26               dat_o,
  27               rst_i,
  28               stb_i,
  29               we_i);
  30    input clk_i;
  31    input adr_i;
  32    input dat_i;
  33    input rst_i;
  34    input stb_i;
  35    input we_i;
  36    output ack_o;
  37    output dat_o;
  38
  39    wire       clk_i;
  40    wire [15:0] adr_i;
  41    wire [7:0] dat_i;
  42    wire       rst_i;
  43    wire       stb_i;
  44    wire       we_i;
  45
  46    wire       ack_o;
  47    wire [7:0] dat_o;
  48
  49    wire       ramstb;
  50    wire       romstb;
  51    wire       ramack_o;
  52    wire       romack_o;
  53    wire [7:0] ramdat_o;
  54    wire [7:0] romdat_o;
  55
  56    ram u_ram(.clk_i(clk_i),
  57              .adr_i(adr_i[9:0]),
  58              .dat_i(dat_i),
  59              .rst_i(rst_i),
  60              .stb_i(ramstb),
  61              .we_i(we_i),
  62              .ack_o(ramack_o),
  63              .dat_o(ramdat_o));
  64
  65    defparam    u_rom.size = 'h1000;
  66    defparam    u_rom.adrbits = 12;
  67
  68    rom u_rom(.clk_i(clk_i),
  69              .adr_i(adr_i[11:0]),
  70              .rst_i(rst_i),
  71              .stb_i(romstb),
  72              .ack_o(romack_o),
  73              .dat_o(romdat_o));
  74
  75    assign     ack_o = ramack_o | romack_o;
  76    assign     dat_o = ramstb ? ramdat_o : romdat_o;
  77
  78    assign ramstb = stb_i & (adr_i[15:10] == 6'b0);
  79    assign romstb = stb_i & (adr_i[15:12] == 'hf);
  80
  81 endmodule
  82
  83 module cpu6502_test_reg(clk_i, rst_i,
  84                         adr_i, dat_i,
  85                         stb_i, we_i,
  86                         ack_o,
  87                         test_seq_o,
  88                         test_done_o, test_res_o, test_finish_o);
  89    input clk_i, rst_i;
  90    input adr_i, dat_i;
  91    input stb_i, we_i;
  92
  93    output ack_o;
  94    output test_seq_o;
  95    output test_done_o, test_res_o, test_finish_o;
  96
  97    wire   clk_i, rst_i;
  98    wire [2:0] adr_i;
  99    wire [7:0] dat_i;
 100    wire       stb_i, we_i;
 101    wire       ack_o;
 102
 103    reg [15:0] test_seq_o;
 104    wire       test_done_o, test_res_o;
 105    reg        test_finish_o;
 106
 107    assign     ack_o = stb_i;
 108
 109    always @ (posedge clk_i)
 110      if (rst_i)
 111        test_finish_o <= 0;
 112      else if (stb_i && we_i && adr_i == 1)
 113        test_finish_o <= 1;
 114
 115    always @ (posedge clk_i)
 116      if (stb_i && we_i)
 117        if (adr_i == 4)
 118          test_seq_o[7:0] <= dat_i;
 119        else if (adr_i == 5)
 120          test_seq_o[15:8] <= dat_i;
 121
 122    assign     test_done_o = (stb_i && we_i && adr_i == 0);
 123    assign     test_res_o = dat_i[0];
 124 endmodule
 125
 126 module cpu6502_tb();
 127    reg clk_o;
 128    reg rst_o;
 129    wire [15:0] adr;
 130    wire [7:0]  cpudat_i;
 131    wire [7:0]  cpudat_o;
 132    wire        cpu_stb_o;
 133    wire        memory_stb, test_reg_stb;
 134    wire        cpu_cyc_o;
 135    wire        we;
 136    wire        ack;
 137    wire        memory_ack, test_reg_ack;
 138
 139    wire [15:0] test_seq;
 140    wire        test_done, test_res, test_finish;
 141
 142    reg         ok;
 143
 144    initial begin
 145       $readmemh("tests/cpu_test.memh", u_memory.u_rom.memory);
 146       //$monitor("%h %h a=%h %b %h %h", u_cpu.pc, u_cpu.ir, u_cpu.acc,
 147         //       u_cpu.regf, adr, u_cpu.dat_o);
 148       ok = 1;
 149       clk_o = 1;
 150       rst_o = 0;
 151       #5 rst_o = 1;
 152       #10 rst_o = 0;
 153    end
 154
 155    always @ (posedge clk_o) begin
 156       if (test_finish) begin
 157          if (ok)
 158            $display("OK");
 159          else
 160            $display("FAILED");
 161          $finish;
 162       end
 163       if (test_done)
 164         if (test_res)
 165           $display("Test at %d: PASSED", test_seq);
 166         else begin
 167            $display("Test at %d: FAILED", test_seq);
 168            ok <= 0;
 169         end
 170    end
 171
 172    always begin
 173       #5 clk_o = ~clk_o;
 174    end
 175
 176    assign memory_stb = cpu_stb_o && cpu_cyc_o &&
 177                        (adr[15:10] == 0 || adr[15:12] == 'hf);
 178    assign test_reg_stb = cpu_stb_o && cpu_cyc_o && (adr[15:8] == 8'hee);
 179
 180    assign ack = memory_ack | test_reg_ack;
 181
 182    memory u_memory(.clk_i(clk_o),
 183                    .adr_i(adr),
 184                    .dat_i(cpudat_o),
 185                    .rst_i(rst_o),
 186                    .stb_i(memory_stb),
 187                    .we_i(we),
 188                    .ack_o(memory_ack),
 189                    .dat_o(cpudat_i));
 190
 191    cpu6502_test_reg test_reg(.clk_i(clk_o),
 192                              .rst_i(rst_o),
 193                              .adr_i(adr[2:0]),
 194                              .dat_i(cpudat_o),
 195                              .stb_i(test_reg_stb),
 196                              .we_i(we),
 197                              .ack_o(test_reg_ack),
 198                              .test_seq_o(test_seq),
 199                              .test_done_o(test_done),
 200                              .test_res_o(test_res),
 201                              .test_finish_o(test_finish));
 202
 203    cpu6502 u_cpu(.clk_i(clk_o),
 204                  .adr_o(adr),
 205                  .dat_i(cpudat_i),
 206                  .rst_i(rst_o),
 207                  .stb_o(cpu_stb_o),
 208                  .cyc_o(cpu_cyc_o),
 209                  .we_o(we),
 210                  .ack_i(ack),
 211                  .dat_o(cpudat_o));
 212
 213 endmodule // cpu6502_tb