makes GPIO_PIN_RST optional for the sx1276
[ExpressLRS.git] / src / lib / SX127xDriver / SX127xHal.h
blob9a0a30cdc3e0fb328c2fd78fbcbb96e778d41bd7
1 #pragma once
3 #include "targets.h"
4 #include "SX127xRegs.h"
5 #ifndef UNIT_TEST
6 #include <SPI.h>
7 #endif
9 class SX127xHal
12 public:
13 static SX127xHal *instance;
15 SX127xHal();
17 void init();
18 void end();
20 static void ICACHE_RAM_ATTR dioISR();
21 void (*IsrCallback)(); //function pointer for callback
23 void ICACHE_RAM_ATTR TXenable();
24 void ICACHE_RAM_ATTR RXenable();
25 void ICACHE_RAM_ATTR TXRXdisable();
27 uint8_t ICACHE_RAM_ATTR getRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
28 uint8_t ICACHE_RAM_ATTR readRegister(uint8_t reg);
29 void ICACHE_RAM_ATTR readRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t *inBytes);
31 uint8_t ICACHE_RAM_ATTR setRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0);
33 void ICACHE_RAM_ATTR writeRegister(uint8_t reg, uint8_t data);
34 void ICACHE_RAM_ATTR writeRegisterFIFO(volatile uint8_t *data, uint8_t numBytes);
35 void ICACHE_RAM_ATTR readRegisterFIFO(volatile uint8_t *data, uint8_t numBytes);
36 void ICACHE_RAM_ATTR writeRegisterBurst(uint8_t reg, uint8_t *data, uint8_t numBytes);