src/variants/L432K/variant_L432KB.cpp

   1 /*
   2   Copyright (c) 2011 Arduino.  All right reserved.
   3
   4   This library is free software; you can redistribute it and/or
   5   modify it under the terms of the GNU Lesser General Public
   6   License as published by the Free Software Foundation; either
   7   version 2.1 of the License, or (at your option) any later version.
   8
   9   This library is distributed in the hope that it will be useful,
  10   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  12   See the GNU Lesser General Public License for more details.
  13
  14   You should have received a copy of the GNU Lesser General Public
  15   License along with this library; if not, write to the Free Software
  16   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17 */
  18
  19 #include "pins_arduino.h"
  20
  21 #ifdef __cplusplus
  22 extern "C" {
  23 #endif
  24
  25 #include <string.h>
  26
  27 // Pin number
  28 const PinName digitalPin[] = {
  29   PA_10, //D0
  30   PA_9,  //D1
  31   PA_12, //D2
  32   PB_0,  //D3
  33   PB_7,  //D4
  34   PB_6,  //D5
  35   PB_1,  //D6
  36   PC_14, //D7 - By default, SB6 open PF0/PC14 not connected to D7
  37   PC_15, //D8 - By default, SB8 open PF1/PC15 not connected to D8
  38   PA_8,  //D9
  39   PA_11, //D10
  40   PB_5,  //D11
  41   PB_4,  //D12
  42   PB_3,  //D13 - LED
  43   PA_0,  //D14/A0
  44   PA_1,  //D15/A1
  45   PA_3,  //D16/A2
  46   PA_4,  //D17/A3
  47   PA_5,  //D18/A4
  48   PA_6,  //D19/A5
  49   PA_7,  //D20/A6
  50   PA_2,  //D21/A7 - STLink Tx
  51   PA_15  //D22 - STLink Rx
  52 };
  53
  54 // If analog pins are not contiguous in the digitalPin array:
  55 // Add the analogInputPin array without defining NUM_ANALOG_FIRST
  56 // Analog (Ax) pin number array
  57 // where x is the index to retrieve the digital pin number
  58 const uint32_t analogInputPin[] = {
  59   PA0,
  60   PA1,
  61   PA3,
  62   PA4,
  63   PA5,
  64   PA6,
  65   PA7
  66 };
  67
  68 #ifdef __cplusplus
  69 }
  70 #endif
  71
  72 // ----------------------------------------------------------------------------
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 /**
  79   * @brief  System Clock Configuration
  80   *         The system Clock is configured as follows :
  81   *            System Clock source            = PLL (MSI)
  82   *            SYSCLK(Hz)                     = 80000000
  83   *            HCLK(Hz)                       = 80000000
  84   *            AHB Prescaler                  = 1
  85   *            APB1 Prescaler                 = 1
  86   *            APB2 Prescaler                 = 1
  87   *            MSI Frequency(Hz)              = 4000000
  88   *            PLL_M                          = 1
  89   *            PLL_N                          = 40
  90   *            PLL_R                          = 2
  91   *            PLL_P                          = 7
  92   *            PLL_Q                          = 4
  93   *            Flash Latency(WS)              = 4
  94   * @param  None
  95   * @retval None
  96   */
  97 WEAK void SystemClock_Config(void)
  98 {
  99   RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
 100   RCC_OscInitTypeDef RCC_OscInitStruct = {};
 101
 102 #if USE_HSI
 103   RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
 104
 105   memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitTypeDef));
 106   memset(&RCC_ClkInitStruct, 0, sizeof(RCC_ClkInitTypeDef));
 107   memset(&PeriphClkInit, 0, sizeof(RCC_PeriphCLKInitTypeDef));
 108
 109   /* Enable Power Control clock */
 110   __HAL_RCC_PWR_CLK_ENABLE();
 111
 112   /* The voltage scaling allows optimizing the power consumption when the device is
 113      clocked below the maximum system frequency, to update the voltage scaling value
 114      regarding system frequency refer to product datasheet.  */
 115   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 116
 117   /* Enable HSI Oscillator and activate PLL with HSI as source */
 118   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 119   RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
 120   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 121   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 122   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 123   RCC_OscInitStruct.PLL.PLLM = 1;  // 16MHz
 124   RCC_OscInitStruct.PLL.PLLN = 10; // 10 * 16MHz
 125   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; // 160MHz / 2
 126   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; // 160MHz / 7
 127   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; // 160MHz / 4
 128   RCC_OscInitStruct.HSICalibrationValue = 0x10;
 129   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 130     //Error_Handler();
 131     while (1);
 132
 133   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
 134      clocks dividers */
 135   RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 136   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 137   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 138   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 139   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 140   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 141     //Error_Handler();
 142     while (1);
 143
 144   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2;
 145   PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 146   PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 147   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 148     //Error_Handler();
 149     while (1);
 150
 151   HAL_ResumeTick();
 152
 153
 154 #else // !USE_HSI
 155
 156   /* MSI is enabled after System reset, activate PLL with MSI as source */
 157   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
 158   RCC_OscInitStruct.MSIState = RCC_MSI_ON;
 159
 160   RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
 161   RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
 162   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 163   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
 164   RCC_OscInitStruct.PLL.PLLM = 1;
 165   RCC_OscInitStruct.PLL.PLLN = 40;
 166   RCC_OscInitStruct.PLL.PLLR = 2;
 167   RCC_OscInitStruct.PLL.PLLP = 7;
 168   RCC_OscInitStruct.PLL.PLLQ = 4;
 169
 170   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 171     /* Initialization Error */
 172     while (1);
 173   }
 174
 175   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
 176      clocks dividers */
 177   RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 178   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 179   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 180   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 181   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 182   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
 183     /* Initialization Error */
 184     while (1);
 185   }
 186
 187 #endif // USE_HSI
 188 }
 189
 190 #ifdef __cplusplus
 191 }
 192 #endif