src/lib/RFAMP/RFAMP_hal.cpp

   1 #ifndef UNIT_TEST
   2
   3 #include "RFAMP_hal.h"
   4 #include "logging.h"
   5
   6 RFAMP_hal *RFAMP_hal::instance = NULL;
   7
   8 RFAMP_hal::RFAMP_hal()
   9 {
  10     instance = this;
  11 }
  12
  13 void RFAMP_hal::init()
  14 {
  15     DBGLN("RFAMP_hal Init");
  16
  17 #if defined(PLATFORM_ESP32)
  18     #define SET_BIT(n) ((n != UNDEF_PIN) ? 1ULL << n : 0)
  19
  20     txrx_disable_clr_bits = 0;
  21     txrx_disable_clr_bits |= SET_BIT(GPIO_PIN_PA_ENABLE);
  22     txrx_disable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE);
  23     txrx_disable_clr_bits |= SET_BIT(GPIO_PIN_TX_ENABLE);
  24     txrx_disable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE_2);
  25     txrx_disable_clr_bits |= SET_BIT(GPIO_PIN_TX_ENABLE_2);
  26
  27     tx1_enable_set_bits = 0;
  28     tx1_enable_clr_bits = 0;
  29     tx1_enable_set_bits |= SET_BIT(GPIO_PIN_PA_ENABLE);
  30     tx1_enable_set_bits |= SET_BIT(GPIO_PIN_TX_ENABLE);
  31     tx1_enable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE);
  32     tx1_enable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE_2);
  33
  34     tx2_enable_set_bits = 0;
  35     tx2_enable_clr_bits = 0;
  36     tx2_enable_set_bits |= SET_BIT(GPIO_PIN_PA_ENABLE);
  37     tx2_enable_set_bits |= SET_BIT(GPIO_PIN_TX_ENABLE_2);
  38     tx2_enable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE_2);
  39     tx2_enable_clr_bits |= SET_BIT(GPIO_PIN_RX_ENABLE);
  40
  41     tx_all_enable_set_bits = 0;
  42     tx_all_enable_clr_bits = 0;
  43     tx_all_enable_set_bits = tx1_enable_set_bits | tx2_enable_set_bits;
  44     tx_all_enable_clr_bits = tx1_enable_clr_bits | tx2_enable_clr_bits;
  45
  46     rx_enable_set_bits = 0;
  47     rx_enable_clr_bits = 0;
  48     rx_enable_set_bits |= SET_BIT(GPIO_PIN_PA_ENABLE);
  49     rx_enable_set_bits |= SET_BIT(GPIO_PIN_RX_ENABLE);
  50     rx_enable_set_bits |= SET_BIT(GPIO_PIN_RX_ENABLE_2);
  51     rx_enable_clr_bits |= SET_BIT(GPIO_PIN_TX_ENABLE);
  52     rx_enable_clr_bits |= SET_BIT(GPIO_PIN_TX_ENABLE_2);
  53 #else
  54     rx_enabled = false;
  55     tx1_enabled = false;
  56     tx2_enabled = false;
  57 #endif
  58
  59     if (GPIO_PIN_PA_ENABLE != UNDEF_PIN)
  60     {
  61         DBGLN("Use PA enable pin: %d", GPIO_PIN_PA_ENABLE);
  62         pinMode(GPIO_PIN_PA_ENABLE, OUTPUT);
  63         digitalWrite(GPIO_PIN_PA_ENABLE, LOW);
  64     }
  65
  66     if (GPIO_PIN_TX_ENABLE != UNDEF_PIN)
  67     {
  68         DBGLN("Use TX pin: %d", GPIO_PIN_TX_ENABLE);
  69         pinMode(GPIO_PIN_TX_ENABLE, OUTPUT);
  70         digitalWrite(GPIO_PIN_TX_ENABLE, LOW);
  71     }
  72
  73     if (GPIO_PIN_RX_ENABLE != UNDEF_PIN)
  74     {
  75         DBGLN("Use RX pin: %d", GPIO_PIN_RX_ENABLE);
  76         pinMode(GPIO_PIN_RX_ENABLE, OUTPUT);
  77         digitalWrite(GPIO_PIN_RX_ENABLE, LOW);
  78     }
  79
  80     if (GPIO_PIN_TX_ENABLE_2 != UNDEF_PIN)
  81     {
  82         DBGLN("Use TX_2 pin: %d", GPIO_PIN_TX_ENABLE_2);
  83         pinMode(GPIO_PIN_TX_ENABLE_2, OUTPUT);
  84         digitalWrite(GPIO_PIN_TX_ENABLE_2, LOW);
  85     }
  86
  87     if (GPIO_PIN_RX_ENABLE_2 != UNDEF_PIN)
  88     {
  89         DBGLN("Use RX_2 pin: %d", GPIO_PIN_RX_ENABLE_2);
  90         pinMode(GPIO_PIN_RX_ENABLE_2, OUTPUT);
  91         digitalWrite(GPIO_PIN_RX_ENABLE_2, LOW);
  92     }
  93 }
  94
  95 void ICACHE_RAM_ATTR RFAMP_hal::TXenable(SX12XX_Radio_Number_t radioNumber)
  96 {
  97 #if defined(PLATFORM_ESP32_C3)
  98     if (radioNumber == SX12XX_Radio_All)
  99     {
 100         GPIO.out_w1ts.out_w1ts = tx_all_enable_set_bits;
 101         GPIO.out_w1tc.out_w1tc = tx_all_enable_clr_bits;
 102     }
 103     else if (radioNumber == SX12XX_Radio_2)
 104     {
 105         GPIO.out_w1ts.out_w1ts = tx2_enable_set_bits;
 106         GPIO.out_w1tc.out_w1tc = tx2_enable_clr_bits;
 107     }
 108     else
 109     {
 110         GPIO.out_w1ts.out_w1ts = tx1_enable_set_bits;
 111         GPIO.out_w1tc.out_w1tc = tx1_enable_clr_bits;
 112     }
 113 #elif defined(PLATFORM_ESP32)
 114     if (radioNumber == SX12XX_Radio_All)
 115     {
 116         GPIO.out_w1ts = (uint32_t)tx_all_enable_set_bits;
 117         GPIO.out_w1tc = tx_all_enable_clr_bits;
 118
 119         GPIO.out1_w1ts.data = tx_all_enable_set_bits >> 32;
 120         GPIO.out1_w1tc.data = tx_all_enable_clr_bits >> 32;
 121     }
 122     else if (radioNumber == SX12XX_Radio_2)
 123     {
 124         GPIO.out_w1ts = tx2_enable_set_bits;
 125         GPIO.out_w1tc = tx2_enable_clr_bits;
 126
 127         GPIO.out1_w1ts.data = tx2_enable_set_bits >> 32;
 128         GPIO.out1_w1tc.data = tx2_enable_clr_bits >> 32;
 129     }
 130     else
 131     {
 132         GPIO.out_w1ts = tx1_enable_set_bits;
 133         GPIO.out_w1tc = tx1_enable_clr_bits;
 134
 135         GPIO.out1_w1ts.data = tx1_enable_set_bits >> 32;
 136         GPIO.out1_w1tc.data = tx1_enable_clr_bits >> 32;
 137     }
 138 #else
 139     if (!tx1_enabled && !tx2_enabled && !rx_enabled)
 140     {
 141         if (GPIO_PIN_PA_ENABLE != UNDEF_PIN)
 142         {
 143             digitalWrite(GPIO_PIN_PA_ENABLE, HIGH);
 144         }
 145     }
 146     if (rx_enabled)
 147     {
 148         if (GPIO_PIN_RX_ENABLE != UNDEF_PIN)
 149         {
 150             digitalWrite(GPIO_PIN_RX_ENABLE, LOW);
 151         }
 152         if (GPIO_PIN_RX_ENABLE_2 != UNDEF_PIN)
 153         {
 154             digitalWrite(GPIO_PIN_RX_ENABLE_2, LOW);
 155         }
 156         rx_enabled = false;
 157     }
 158     if (radioNumber == SX12XX_Radio_1 && !tx1_enabled)
 159     {
 160         if (GPIO_PIN_TX_ENABLE != UNDEF_PIN)
 161         {
 162             digitalWrite(GPIO_PIN_TX_ENABLE, HIGH);
 163         }
 164         if (GPIO_PIN_TX_ENABLE_2 != UNDEF_PIN)
 165         {
 166             digitalWrite(GPIO_PIN_TX_ENABLE_2, LOW);
 167         }
 168         tx1_enabled = true;
 169         tx2_enabled = false;
 170     }
 171     if (radioNumber == SX12XX_Radio_2 && !tx2_enabled)
 172     {
 173         if (GPIO_PIN_TX_ENABLE != UNDEF_PIN)
 174         {
 175             digitalWrite(GPIO_PIN_TX_ENABLE, LOW);
 176         }
 177         if (GPIO_PIN_TX_ENABLE_2 != UNDEF_PIN)
 178         {
 179             digitalWrite(GPIO_PIN_TX_ENABLE_2, HIGH);
 180         }
 181         tx1_enabled = false;
 182         tx2_enabled = true;
 183     }
 184 #endif
 185 }
 186
 187 void ICACHE_RAM_ATTR RFAMP_hal::RXenable()
 188 {
 189 #if defined(PLATFORM_ESP32_C3)
 190     GPIO.out_w1ts.out_w1ts = rx_enable_set_bits;
 191     GPIO.out_w1tc.out_w1tc = rx_enable_clr_bits;
 192 #elif defined(PLATFORM_ESP32)
 193     GPIO.out_w1ts = rx_enable_set_bits;
 194     GPIO.out_w1tc = rx_enable_clr_bits;
 195
 196     GPIO.out1_w1ts.data = rx_enable_set_bits >> 32;
 197     GPIO.out1_w1tc.data = rx_enable_clr_bits >> 32;
 198 #else
 199     if (!rx_enabled)
 200     {
 201         if (!tx1_enabled && !tx2_enabled && GPIO_PIN_PA_ENABLE != UNDEF_PIN)
 202             digitalWrite(GPIO_PIN_PA_ENABLE, HIGH);
 203
 204         if (tx1_enabled && GPIO_PIN_TX_ENABLE != UNDEF_PIN)
 205         {
 206             digitalWrite(GPIO_PIN_TX_ENABLE, LOW);
 207             tx1_enabled = false;
 208         }
 209
 210         if (tx2_enabled && GPIO_PIN_TX_ENABLE_2 != UNDEF_PIN)
 211         {
 212             digitalWrite(GPIO_PIN_TX_ENABLE_2, LOW);
 213             tx2_enabled = false;
 214         }
 215
 216         if (GPIO_PIN_RX_ENABLE != UNDEF_PIN)
 217         {
 218             digitalWrite(GPIO_PIN_RX_ENABLE, HIGH);
 219         }
 220         if (GPIO_PIN_RX_ENABLE_2 != UNDEF_PIN)
 221         {
 222             digitalWrite(GPIO_PIN_RX_ENABLE_2, HIGH);
 223         }
 224
 225         rx_enabled = true;
 226     }
 227 #endif
 228 }
 229
 230 void ICACHE_RAM_ATTR RFAMP_hal::TXRXdisable()
 231 {
 232 #if defined(PLATFORM_ESP32_C3)
 233     GPIO.out_w1tc.out_w1tc = txrx_disable_clr_bits;
 234 #elif defined(PLATFORM_ESP32)
 235     GPIO.out_w1tc = txrx_disable_clr_bits;
 236     GPIO.out1_w1tc.data = txrx_disable_clr_bits >> 32;
 237 #else
 238     if (rx_enabled)
 239     {
 240         if (GPIO_PIN_RX_ENABLE != UNDEF_PIN)
 241         {
 242             digitalWrite(GPIO_PIN_RX_ENABLE, LOW);
 243         }
 244         if (GPIO_PIN_RX_ENABLE_2 != UNDEF_PIN)
 245         {
 246             digitalWrite(GPIO_PIN_RX_ENABLE_2, LOW);
 247         }
 248         rx_enabled = false;
 249     }
 250     if (tx1_enabled)
 251     {
 252         if (GPIO_PIN_PA_ENABLE != UNDEF_PIN)
 253         {
 254             digitalWrite(GPIO_PIN_PA_ENABLE, LOW);
 255         }
 256         if (GPIO_PIN_TX_ENABLE != UNDEF_PIN)
 257         {
 258             digitalWrite(GPIO_PIN_TX_ENABLE, LOW);
 259         }
 260         tx1_enabled = false;
 261     }
 262     if (tx2_enabled)
 263     {
 264         if (GPIO_PIN_PA_ENABLE != UNDEF_PIN)
 265         {
 266             digitalWrite(GPIO_PIN_PA_ENABLE, LOW);
 267         }
 268         if (GPIO_PIN_TX_ENABLE_2 != UNDEF_PIN)
 269         {
 270             digitalWrite(GPIO_PIN_TX_ENABLE_2, LOW);
 271         }
 272         tx2_enabled = false;
 273     }
 274 #endif
 275 }
 276
 277 #endif // UNIT_TEST