src/lib/SPIEx/SPIEx.h

   1 #include "targets.h"
   2 #include <SPI.h>
   3
   4 /**
   5  * @brief An extension to the platform SPI class that provides some performance enhancements.
   6  *
   7  * 1. The provided data buffer is expected to be word-aligned and word-padded, this allow the
   8  *    data to be copied to the SPI fifo in word-sized chunks.
   9  * 2. The wait for non-busy is removed from the end of the write call so the processor can
  10  *    continue to do work while the SPI module is pumping the data from the FIFO to the external
  11  *    device.
  12  */
  13 class SPIExClass : public SPIClass
  14 {
  15 public:
  16 #if defined(PLATFORM_ESP32)
  17     explicit SPIExClass(uint8_t spi_bus=HSPI) : SPIClass(spi_bus) {}
  18 #else
  19     explicit SPIExClass() : SPIClass() {}
  20 #endif
  21
  22     /**
  23      * @brief Perform an SPI read operation on the SPI bus.
  24      *
  25      * If the SPI bus is busy the processor waits for the current operation to complete before starting
  26      * this operation.
  27      * Once the SPI bus is free, the data is copied to the SPI fifo and the processor waits for the operation
  28      * to complete then copies the incoming data back into the provided data buffer.
  29      *
  30      * @param cs_mask mask of CS pins to enable for this operation
  31      * @param data word-aligned and padded data buffer
  32      * @param size the number of bytes to be read into in the data buffer
  33      */
  34     void inline ICACHE_RAM_ATTR read(uint8_t cs_mask, uint8_t *data, uint32_t size) { _transfer(cs_mask, data, size, true); }
  35
  36     /**
  37      * @brief Perform an SPI write operation on the SPI bus.
  38      *
  39      * If the SPI bus is busy the processor waits for the current operation to complete before starting
  40      * this operation.
  41      * One the SPI bus is not busy, it copies the data to the SPI fifo then returns without waiting for
  42      * the operation to complete allowing the processor to do other work.
  43      *
  44      * @param cs_mask mask of CS pins to enable for this operation
  45      * @param data word-aligned and padded data buffer
  46      * @param size the number of bytes to be written to the SPI device
  47      */
  48     void inline ICACHE_RAM_ATTR write(uint8_t cs_mask, uint8_t * data, uint32_t size) { _transfer(cs_mask, data, size, false); }
  49
  50 private:
  51     void _transfer(uint8_t cs_mask, uint8_t *data, uint32_t size, bool reading);
  52 };
  53
  54 extern SPIExClass SPIEx;