src/variants/R9MM/variant_R9MM.cpp

   1 /*
   2   Copyright (c) 2011 Arduino.  All right reserved.
   3
   4   This library is free software; you can redistribute it and/or
   5   modify it under the terms of the GNU Lesser General Public
   6   License as published by the Free Software Foundation; either
   7   version 2.1 of the License, or (at your option) any later version.
   8
   9   This library is distributed in the hope that it will be useful,
  10   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  12   See the GNU Lesser General Public License for more details.
  13
  14   You should have received a copy of the GNU Lesser General Public
  15   License along with this library; if not, write to the Free Software
  16   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17 */
  18
  19 #include "pins_arduino.h"
  20
  21 #ifdef __cplusplus
  22 extern "C" {
  23 #endif
  24
  25 // Pin number
  26 const PinName digitalPin[] = {
  27   PA_3,  //D0
  28   PA_2,  //D1
  29   PA_10, //D2
  30   PB_3,  //D3
  31   PB_5,  //D4
  32   PB_4,  //D5
  33   PB_10, //D6
  34   PA_8,  //D7
  35   PA_9,  //D8
  36   PC_7,  //D9
  37   PB_6,  //D10
  38   PA_7,  //D11
  39   PA_6,  //D12
  40   PA_5,  //D13 - LED
  41   PB_9,  //D14
  42   PB_8,  //D15
  43   // ST Morpho
  44   // CN7 Left Side
  45   PC_10, //D16
  46   PC_12, //D17
  47   NC,   //D18 - BOOT0
  48   PA_13, //D19 - SWD
  49   PA_14, //D20 - SWD
  50   PA_15, //D21
  51   PB_7,  //D22
  52   PC_13, //D23
  53   PC_14, //D24
  54   PC_15, //D25
  55   PD_0,  //D26
  56   PD_1,  //D27
  57   PC_2,  //D28
  58   PC_3,  //D29
  59   // CN7 Right Side
  60   PC_11, //D30
  61   PD_2,  //D31
  62   // CN10 Left Side
  63   PC_9,  //D32
  64   // CN10 Right side
  65   PC_8,  //D33
  66   PC_6,  //D34
  67   PC_5,  //D35
  68   PA_12, //D36
  69   PA_11, //D37
  70   PB_12, //D38
  71   PB_11, //D39
  72   PB_2,  //D40
  73   PB_1,  //D41
  74   PB_15, //D42
  75   PB_14, //D43
  76   PB_13, //D44
  77   PC_4,  //D45
  78   PA_0,  //D46/A0
  79   PA_1,  //D47/A1
  80   PA_4,  //D48/A2
  81   PB_0,  //D49/A3
  82   PC_1,  //D50/A4
  83   PC_0,  //D51/A5
  84   // Duplicated pins in order to be aligned with PinMap_ADC
  85   PA_7,  //D52/A6 = D11
  86   PA_6,  //D53/A7 = D12
  87   PA_5,  //D54/A8 = D13
  88   PC_2,  //D55/A9 = D28
  89   PC_3,  //D56/A10 = D29
  90   PB_1,  //D57/A11 = D41
  91   PC_4,  //D58/A12 = D45
  92   PC_5   //D59/A13 = D35
  93 };
  94
  95 // If analog pins are not contiguous in the digitalPin array:
  96 // Add the analogInputPin array without defining NUM_ANALOG_FIRST
  97 // Analog (Ax) pin number array
  98 // where x is the index to retrieve the digital pin number
  99 const uint32_t analogInputPin[] = {
 100   PA0,
 101   PA1,
 102   PA4,
 103   PB0,
 104   PC1,
 105   PC0,
 106   PA7,
 107   PA6,
 108   PA5,
 109   PC2,
 110   PC3,
 111   PB1,
 112   PC4,
 113   PC5
 114 };
 115
 116 #ifdef __cplusplus
 117 }
 118 #endif
 119
 120 // ----------------------------------------------------------------------------
 121
 122 #ifdef __cplusplus
 123 extern "C" {
 124 #endif
 125
 126 /**
 127   * @brief  System Clock Configuration
 128   *         The system Clock is configured as follow :
 129   *            System Clock source            = PLL (HSI)
 130   *            SYSCLK(Hz)                     = 64000000
 131   *            HCLK(Hz)                       = 64000000
 132   *            AHB Prescaler                  = 1
 133   *            APB1 Prescaler                 = 2
 134   *            APB2 Prescaler                 = 1
 135   *            PLL_Source                     = HSI
 136   *            PLL_Mul                        = 16
 137   *            Flash Latency(WS)              = 2
 138   *            ADC Prescaler                  = 6
 139   * @param  None
 140   * @retval None
 141   */
 142
 143 //64MHZ Internal Clock
 144 // WEAK void SystemClock_Config(void)
 145 // {
 146   // RCC_OscInitTypeDef RCC_OscInitStruct;
 147   // RCC_ClkInitTypeDef RCC_ClkInitStruct;
 148   // RCC_PeriphCLKInitTypeDef PeriphClkInit;
 149
 150   // /* Initializes the CPU, AHB and APB busses clocks */
 151   // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 152   // RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 153   // RCC_OscInitStruct.HSICalibrationValue = 16;
 154   // RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 155   // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
 156   // RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
 157   // if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 158     // Error_Handler();
 159   // }
 160
 161   // /* Initializes the CPU, AHB and APB busses clocks */
 162   // RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
 163                                 // | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 164   // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 165   // RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 166   // RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 167   // RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 168
 169   // if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
 170     // Error_Handler();
 171   // }
 172
 173   // PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 174   // PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 175   // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
 176     // Error_Handler();
 177   // }
 178 // }
 179
 180
 181 //72 MHz with 24Mhz ext. clock input/// (R9MM RX configuration)
 182 void SystemClock_Config(void)
 183 {
 184   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 185   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 186
 187   /** Initializes the CPU, AHB and APB busses clocks
 188   */
 189   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 190   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 191   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
 192   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 193   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 194   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 195   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
 196   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 197   {
 198     Error_Handler();
 199   }
 200   /** Initializes the CPU, AHB and APB busses clocks
 201   */
 202   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 203                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 204   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 205   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 206   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 207   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 208
 209   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 210   {
 211     Error_Handler();
 212   }
 213 }
 214
 215 #ifdef __cplusplus
 216 }
 217 #endif