| blob | 0069086109876fdf4365b6ee49133920f9e7c2dd |
1 /**************************** lpc210x.ld ********************************/\r
2 /* Copyright 2003/12/30 Aeolus Development */\r
3 /* */\r
4 /* Freely modifiable and redistributable. Modify to suit your own needs*/\r
5 /* Please remove Aeolus Development copyright for any significant */\r
6 /* modifications or add explanatory notes to explain the mods and */\r
7 /* list authour(s). */\r
8 /* */\r
9 /* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
10 /* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
11 /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
12 /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
13 /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
14 /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
15 /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
16 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
17 /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
18 /* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
19 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
20 /************************************************************************/\r
21 /*\r
22 * TLIB revision history:\r
23 * 1 lpc2119.ld 17-Jun-2004,16:08:28,`RADSETT' Original archive version\r
24 * 2 lpc2119.ld 21-Jul-2004,11:31:02,`RADSETT' Increase interrupt stack sizes.\r
25 * TLIB revision history ends.\r
26 */\r
27 \r
28 /* Search directories for libraries. Modify as needed. */\r
29 \r
30 /*\r
31 SEARCH_DIR( /home/cabrit/arm/test)\r
32 SEARCH_DIR( /usr/arm-elf/lib)\r
33 SEARCH_DIR( /home/lib/gcc-lib/i486-linux/3.3.5)\r
34 */\r
35 \r
36 /* Memory layout for processor. Modify RAM size upwards for 2105 and */\r
37 /* 2106 */\r
38 \r
39 MEMORY {\r
40 flash : ORIGIN = 0, LENGTH = 120K\r
41 ram : ORIGIN = 0x40000000, LENGTH = 16K\r
42 }\r
43 \r
44 __ram_size__ = 16K;\r
45 \r
46 __STACK_SIZE_FIQ__ = 0x100;\r
47 __STACK_SIZE_IRQ__ = 0x100;\r
48 __STACK_SIZE_SUPERVISOR__ = 0x4;\r
49 __STACK_SIZE_ABORT__ = 0x4;\r
50 __STACK_SIZE_UNDEFINED__ = 0x4;\r
51 \r
52 __stack_end__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
53 __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__ - __STACK_SIZE_ABORT__ -\r
54 __STACK_SIZE_UNDEFINED__;\r
55 __stack_end_undefined__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
56 __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__ - __STACK_SIZE_ABORT__;\r
57 __stack_end_abort__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
58 __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__;\r
59 __stack_end_supervisor__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
60 __STACK_SIZE_IRQ__;\r
61 __stack_end_irq__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__;\r
62 __stack_end_fiq__ = 0x40000000 + __ram_size__ - 4;\r
63 \r
64 \r
65 SECTIONS {\r
66 . = 0; /* Start at address 0. */\r
67 startup : { *(.startup)} >flash /* Place startup first. */\r
68 \r
69 prog : { /* Program (.text) sections */\r
70 *(.text) /* are next, then constant data.*/\r
71 *(.rodata)\r
72 *(.rodata*)\r
73 *(.glue_7)\r
74 *(.glue_7t)\r
75 } >flash\r
76 __end_of_text__ = .; /* Used by startup to find */\r
77 /* initialized vars. */\r
78 \r
79 /* Initialized data, located in ram but a copy is placed */\r
80 /* in flash so it can be used to init the ram on startup. */\r
81 .data : { \r
82 __data_beg__ = .; /* Used by startup. */\r
83 __data_beg_src__ = __end_of_text__; /* Used by startup. */\r
84 *(.data)\r
85 __data_end__ = .; /* Used by startup. */\r
86 } >ram AT>flash\r
87 \r
88 /* Unitialized data, located in ram, no copy in flash needed */\r
89 /* since startup will zero associated area in RAM. */\r
90 .bss : { \r
91 __bss_beg__ = .; /* Used by startup to find start of */\r
92 /* unitialized variables. */\r
93 *(.bss)\r
94 } >ram\r
95 /* Align here to ensure that the .bss section occupies space up to\r
96 _end. Align after .bss to ensure correct alignment even if the\r
97 .bss section disappears because there are no input sections. */\r
98 . = ALIGN(32 / 8);\r
99 }\r
100 . = ALIGN(32 / 8);\r
101 \r
102 /* Used by startup to find end of unitialized variables. */\r
103 _end = .;\r
104 _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; \r
105 PROVIDE (end = .);\r
106 \r
107 /* Libraries to link against. */\r
108 /* INPUT( -lc -lnewlib -lpc -lc -lgcc ) */\r
109 \r
110 /* Provide a default vector for any unhandled interrupts. */\r
111 PROVIDE( undefined_instruction_exception = endless_loop);\r
112 PROVIDE( software_interrupt_exception = endless_loop);\r
113 PROVIDE( prefetch_abort_exception = endless_loop);\r
114 PROVIDE( data_abort_exception = endless_loop);\r
115 PROVIDE( reserved_exception = endless_loop);\r
116 PROVIDE( interrupt_exception = endless_loop);\r
117 PROVIDE( fast_interrupt_exception = endless_loop);\r
118 \r
119 /* Provide address definitions for any peripheral registers */\r
120 /* used. */\r
121 \r
122 /* WD */\r
123 \r
124 PROVIDE( WDMOD = 0xE0000000);\r
125 PROVIDE( WDTC = 0xE0000004);\r
126 PROVIDE( WDFEED = 0xE0000008);\r
127 PROVIDE( WDTV = 0xE000000C);\r
128 \r
129 /* TIMER 0 */\r
130 \r
131 PROVIDE( T0IR = 0xE0004000);\r
132 PROVIDE( T0TCR = 0xE0004004);\r
133 PROVIDE( T0TC = 0xE0004008);\r
134 PROVIDE( T0PR = 0xE000400C);\r
135 PROVIDE( T0PC = 0xE0004010);\r
136 PROVIDE( T0MCR = 0xE0004014);\r
137 PROVIDE( T0MR0 = 0xE0004018);\r
138 PROVIDE( T0MR1 = 0xE000401C);\r
139 PROVIDE( T0MR2 = 0xE0004020);\r
140 PROVIDE( T0MR3 = 0xE0004024);\r
141 PROVIDE( T0CCR = 0xE0004028);\r
142 PROVIDE( T0CR0 = 0xE000402C);\r
143 PROVIDE( T0CR1 = 0xE0004030);\r
144 PROVIDE( T0CR2 = 0xE0004034);\r
145 PROVIDE( T0EMR = 0xE000403C);\r
146 \r
147 /* TIMER 1 */\r
148 \r
149 PROVIDE( T1IR = 0xE0008000);\r
150 PROVIDE( T1TCR = 0xE0008004);\r
151 PROVIDE( T1TC = 0xE0008008);\r
152 PROVIDE( T1PR = 0xE000800C);\r
153 PROVIDE( T1PC = 0xE0008010);\r
154 PROVIDE( T1MCR = 0xE0008014);\r
155 PROVIDE( T1MR0 = 0xE0008018);\r
156 PROVIDE( T1MR1 = 0xE000801C);\r
157 PROVIDE( T1MR2 = 0xE0008020);\r
158 PROVIDE( T1MR3 = 0xE0008024);\r
159 PROVIDE( T1CCR = 0xE0008028);\r
160 PROVIDE( T1CR0 = 0xE000802C);\r
161 PROVIDE( T1CR1 = 0xE0008030);\r
162 PROVIDE( T1CR2 = 0xE0008034);\r
163 PROVIDE( T1CR3 = 0xE0008038);\r
164 PROVIDE( T1EMR = 0xE000803C);\r
165 \r
166 /* UART 0 */\r
167 \r
168 PROVIDE( U0RBR = 0xE000C000);\r
169 PROVIDE( U0THR = 0xE000C000);\r
170 PROVIDE( U0DLL = 0xE000C000);\r
171 PROVIDE( U0IER = 0xE000C004);\r
172 PROVIDE( U0DLM = 0xE000C004);\r
173 PROVIDE( U0IIR = 0xE000C008);\r
174 PROVIDE( U0FCR = 0xE000C008);\r
175 PROVIDE( U0LCR = 0xE000C00C);\r
176 PROVIDE( U0LSR = 0xE000C014);\r
177 PROVIDE( U0SCR = 0xE000C01C);\r
178 \r
179 /* UART 1 */\r
180 \r
181 PROVIDE( U1RBR = 0xE0010000);\r
182 PROVIDE( U1THR = 0xE0010000);\r
183 PROVIDE( U1DLL = 0xE0010000);\r
184 PROVIDE( U1IER = 0xE0010004);\r
185 PROVIDE( U1DLM = 0xE0010004);\r
186 PROVIDE( U1IIR = 0xE0010008);\r
187 PROVIDE( U1FCR = 0xE0010008);\r
188 PROVIDE( U1LCR = 0xE001000C);\r
189 PROVIDE( U1MCR = 0xE0010010);\r
190 PROVIDE( U1LSR = 0xE0010014);\r
191 PROVIDE( U1MSR = 0xE0010018);\r
192 PROVIDE( U1SCR = 0xE001001C);\r
193 \r
194 /* PWM */\r
195 \r
196 PROVIDE( PWMIR = 0xE0014000);\r
197 PROVIDE( PWMTCR = 0xE0014004);\r
198 PROVIDE( PWMTC = 0xE0014008);\r
199 PROVIDE( PWMPR = 0xE001400C);\r
200 PROVIDE( PWMPC = 0xE0014010);\r
201 PROVIDE( PWMMCR = 0xE0014014);\r
202 PROVIDE( PWMMR0 = 0xE0014018);\r
203 PROVIDE( PWMMR1 = 0xE001401C);\r
204 PROVIDE( PWMMR2 = 0xE0014020);\r
205 PROVIDE( PWMMR3 = 0xE0014024);\r
206 PROVIDE( PWMMR4 = 0xE0014040);\r
207 PROVIDE( PWMMR5 = 0xE0014044);\r
208 PROVIDE( PWMMR6 = 0xE0014048);\r
209 PROVIDE( PWMPCR = 0xE001404C);\r
210 PROVIDE( PWMLER = 0xE0014050);\r
211 \r
212 /* IIC */\r
213 \r
214 PROVIDE( I2CONSET = 0xE001C000);\r
215 PROVIDE( I2STAT = 0xE001C004);\r
216 PROVIDE( I2DAT = 0xE001C008);\r
217 PROVIDE( I2ADR = 0xE001C00C);\r
218 PROVIDE( I2SCLH = 0xE001C010);\r
219 PROVIDE( I2SCLL = 0xE001C014);\r
220 PROVIDE( I2CONCLR = 0xE001C018);\r
221 \r
222 /* SPI/SPI0 */\r
223 \r
224 PROVIDE( S0PCR = 0xE0020000);\r
225 PROVIDE( S0PSR = 0xE0020004);\r
226 PROVIDE( S0PPR = 0xE0020008);\r
227 PROVIDE( S0PCCR = 0xE002000C);\r
228 PROVIDE( S0PINT = 0xE002001C);\r
229 \r
230 /* Synonyms for compatibility with the 210x series. */\r
231 PROVIDE( SPCR = 0xE0020000);\r
232 PROVIDE( SPSR = 0xE0020004);\r
233 PROVIDE( SPPR = 0xE0020008);\r
234 PROVIDE( SPCCR = 0xE002000C);\r
235 PROVIDE( SPINT = 0xE002001C);\r
236 \r
237 /* RTC */\r
238 \r
239 PROVIDE( ILR = 0xE0024000);\r
240 PROVIDE( CTC = 0xE0024004);\r
241 PROVIDE( CCR = 0xE0024008);\r
242 PROVIDE( CIIR = 0xE002400C);\r
243 PROVIDE( AMR = 0xE0024010);\r
244 PROVIDE( CTIME0 = 0xE0024014);\r
245 PROVIDE( CTIME1 = 0xE0024018);\r
246 PROVIDE( CTIME2 = 0xE002401C);\r
247 PROVIDE( SEC = 0xE0024020);\r
248 PROVIDE( MINUTE = 0xE0024024);\r
249 PROVIDE( HOUR = 0xE0024028);\r
250 PROVIDE( DOM = 0xE002402C);\r
251 PROVIDE( DOW = 0xE0024030);\r
252 PROVIDE( DOY = 0xE0024034);\r
253 PROVIDE( MONTH = 0xE0024038);\r
254 PROVIDE( YEAR = 0xE002403C);\r
255 PROVIDE( ALSEC = 0xE0024060);\r
256 PROVIDE( ALMIN = 0xE0024064);\r
257 PROVIDE( ALHOUR = 0xE0024068);\r
258 PROVIDE( ALDOM = 0xE002406C);\r
259 PROVIDE( ALDOW = 0xE0024070);\r
260 PROVIDE( ALDOY = 0xE0024074);\r
261 PROVIDE( ALMON = 0xE0024078);\r
262 PROVIDE( ALYEAR = 0xE002407C);\r
263 PROVIDE( PREINT = 0xE0024080);\r
264 PROVIDE( PREFRAC = 0xE0024084);\r
265 \r
266 /* GPIO PORT0 */\r
267 \r
268 PROVIDE( IO0PIN = 0xE0028000);\r
269 PROVIDE( IO0SET = 0xE0028004);\r
270 PROVIDE( IO0DIR = 0xE0028008);\r
271 PROVIDE( IO0CLR = 0xE002800C);\r
272 \r
273 /* Synonyms for compatibility with the 210x series. */\r
274 PROVIDE( IOPIN = 0xE0028000);\r
275 PROVIDE( IOSET = 0xE0028004);\r
276 PROVIDE( IODIR = 0xE0028008);\r
277 PROVIDE( IOCLR = 0xE002800C);\r
278 \r
279 /* GPIO PORT1 */\r
280 \r
281 PROVIDE( IO1PIN = 0xE0028010);\r
282 PROVIDE( IO1SET = 0xE0028014);\r
283 PROVIDE( IO1DIR = 0xE0028018);\r
284 PROVIDE( IO1CLR = 0xE002800C);\r
285 \r
286 /* GPIO PORT2 */\r
287 \r
288 PROVIDE( IO2PIN = 0xE0028020);\r
289 PROVIDE( IO2SET = 0xE0028024);\r
290 PROVIDE( IO2DIR = 0xE0028028);\r
291 PROVIDE( IO2CLR = 0xE002802C);\r
292 \r
293 /* GPIO PORT3 */\r
294 \r
295 PROVIDE( IO3PIN = 0xE0028030);\r
296 PROVIDE( IO3SET = 0xE0028034);\r
297 PROVIDE( IO3DIR = 0xE0028038);\r
298 PROVIDE( IO3CLR = 0xE002803C);\r
299 \r
300 /* PIN CONNECT BLOCK */\r
301 \r
302 PROVIDE( PINSEL0 = 0xE002C000);\r
303 PROVIDE( PINSEL1 = 0xE002C004);\r
304 PROVIDE( PINSEL2 = 0xE002C014);\r
305 \r
306 /* SPI1 */\r
307 \r
308 PROVIDE( S1PCR = 0xE0030000);\r
309 PROVIDE( S1PSR = 0xE0030004);\r
310 PROVIDE( S1PPR = 0xE0030008);\r
311 PROVIDE( S1PCCR = 0xE003000C);\r
312 PROVIDE( S1PINT = 0xE003001C);\r
313 \r
314 /* ADC */\r
315 \r
316 /* Renamed from AD... to prevent ld conflict. */\r
317 PROVIDE( A2DCR = 0xE0034000);\r
318 PROVIDE( A2DDR = 0xE0034004);\r
319 \r
320 /* CAN */\r
321 \r
322 PROVIDE( CAN_RECV = 0xE0038000);\r
323 PROVIDE( AFMR = 0xE003C000);\r
324 PROVIDE( SFF_sa = 0xE003C004);\r
325 PROVIDE( SFF_GRP_sa = 0xE003C008);\r
326 PROVIDE( EFF_sa = 0xE003C00C);\r
327 PROVIDE( EFF_GRP_sa = 0xE003C010);\r
328 PROVIDE( ENDofTable = 0xE003C014);\r
329 PROVIDE( LUTerrAd = 0xE003C018);\r
330 PROVIDE( LUTerr = 0xE003C01C);\r
331 PROVIDE( CANTxSR = 0xE0040000);\r
332 PROVIDE( CANRxSR = 0xE0040004);\r
333 PROVIDE( CANMSR = 0xE0040008);\r
334 \r
335 /* CAN1 Interface */\r
336 \r
337 PROVIDE( C1MOD = 0xE0044000);\r
338 PROVIDE( C1CMR = 0xE0044004);\r
339 PROVIDE( C1GSR = 0xE0044008);\r
340 PROVIDE( C1ICR = 0xE004400C);\r
341 PROVIDE( C1IER = 0xE0044010);\r
342 PROVIDE( C1BTR = 0xE0044014);\r
343 PROVIDE( C1EWL = 0xE0044018);\r
344 PROVIDE( C1SR = 0xE004401C);\r
345 PROVIDE( C1RFS = 0xE0044020);\r
346 PROVIDE( C1RID = 0xE0044024);\r
347 PROVIDE( C1RDA = 0xE0044028);\r
348 PROVIDE( C1RDB = 0xE004402C);\r
349 PROVIDE( C1TFI1 = 0xE0044030);\r
350 PROVIDE( C1TID1 = 0xE0044034);\r
351 PROVIDE( C1TDA1 = 0xE0044038);\r
352 PROVIDE( C1TDB1 = 0xE004403C);\r
353 PROVIDE( C1TFI2 = 0xE0044040);\r
354 PROVIDE( C1TID2 = 0xE0044044);\r
355 PROVIDE( C1TDA2 = 0xE0044048);\r
356 PROVIDE( C1TDB2 = 0xE004404C);\r
357 PROVIDE( C1TFI3 = 0xE0044050);\r
358 PROVIDE( C1TID3 = 0xE0044054);\r
359 PROVIDE( C1TDA3 = 0xE0044058);\r
360 PROVIDE( C1TDB3 = 0xE004405C);\r
361 \r
362 /* CAN2 Interface */\r
363 \r
364 PROVIDE( C2MOD = 0xE0048000);\r
365 PROVIDE( C2CMR = 0xE0048004);\r
366 PROVIDE( C2GSR = 0xE0048008);\r
367 PROVIDE( C2ICR = 0xE004800C);\r
368 PROVIDE( C2IER = 0xE0048010);\r
369 PROVIDE( C2BTR = 0xE0048014);\r
370 PROVIDE( C2EWL = 0xE0048018);\r
371 PROVIDE( C2SR = 0xE004801C);\r
372 PROVIDE( C2RFS = 0xE0048020);\r
373 PROVIDE( C2RID = 0xE0048024);\r
374 PROVIDE( C2RDA = 0xE0048028);\r
375 PROVIDE( C2RDB = 0xE004802C);\r
376 PROVIDE( C2TFI1 = 0xE0048030);\r
377 PROVIDE( C2TID1 = 0xE0048034);\r
378 PROVIDE( C2TDA1 = 0xE0048038);\r
379 PROVIDE( C2TDB1 = 0xE004803C);\r
380 PROVIDE( C2TFI2 = 0xE0048040);\r
381 PROVIDE( C2TID2 = 0xE0048044);\r
382 PROVIDE( C2TDA2 = 0xE0048048);\r
383 PROVIDE( C2TDB2 = 0xE004804C);\r
384 PROVIDE( C2TFI3 = 0xE0048050);\r
385 PROVIDE( C2TID3 = 0xE0048054);\r
386 PROVIDE( C2TDA3 = 0xE0048058);\r
387 PROVIDE( C2TDB3 = 0xE004805C);\r
388 \r
389 /* CAN3 Interface */\r
390 \r
391 PROVIDE( C3MOD = 0xE004C000);\r
392 PROVIDE( C3CMR = 0xE004C004);\r
393 PROVIDE( C3GSR = 0xE004C008);\r
394 PROVIDE( C3ICR = 0xE004C00C);\r
395 PROVIDE( C3IER = 0xE004C010);\r
396 PROVIDE( C3BTR = 0xE004C014);\r
397 PROVIDE( C3EWL = 0xE004C018);\r
398 PROVIDE( C3SR = 0xE004C01C);\r
399 PROVIDE( C3RFS = 0xE004C020);\r
400 PROVIDE( C3RID = 0xE004C024);\r
401 PROVIDE( C3RDA = 0xE004C028);\r
402 PROVIDE( C3RDB = 0xE004C02C);\r
403 PROVIDE( C3TFI1 = 0xE004C030);\r
404 PROVIDE( C3TID1 = 0xE004C034);\r
405 PROVIDE( C3TDA1 = 0xE004C038);\r
406 PROVIDE( C3TDB1 = 0xE004C03C);\r
407 PROVIDE( C3TFI2 = 0xE004C040);\r
408 PROVIDE( C3TID2 = 0xE004C044);\r
409 PROVIDE( C3TDA2 = 0xE004C048);\r
410 PROVIDE( C3TDB2 = 0xE004C04C);\r
411 PROVIDE( C3TFI3 = 0xE004C050);\r
412 PROVIDE( C3TID3 = 0xE004C054);\r
413 PROVIDE( C3TDA3 = 0xE004C058);\r
414 PROVIDE( C3TDB3 = 0xE004C05C);\r
415 \r
416 /* CAN4 Interface */\r
417 \r
418 PROVIDE( C4MOD = 0xE0050000);\r
419 PROVIDE( C4CMR = 0xE0050004);\r
420 PROVIDE( C4GSR = 0xE0050008);\r
421 PROVIDE( C4ICR = 0xE005000C);\r
422 PROVIDE( C4IER = 0xE0050010);\r
423 PROVIDE( C4BTR = 0xE0050014);\r
424 PROVIDE( C4EWL = 0xE0050018);\r
425 PROVIDE( C4SR = 0xE005001C);\r
426 PROVIDE( C4RFS = 0xE0050020);\r
427 PROVIDE( C4RID = 0xE0050024);\r
428 PROVIDE( C4RDA = 0xE0050028);\r
429 PROVIDE( C4RDB = 0xE005002C);\r
430 PROVIDE( C4TFI1 = 0xE0050030);\r
431 PROVIDE( C4TID1 = 0xE0050034);\r
432 PROVIDE( C4TDA1 = 0xE0050038);\r
433 PROVIDE( C4TDB1 = 0xE005003C);\r
434 PROVIDE( C4TFI2 = 0xE0050040);\r
435 PROVIDE( C4TID2 = 0xE0050044);\r
436 PROVIDE( C4TDA2 = 0xE0050048);\r
437 PROVIDE( C4TDB2 = 0xE005004C);\r
438 PROVIDE( C4TFI3 = 0xE0050050);\r
439 PROVIDE( C4TID3 = 0xE0050054);\r
440 PROVIDE( C4TDA3 = 0xE0050058);\r
441 PROVIDE( C4TDB3 = 0xE005005C);\r
442 \r
443 /* SYSTEM CONTROL BLOCK */\r
444 /* MAM */\r
445 \r
446 PROVIDE( MAMCR = 0xE01FC000);\r
447 PROVIDE( MAMTIM = 0xE01FC004);\r
448 \r
449 \r
450 PROVIDE( MEMAP = 0xE01FC040);\r
451 \r
452 /* PLL */\r
453 \r
454 PROVIDE( PLLCON = 0xE01FC080);\r
455 PROVIDE( PLLCFG = 0xE01FC084);\r
456 PROVIDE( PLLSTAT = 0xE01FC088);\r
457 PROVIDE( PLLFEED = 0xE01FC08C);\r
458 \r
459 /* POWER CONTROL */\r
460 \r
461 PROVIDE( PCON = 0xE01FC0C0);\r
462 PROVIDE( PCONP = 0xE01FC0C4);\r
463 \r
464 /* VPB */\r
465 \r
466 PROVIDE( VPBDIV = 0xE01FC100);\r
467 \r
468 /* EXTERNAL INTERUPT/WAKE */\r
469 \r
470 PROVIDE( EXTINT = 0xE01FC140);\r
471 PROVIDE( EXTWAKE = 0xE01FC144);\r
472 PROVIDE( EXTMODE = 0xE01FC148);\r
473 PROVIDE( EXTPOLAR = 0xE01FC14C);\r
474 \r
475 /* External Memory Controller- EMC */\r
476 \r
477 PROVIDE( BCFG0 = 0xFFE00000);\r
478 PROVIDE( BCFG1 = 0xFFE00004);\r
479 PROVIDE( BCFG2 = 0xFFE00008);\r
480 PROVIDE( BCFG3 = 0xFFE0000C);\r
481 \r
482 /* Vector Interrupt Controller (VIC) */\r
483 \r
484 PROVIDE( VICIRQStatus = 0xFFFFF000);\r
485 PROVIDE( VICFIQStatus = 0xFFFFF004);\r
486 PROVIDE( VICRawIntr = 0xFFFFF008);\r
487 PROVIDE( VICIntSelect = 0xFFFFF00C);\r
488 PROVIDE( VICIntEnable = 0xFFFFF010);\r
489 PROVIDE( VICIntEnClr = 0xFFFFF014);\r
490 PROVIDE( VICSoftInt = 0xFFFFF018);\r
491 PROVIDE( VICSoftIntClear = 0xFFFFF01C);\r
492 PROVIDE( VICProtection = 0xFFFFF020);\r
493 PROVIDE( VICVectAddrRead = 0xFFFFF030);\r
494 PROVIDE( VICDefVectAddr = 0xFFFFF034);\r
495 PROVIDE( VICVectAddr = 0xFFFFF100);\r
496 PROVIDE( VICVectCntl = 0xFFFFF200);\r
497 \r