| blob | f6bd40366c101c54de1973a2017bc742c991cb43 |
1 /*
2 * cpu.h --
3 *
4 * All the various CPU defines are placed here to avoid
5 * cluttering marmot.h too much.
6 */
8 #ifndef _CPU_H
9 #define _CPU_H
11 #include <types.h>
13 #define APIC_BASE_MSR 0x1b
16 /*
17 * Note about hypervisor features:
18 *
19 * If cpuid[1].ecx[31] is set, then a hypervisor is present and the
20 * hypervisor functions (0x400000xx) can be queried (which isn't to
21 * say a hypervisor *isn't* present if the bit isn't set).
22 *
23 * VMware defines the following leaves:
24 *
25 * 0x40000000.eax: Max cpuid input value
26 * .ebx: 0x61774d56 (awMV)
27 * .ecx: 0x4d566572 (MVer)
28 * .edx: 0x65726177 (eraw)
29 *
30 * 0x4000000a.eax: Virtual TSC frequency in kHz
31 * .ebx: Virtual bus (local APIC timer) frequency in kHz
32 * .ecx: Reserved
33 * .edx: Reserved
34 *
35 *
36 * Microsoft defines the following leaves:
37 *
38 * 0x40000000.eax: Max cpuid input value
39 * .ebx: 0x7263694d (rciM)
40 * .ecx: 0x666f736f (foso)
41 * .edx: 0x76482074 (vH t)
42 *
43 * 0x40000001.eax: 0x31237648 (1#vH)
44 * .ebx: Reserved
45 * .ecx: Reserved
46 * .edx: Reserved
47 *
48 * 0x40000002.eax: Build number
49 * .ebx: Bits 31-16: Major version
50 * Bits 15-0: Minor version
51 * .ecx: Service pack
52 * .edx: Bits 31-24: Service branch
53 * Bits 23-0: Service number
54 *
55 * 0x40000003.eax: Bit 0: VP runtime (HV_X64_MSR_VP_RUNTIME) is available.
56 * Bit 1: Partition reference counter
57 * (HV_X64_MSR_TIME_REF_COUNT) is available.
58 * Bit 2: Basic SynIC MSRs (HV_X64_MSR_SCONTROL through
59 * HV_X64_MSR_EOM and HV_X64_MSR_SINT0 through
60 * HV_X64_MSR_SINT15) are available.
61 * Bit 3: Synthetic timer MSRs (HV_X64_STIMER0_CONFIG
62 * through HV_X64_STIMER3_COUNT) are available.
63 * Bit 4: APIC access MSRs (HV_X64_MSR_EOI,
64 * HV_X64_MSR_ICR, and HV_X64_MSR_TPR) are
65 * available.
66 * Bit 5: Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and
67 * HV_X64_MSR_HYPERCALL) are available.
68 * Bit 6: Access virtual process index MSR
69 * (HV_X64_MSR_VP_INDEX) is available.
70 * Bit 7: Virtual system reset MSR (HV_X64_MSR_RESET) is
71 * available.
72 * Bits 8-31: Reserved
73 * .ebx: Flags that parent partition specified to create child
74 * partition (HV_PARTITION_PRIVILEGE_MASK):
75 * Bit 0: CreatePartitions
76 * Bit 1: AccessPartitionId
77 * Bit 2: AccessMemoryPool
78 * Bit 3: AdjustMessageBuffers
79 * Bit 4: PostMessages
80 * Bit 5: SignalEvents
81 * Bit 6: CreatePort
82 * Bit 7: ConnectPort
83 * Bit 8: AccessStats
84 * Bit 9: IteratePhysicalHardware
85 * Bit 10: DeprecatedExposeHyperthreads
86 * Bit 11: Debugging
87 * Bit 12: CpuPowerManagement
88 * Bits 13-31: Reserved
89 * .ecx: Power management information:
90 * Bits 0-3: Maximum processor power state:
91 * 0 = C0, 1 = C1, 2 = C2, 3 = C3
92 * Bits 4-31: Reserved
93 * .edx: Miscellaneous features available to partition:
94 * Bit 0: MWAIT is available.
95 * Bit 1: Guest debugging support is available.
96 * Bit 2: Performance monitor support is available.
97 * Bits 3-31: Reserved
98 *
99 * 0x40000004: Hypervisor recommendations to guest.
100 * .eax: Bit 0: Use hypercall for address space switch instead
101 * of mov to %cr3.
102 * Bit 1: Use hypercall for TLB flush instead of invlpg
103 * or mov to %cr3.
104 * Bit 2: User hypercall for remote TLB flush instead of
105 * IPI.
106 * Bit 3: Use MSRs to access APIC registers EOI, ICR, and
107 * TPR instead of memory-mapped APIC registers.
108 * Bit 4: User hypervisor MSR to initiate system RESET.
109 * Bit 5: Use "relaxed timing" in this partition.
110 * Bit 6-31: Reserved
111 * .ebx: Recommended spinlock retries before notifying
112 * hypervisor (0xffffffff indicates never retry).
113 * .ecx: Reserved
114 * .edx: Reserved
115 *
116 * 0x40000005.eax: Maximum number of virtual processors supported.
117 * .ebx: Maximum number of physical processors supported.
118 * .ecx: Reserved
119 * .edx: Reserved
120 *
121 */
124 #define CPUID_FEATURES_STANDARD 0
125 #define CPUID_FEATURES_HYPERVISOR 4
126 #define CPUID_FEATURES_EXTENDED 8
128 #define CPUID_REGISTER_EAX 0
129 #define CPUID_REGISTER_EBX 1
130 #define CPUID_REGISTER_ECX 2
131 #define CPUID_REGISTER_EDX 3
133 /*
134 * The feature mask for each feature looks like:
135 *
136 * 0000 0000 0000 tttt ffff rrll lllh hhhh
137 *
138 * Type is 0, 4, or 8 (standard, hypervisor, or extended).
139 * Function is the function number within the type.
140 * Register is eax, ebx, ecx, or edx.
141 * The feature returned extends from the low bit to the high bit.
142 */
145 #define CPUID_TYPE_SHIFT 16
146 #define CPUID_TYPE_MASK 0x000f0000
147 #define CPUID_FCN_SHIFT 12
148 #define CPUID_FCN_MASK 0x0000f000
149 #define CPUID_REG_SHIFT 10
150 #define CPUID_REG_MASK 0x00000c00
151 #define CPUID_LBIT_SHIFT 5
152 #define CPUID_LBIT_MASK 0x000003e0
153 #define CPUID_HBIT_SHIFT 0
154 #define CPUID_HBIT_MASK 0x0000001f
156 #define CPUID_FEATURE(type,fcn,reg,bl,bh) (((type) << CPUID_TYPE_SHIFT) | \
157 ((fcn) << CPUID_FCN_SHIFT) | \
158 ((reg) << CPUID_REG_SHIFT) | \
159 ((bl) << CPUID_LBIT_SHIFT) | \
160 ((bh) << CPUID_HBIT_SHIFT))
162 #define CPU_HYPERVISOR_PRESENT CPUID_FEATURE(CPUID_FEATURES_STANDARD, \
163 1, \
164 CPUID_REGISTER_ECX, \
165 31, \
166 31)
168 #define CPU_APIC_ENABLED CPUID_FEATURE(CPUID_FEATURES_STANDARD, \
169 1, \
170 CPUID_REGISTER_EDX, \
171 9, \
172 9)
174 #define CPU_VMW_VTSC_KHZ CPUID_FEATURE(CPUID_FEATURES_HYPERVISOR, \
175 0xa, \
176 CPUID_REGISTER_EAX, \
177 0, \
178 31)
180 /*
181 * Check whether the indicated feature bit is set.
182 */
186 #endif