pkgs/by-name/gh/ghdl/simple-tb.vhd

   1 library ieee;
   2 use IEEE.STD_LOGIC_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library STD;
   6 use STD.textio.all;
   7
   8 entity tb is
   9 end tb;
  10
  11 architecture beh of tb is
  12
  13 component simple
  14 port (
  15     CLK, RESET : in std_ulogic;
  16     DATA_OUT : out std_ulogic_vector(7 downto 0);
  17     DONE_OUT : out std_ulogic
  18 );
  19 end component;
  20
  21 signal data : std_ulogic_vector(7 downto 0) := "00100000";
  22 signal clk : std_ulogic;
  23 signal RESET : std_ulogic := '0';
  24 signal done : std_ulogic := '0';
  25 signal cyclecount : integer := 0;
  26
  27 constant cycle_time_c : time := 200 ms;
  28 constant maxcycles : integer := 100;
  29
  30 begin
  31
  32 simple1 : simple
  33 port map (
  34     CLK => clk,
  35     RESET => RESET,
  36     DATA_OUT => data,
  37     DONE_OUT => done
  38 );
  39
  40 clk_process : process
  41 begin
  42     clk <= '0';
  43     wait for cycle_time_c/2;
  44     clk <= '1';
  45     wait for cycle_time_c/2;
  46 end process;
  47
  48 count_process : process(CLK)
  49 begin
  50     if (CLK'event and CLK ='1') then
  51     if (RESET = '1') then
  52         cyclecount <= 0;
  53     else
  54         cyclecount <= cyclecount + 1;
  55     end if;
  56     end if;
  57 end process;
  58
  59 test : process
  60
  61 begin
  62
  63 RESET <= '1';
  64 wait until (clk'event and clk='1');
  65 wait until (clk'event and clk='1');
  66 RESET <= '0';
  67 wait until (clk'event and clk='1');
  68 for cyclecnt in 1 to maxcycles loop
  69     exit when done = '1';
  70     wait until (clk'event and clk='1');
  71     report integer'image(to_integer(unsigned(data)));
  72 end loop;
  73 wait until (clk'event and clk='1');
  74
  75 report "All tests passed." severity NOTE;
  76 wait;
  77 end process;
  78 end beh;