lib/systems/architectures.nix

   1 { lib }:
   2
   3 rec {
   4   # gcc.arch to its features (as in /proc/cpuinfo)
   5   features = {
   6     # x86_64 Generic
   7     # Spec: https://gitlab.com/x86-psABIs/x86-64-ABI/
   8     default        = [ ];
   9     x86-64         = [ ];
  10     x86-64-v2      = [ "sse3" "ssse3" "sse4_1" "sse4_2"                                                  ];
  11     x86-64-v3      = [ "sse3" "ssse3" "sse4_1" "sse4_2"               "avx" "avx2"          "fma"        ];
  12     x86-64-v4      = [ "sse3" "ssse3" "sse4_1" "sse4_2"               "avx" "avx2" "avx512" "fma"        ];
  13     # x86_64 Intel
  14     nehalem        = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes"                                    ];
  15     westmere       = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes"                                    ];
  16     sandybridge    = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx"                              ];
  17     ivybridge      = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx"                              ];
  18     haswell        = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2"          "fma"        ];
  19     broadwell      = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2"          "fma"        ];
  20     skylake        = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2"          "fma"        ];
  21     skylake-avx512 = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  22     cannonlake     = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  23     icelake-client = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  24     icelake-server = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  25     cascadelake    = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  26     cooperlake     = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  27     tigerlake      = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  28     alderlake      = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2"          "fma"        ];
  29     sapphirerapids = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  30     emeraldrapids  = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx" "avx2" "avx512" "fma"        ];
  31     # x86_64 AMD
  32     btver1         = [ "sse3" "ssse3" "sse4_1" "sse4_2"                                                  ];
  33     btver2         = [ "sse3" "ssse3" "sse4_1" "sse4_2"         "aes" "avx"                              ];
  34     bdver1         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx"                 "fma" "fma4" ];
  35     bdver2         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx"                 "fma" "fma4" ];
  36     bdver3         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx"                 "fma" "fma4" ];
  37     bdver4         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2"          "fma" "fma4" ];
  38     znver1         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2"          "fma"        ];
  39     znver2         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2"          "fma"        ];
  40     znver3         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2"          "fma"        ];
  41     znver4         = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "avx512" "fma"        ];
  42     # other
  43     armv5te        = [ ];
  44     armv6          = [ ];
  45     armv7-a        = [ ];
  46     armv8-a        = [ ];
  47     mips32         = [ ];
  48     loongson2f     = [ ];
  49   };
  50
  51   # a superior CPU has all the features of an inferior and is able to build and test code for it
  52   inferiors = {
  53     # x86_64 Generic
  54     default   = [ ];
  55     x86-64    = [ ];
  56     x86-64-v2 = [ "x86-64"    ];
  57     x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
  58     x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
  59
  60     # x86_64 Intel
  61     # https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
  62     nehalem        = [ "x86-64-v2"   ] ++ inferiors.x86-64-v2;
  63     westmere       = [ "nehalem"     ] ++ inferiors.nehalem;
  64     sandybridge    = [ "westmere"    ] ++ inferiors.westmere;
  65     ivybridge      = [ "sandybridge" ] ++ inferiors.sandybridge;
  66
  67     haswell        = lib.unique ([ "ivybridge" "x86-64-v3" ] ++ inferiors.ivybridge ++ inferiors.x86-64-v3);
  68     broadwell      = [ "haswell"   ] ++ inferiors.haswell;
  69     skylake        = [ "broadwell" ] ++ inferiors.broadwell;
  70
  71     skylake-avx512 = lib.unique ([ "skylake" "x86-64-v4" ] ++ inferiors.skylake ++ inferiors.x86-64-v4);
  72     cannonlake     = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
  73     icelake-client = [ "cannonlake"     ] ++ inferiors.cannonlake;
  74     icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
  75     cascadelake    = [ "cannonlake"     ] ++ inferiors.cannonlake;
  76     cooperlake     = [ "cascadelake"    ] ++ inferiors.cascadelake;
  77     tigerlake      = [ "icelake-server" ] ++ inferiors.icelake-server;
  78     sapphirerapids = [ "tigerlake"      ] ++ inferiors.tigerlake;
  79     emeraldrapids  = [ "sapphirerapids" ] ++ inferiors.sapphirerapids;
  80
  81     # CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
  82     alderlake      = [ ];
  83
  84     # x86_64 AMD
  85     # TODO: fill this (need testing)
  86     btver1         = [ ];
  87     btver2         = [ ];
  88     bdver1         = [ ];
  89     bdver2         = [ ];
  90     bdver3         = [ ];
  91     bdver4         = [ ];
  92     # Regarding `skylake` as inferior of `znver1`, there are reports of
  93     # successful usage by Gentoo users and Phoronix benchmarking of different
  94     # `-march` targets.
  95     #
  96     # The GCC documentation on extensions used and wikichip documentation
  97     # regarding supperted extensions on znver1 and skylake was used to create
  98     # this partial order.
  99     #
 100     # Note:
 101     #
 102     # - The successors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512`
 103     #   which no current AMD Zen michroarch support.
 104     # - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no
 105     #   current Intel microarch support.
 106     #
 107     # https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1
 108     # https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
 109     # https://en.wikichip.org/wiki/amd/microarchitectures/zen
 110     # https://en.wikichip.org/wiki/intel/microarchitectures/skylake
 111     znver1         = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
 112     znver2         = [ "znver1"  ] ++ inferiors.znver1;
 113     znver3         = [ "znver2"  ] ++ inferiors.znver2;
 114     znver4         = lib.unique ([ "znver3" "x86-64-v4" ] ++ inferiors.znver3 ++ inferiors.x86-64-v4);
 115
 116     # other
 117     armv5te        = [ ];
 118     armv6          = [ ];
 119     armv7-a        = [ ];
 120     armv8-a        = [ ];
 121     mips32         = [ ];
 122     loongson2f     = [ ];
 123   };
 124
 125   predicates = let
 126     featureSupport = feature: x: builtins.elem feature features.${x} or [];
 127   in {
 128     sse3Support    = featureSupport "sse3";
 129     ssse3Support   = featureSupport "ssse3";
 130     sse4_1Support  = featureSupport "sse4_1";
 131     sse4_2Support  = featureSupport "sse4_2";
 132     sse4_aSupport  = featureSupport "sse4a";
 133     avxSupport     = featureSupport "avx";
 134     avx2Support    = featureSupport "avx2";
 135     avx512Support  = featureSupport "avx512";
 136     aesSupport     = featureSupport "aes";
 137     fmaSupport     = featureSupport "fma";
 138     fma4Support    = featureSupport "fma4";
 139   };
 140 }