src/include/storage/s_lock.h

   1 /*-------------------------------------------------------------------------
   2  *
   3  * s_lock.h
   4  *         Hardware-dependent implementation of spinlocks.
   5  *
   6  *      NOTE: none of the macros in this file are intended to be called directly.
   7  *      Call them through the hardware-independent macros in spin.h.
   8  *
   9  *      The following hardware-dependent macros must be provided for each
  10  *      supported platform:
  11  *
  12  *      void S_INIT_LOCK(slock_t *lock)
  13  *              Initialize a spinlock (to the unlocked state).
  14  *
  15  *      void S_LOCK(slock_t *lock)
  16  *              Acquire a spinlock, waiting if necessary.
  17  *              Time out and abort() if unable to acquire the lock in a
  18  *              "reasonable" amount of time --- typically ~ 1 minute.
  19  *
  20  *      void S_UNLOCK(slock_t *lock)
  21  *              Unlock a previously acquired lock.
  22  *
  23  *      bool S_LOCK_FREE(slock_t *lock)
  24  *              Tests if the lock is free. Returns TRUE if free, FALSE if locked.
  25  *              This does *not* change the state of the lock.
  26  *
  27  *      void SPIN_DELAY(void)
  28  *              Delay operation to occur inside spinlock wait loop.
  29  *
  30  *      Note to implementors: there are default implementations for all these
  31  *      macros at the bottom of the file.  Check if your platform can use
  32  *      these or needs to override them.
  33  *
  34  *  Usually, S_LOCK() is implemented in terms of an even lower-level macro
  35  *      TAS():
  36  *
  37  *      int TAS(slock_t *lock)
  38  *              Atomic test-and-set instruction.  Attempt to acquire the lock,
  39  *              but do *not* wait.      Returns 0 if successful, nonzero if unable
  40  *              to acquire the lock.
  41  *
  42  *      TAS() is NOT part of the API, and should never be called directly.
  43  *
  44  *      CAUTION: on some platforms TAS() may sometimes report failure to acquire
  45  *      a lock even when the lock is not locked.  For example, on Alpha TAS()
  46  *      will "fail" if interrupted.  Therefore TAS() should always be invoked
  47  *      in a retry loop, even if you are certain the lock is free.
  48  *
  49  *      ANOTHER CAUTION: be sure that TAS() and S_UNLOCK() represent sequence
  50  *      points, ie, loads and stores of other values must not be moved across
  51  *      a lock or unlock.  In most cases it suffices to make the operation be
  52  *      done through a "volatile" pointer.
  53  *
  54  *      On most supported platforms, TAS() uses a tas() function written
  55  *      in assembly language to execute a hardware atomic-test-and-set
  56  *      instruction.  Equivalent OS-supplied mutex routines could be used too.
  57  *
  58  *      If no system-specific TAS() is available (ie, HAVE_SPINLOCKS is not
  59  *      defined), then we fall back on an emulation that uses SysV semaphores
  60  *      (see spin.c).  This emulation will be MUCH MUCH slower than a proper TAS()
  61  *      implementation, because of the cost of a kernel call per lock or unlock.
  62  *      An old report is that Postgres spends around 40% of its time in semop(2)
  63  *      when using the SysV semaphore code.
  64  *
  65  *
  66  * Portions Copyright (c) 1996-2008, PostgreSQL Global Development Group
  67  * Portions Copyright (c) 1994, Regents of the University of California
  68  *
  69  *        $PostgreSQL$
  70  *
  71  *-------------------------------------------------------------------------
  72  */
  73 #ifndef S_LOCK_H
  74 #define S_LOCK_H
  75
  76 #include "storage/pg_sema.h"
  77
  78 #ifdef HAVE_SPINLOCKS   /* skip spinlocks if requested */
  79
  80
  81 #if defined(__GNUC__) || defined(__INTEL_COMPILER)
  82 /*************************************************************************
  83  * All the gcc inlines
  84  * Gcc consistently defines the CPU as __cpu__.
  85  * Other compilers use __cpu or __cpu__ so we test for both in those cases.
  86  */
  87
  88 /*----------
  89  * Standard gcc asm format (assuming "volatile slock_t *lock"):
  90
  91         __asm__ __volatile__(
  92                 "       instruction     \n"
  93                 "       instruction     \n"
  94                 "       instruction     \n"
  95 :               "=r"(_res), "+m"(*lock)         // return register, in/out lock value
  96 :               "r"(lock)                                       // lock pointer, in input register
  97 :               "memory", "cc");                        // show clobbered registers here
  98
  99  * The output-operands list (after first colon) should always include
 100  * "+m"(*lock), whether or not the asm code actually refers to this
 101  * operand directly.  This ensures that gcc believes the value in the
 102  * lock variable is used and set by the asm code.  Also, the clobbers
 103  * list (after third colon) should always include "memory"; this prevents
 104  * gcc from thinking it can cache the values of shared-memory fields
 105  * across the asm code.  Add "cc" if your asm code changes the condition
 106  * code register, and also list any temp registers the code uses.
 107  *----------
 108  */
 109
 110
 111 #ifdef __i386__         /* 32-bit i386 */
 112 #define HAS_TEST_AND_SET
 113
 114 typedef unsigned char slock_t;
 115
 116 #define TAS(lock) tas(lock)
 117
 118 static __inline__ int
 119 tas(volatile slock_t *lock)
 120 {
 121         register slock_t _res = 1;
 122
 123         /*
 124          * Use a non-locking test before asserting the bus lock.  Note that the
 125          * extra test appears to be a small loss on some x86 platforms and a small
 126          * win on others; it's by no means clear that we should keep it.
 127          */
 128         __asm__ __volatile__(
 129                 "       cmpb    $0,%1   \n"
 130                 "       jne             1f              \n"
 131                 "       lock                    \n"
 132                 "       xchgb   %0,%1   \n"
 133                 "1: \n"
 134 :               "+q"(_res), "+m"(*lock)
 135 :
 136 :               "memory", "cc");
 137         return (int) _res;
 138 }
 139
 140 #define SPIN_DELAY() spin_delay()
 141
 142 static __inline__ void
 143 spin_delay(void)
 144 {
 145         /*
 146          * This sequence is equivalent to the PAUSE instruction ("rep" is
 147          * ignored by old IA32 processors if the following instruction is
 148          * not a string operation); the IA-32 Architecture Software
 149          * Developer's Manual, Vol. 3, Section 7.7.2 describes why using
 150          * PAUSE in the inner loop of a spin lock is necessary for good
 151          * performance:
 152          *
 153          *     The PAUSE instruction improves the performance of IA-32
 154          *     processors supporting Hyper-Threading Technology when
 155          *     executing spin-wait loops and other routines where one
 156          *     thread is accessing a shared lock or semaphore in a tight
 157          *     polling loop. When executing a spin-wait loop, the
 158          *     processor can suffer a severe performance penalty when
 159          *     exiting the loop because it detects a possible memory order
 160          *     violation and flushes the core processor's pipeline. The
 161          *     PAUSE instruction provides a hint to the processor that the
 162          *     code sequence is a spin-wait loop. The processor uses this
 163          *     hint to avoid the memory order violation and prevent the
 164          *     pipeline flush. In addition, the PAUSE instruction
 165          *     de-pipelines the spin-wait loop to prevent it from
 166          *     consuming execution resources excessively.
 167          */
 168         __asm__ __volatile__(
 169                 " rep; nop                      \n");
 170 }
 171
 172 #endif   /* __i386__ */
 173
 174
 175 #ifdef __x86_64__               /* AMD Opteron, Intel EM64T */
 176 #define HAS_TEST_AND_SET
 177
 178 typedef unsigned char slock_t;
 179
 180 #define TAS(lock) tas(lock)
 181
 182 static __inline__ int
 183 tas(volatile slock_t *lock)
 184 {
 185         register slock_t _res = 1;
 186
 187         /*
 188          * On Opteron, using a non-locking test before the locking instruction
 189          * is a huge loss.  On EM64T, it appears to be a wash or small loss,
 190          * so we needn't bother to try to distinguish the sub-architectures.
 191          */
 192         __asm__ __volatile__(
 193                 "       lock                    \n"
 194                 "       xchgb   %0,%1   \n"
 195 :               "+q"(_res), "+m"(*lock)
 196 :
 197 :               "memory", "cc");
 198         return (int) _res;
 199 }
 200
 201 #define SPIN_DELAY() spin_delay()
 202
 203 static __inline__ void
 204 spin_delay(void)
 205 {
 206         /*
 207          * Adding a PAUSE in the spin delay loop is demonstrably a no-op on
 208          * Opteron, but it may be of some use on EM64T, so we keep it.
 209          */
 210         __asm__ __volatile__(
 211                 " rep; nop                      \n");
 212 }
 213
 214 #endif   /* __x86_64__ */
 215
 216
 217 #if defined(__ia64__) || defined(__ia64)        /* Intel Itanium */
 218 #define HAS_TEST_AND_SET
 219
 220 typedef unsigned int slock_t;
 221
 222 #define TAS(lock) tas(lock)
 223
 224 #ifndef __INTEL_COMPILER
 225
 226 static __inline__ int
 227 tas(volatile slock_t *lock)
 228 {
 229         long int        ret;
 230
 231         __asm__ __volatile__(
 232                 "       xchg4   %0=%1,%2        \n"
 233 :               "=r"(ret), "+m"(*lock)
 234 :               "r"(1)
 235 :               "memory");
 236         return (int) ret;
 237 }
 238
 239 #else /* __INTEL_COMPILER */
 240
 241 static __inline__ int
 242 tas(volatile slock_t *lock)
 243 {
 244         int             ret;
 245
 246         ret = _InterlockedExchange(lock,1);     /* this is a xchg asm macro */
 247
 248         return ret;
 249 }
 250
 251 #endif /* __INTEL_COMPILER */
 252 #endif   /* __ia64__ || __ia64 */
 253
 254
 255 #if defined(__arm__) || defined(__arm)
 256 #define HAS_TEST_AND_SET
 257
 258 typedef unsigned char slock_t;
 259
 260 #define TAS(lock) tas(lock)
 261
 262 static __inline__ int
 263 tas(volatile slock_t *lock)
 264 {
 265         register slock_t _res = 1;
 266
 267         __asm__ __volatile__(
 268                 "       swpb    %0, %0, [%2]    \n"
 269 :               "+r"(_res), "+m"(*lock)
 270 :               "r"(lock)
 271 :               "memory");
 272         return (int) _res;
 273 }
 274
 275 #endif   /* __arm__ */
 276
 277
 278 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
 279 #if defined(__s390__) || defined(__s390x__)
 280 #define HAS_TEST_AND_SET
 281
 282 typedef unsigned int slock_t;
 283
 284 #define TAS(lock)          tas(lock)
 285
 286 static __inline__ int
 287 tas(volatile slock_t *lock)
 288 {
 289         int                     _res = 0;
 290
 291         __asm__ __volatile__(
 292                 "       cs      %0,%3,0(%2)             \n"
 293 :               "+d"(_res), "+m"(*lock)
 294 :               "a"(lock), "d"(1)
 295 :               "memory", "cc");
 296         return _res;
 297 }
 298
 299 #endif   /* __s390__ || __s390x__ */
 300
 301
 302 #if defined(__sparc__)          /* Sparc */
 303 #define HAS_TEST_AND_SET
 304
 305 typedef unsigned char slock_t;
 306
 307 #define TAS(lock) tas(lock)
 308
 309 static __inline__ int
 310 tas(volatile slock_t *lock)
 311 {
 312         register slock_t _res;
 313
 314         /*
 315          *      See comment in /pg/backend/port/tas/solaris_sparc.s for why this
 316          *      uses "ldstub", and that file uses "cas".  gcc currently generates
 317          *      sparcv7-targeted binaries, so "cas" use isn't possible.
 318          */
 319         __asm__ __volatile__(
 320                 "       ldstub  [%2], %0        \n"
 321 :               "=r"(_res), "+m"(*lock)
 322 :               "r"(lock)
 323 :               "memory");
 324         return (int) _res;
 325 }
 326
 327 #endif   /* __sparc__ */
 328
 329
 330 /* PowerPC */
 331 #if defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
 332 #define HAS_TEST_AND_SET
 333
 334 #if defined(__ppc64__) || defined(__powerpc64__)
 335 typedef unsigned long slock_t;
 336 #else
 337 typedef unsigned int slock_t;
 338 #endif
 339
 340 #define TAS(lock) tas(lock)
 341 /*
 342  * NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
 343  * an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
 344  */
 345 static __inline__ int
 346 tas(volatile slock_t *lock)
 347 {
 348         slock_t _t;
 349         int _res;
 350
 351         __asm__ __volatile__(
 352 "       lwarx   %0,0,%3         \n"
 353 "       cmpwi   %0,0            \n"
 354 "       bne     1f                      \n"
 355 "       addi    %0,%0,1         \n"
 356 "       stwcx.  %0,0,%3         \n"
 357 "       beq     2f              \n"
 358 "1:     li      %1,1            \n"
 359 "       b               3f                      \n"
 360 "2:                                             \n"
 361 "       isync                           \n"
 362 "       li      %1,0            \n"
 363 "3:                                             \n"
 364
 365 :       "=&r"(_t), "=r"(_res), "+m"(*lock)
 366 :       "r"(lock)
 367 :       "memory", "cc");
 368         return _res;
 369 }
 370
 371 /* PowerPC S_UNLOCK is almost standard but requires a "sync" instruction */
 372 #define S_UNLOCK(lock)  \
 373 do \
 374 { \
 375         __asm__ __volatile__ (" sync \n"); \
 376         *((volatile slock_t *) (lock)) = 0; \
 377 } while (0)
 378
 379 #endif /* powerpc */
 380
 381
 382 /* Linux Motorola 68k */
 383 #if (defined(__mc68000__) || defined(__m68k__)) && defined(__linux__)
 384 #define HAS_TEST_AND_SET
 385
 386 typedef unsigned char slock_t;
 387
 388 #define TAS(lock) tas(lock)
 389
 390 static __inline__ int
 391 tas(volatile slock_t *lock)
 392 {
 393         register int rv;
 394
 395         __asm__ __volatile__(
 396                 "       clrl    %0              \n"
 397                 "       tas             %1              \n"
 398                 "       sne             %0              \n"
 399 :               "=d"(rv), "+m"(*lock)
 400 :
 401 :               "memory", "cc");
 402         return rv;
 403 }
 404
 405 #endif   /* (__mc68000__ || __m68k__) && __linux__ */
 406
 407
 408 /*
 409  * VAXen -- even multiprocessor ones
 410  * (thanks to Tom Ivar Helbekkmo)
 411  */
 412 #if defined(__vax__)
 413 #define HAS_TEST_AND_SET
 414
 415 typedef unsigned char slock_t;
 416
 417 #define TAS(lock) tas(lock)
 418
 419 static __inline__ int
 420 tas(volatile slock_t *lock)
 421 {
 422         register int    _res;
 423
 424         __asm__ __volatile__(
 425                 "       movl    $1, %0                  \n"
 426                 "       bbssi   $0, (%2), 1f    \n"
 427                 "       clrl    %0                              \n"
 428                 "1: \n"
 429 :               "=&r"(_res), "+m"(*lock)
 430 :               "r"(lock)
 431 :               "memory");
 432         return _res;
 433 }
 434
 435 #endif   /* __vax__ */
 436
 437
 438 #if defined(__ns32k__)          /* National Semiconductor 32K */
 439 #define HAS_TEST_AND_SET
 440
 441 typedef unsigned char slock_t;
 442
 443 #define TAS(lock) tas(lock)
 444
 445 static __inline__ int
 446 tas(volatile slock_t *lock)
 447 {
 448         register int    _res;
 449
 450         __asm__ __volatile__(
 451                 "       sbitb   0, %1   \n"
 452                 "       sfsd    %0              \n"
 453 :               "=r"(_res), "+m"(*lock)
 454 :
 455 :               "memory");
 456         return _res;
 457 }
 458
 459 #endif   /* __ns32k__ */
 460
 461
 462 #if defined(__alpha) || defined(__alpha__)      /* Alpha */
 463 /*
 464  * Correct multi-processor locking methods are explained in section 5.5.3
 465  * of the Alpha AXP Architecture Handbook, which at this writing can be
 466  * found at ftp://ftp.netbsd.org/pub/NetBSD/misc/dec-docs/index.html.
 467  * For gcc we implement the handbook's code directly with inline assembler.
 468  */
 469 #define HAS_TEST_AND_SET
 470
 471 typedef unsigned long slock_t;
 472
 473 #define TAS(lock)  tas(lock)
 474
 475 static __inline__ int
 476 tas(volatile slock_t *lock)
 477 {
 478         register slock_t _res;
 479
 480         __asm__ __volatile__(
 481                 "       ldq             $0, %1  \n"
 482                 "       bne             $0, 2f  \n"
 483                 "       ldq_l   %0, %1  \n"
 484                 "       bne             %0, 2f  \n"
 485                 "       mov             1,  $0  \n"
 486                 "       stq_c   $0, %1  \n"
 487                 "       beq             $0, 2f  \n"
 488                 "       mb                              \n"
 489                 "       br              3f              \n"
 490                 "2:     mov             1, %0   \n"
 491                 "3:                                     \n"
 492 :               "=&r"(_res), "+m"(*lock)
 493 :
 494 :               "memory", "0");
 495         return (int) _res;
 496 }
 497
 498 #define S_UNLOCK(lock)  \
 499 do \
 500 {\
 501         __asm__ __volatile__ (" mb \n"); \
 502         *((volatile slock_t *) (lock)) = 0; \
 503 } while (0)
 504
 505 #endif /* __alpha || __alpha__ */
 506
 507
 508 #if defined(__mips__) && !defined(__sgi)        /* non-SGI MIPS */
 509 /* Note: on SGI we use the OS' mutex ABI, see below */
 510 /* Note: R10000 processors require a separate SYNC */
 511 #define HAS_TEST_AND_SET
 512
 513 typedef unsigned int slock_t;
 514
 515 #define TAS(lock) tas(lock)
 516
 517 static __inline__ int
 518 tas(volatile slock_t *lock)
 519 {
 520         register volatile slock_t *_l = lock;
 521         register int _res;
 522         register int _tmp;
 523
 524         __asm__ __volatile__(
 525                 "       .set push           \n"
 526                 "       .set mips2          \n"
 527                 "       .set noreorder      \n"
 528                 "       .set nomacro        \n"
 529                 "       ll      %0, %2      \n"
 530                 "       or      %1, %0, 1   \n"
 531                 "       sc      %1, %2      \n"
 532                 "       xori    %1, 1       \n"
 533                 "       or      %0, %0, %1  \n"
 534                 "       sync                \n"
 535                 "       .set pop              "
 536 :               "=&r" (_res), "=&r" (_tmp), "+R" (*_l)
 537 :
 538 :               "memory");
 539         return _res;
 540 }
 541
 542 /* MIPS S_UNLOCK is almost standard but requires a "sync" instruction */
 543 #define S_UNLOCK(lock)  \
 544 do \
 545 { \
 546         __asm__ __volatile__( \
 547                 "       .set push           \n" \
 548                 "       .set mips2          \n" \
 549                 "       .set noreorder      \n" \
 550                 "       .set nomacro        \n" \
 551                 "       sync                \n" \
 552                 "       .set pop              "); \
 553         *((volatile slock_t *) (lock)) = 0; \
 554 } while (0)
 555
 556 #endif /* __mips__ && !__sgi */
 557
 558
 559 #if defined(__m32r__) && defined(HAVE_SYS_TAS_H)        /* Renesas' M32R */
 560 #define HAS_TEST_AND_SET
 561
 562 #include <sys/tas.h>
 563
 564 typedef int slock_t;
 565
 566 #define TAS(lock) tas(lock)
 567
 568 #endif /* __m32r__ */
 569
 570
 571 /* These live in s_lock.c, but only for gcc */
 572
 573
 574 #if defined(__m68k__) && !defined(__linux__)    /* non-Linux Motorola 68k */
 575 #define HAS_TEST_AND_SET
 576
 577 typedef unsigned char slock_t;
 578 #endif
 579
 580
 581 #endif  /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
 582
 583
 584
 585 /*
 586  * ---------------------------------------------------------------------
 587  * Platforms that use non-gcc inline assembly:
 588  * ---------------------------------------------------------------------
 589  */
 590
 591 #if !defined(HAS_TEST_AND_SET)  /* We didn't trigger above, let's try here */
 592
 593
 594 #if defined(USE_UNIVEL_CC)              /* Unixware compiler */
 595 #define HAS_TEST_AND_SET
 596
 597 typedef unsigned char slock_t;
 598
 599 #define TAS(lock)       tas(lock)
 600
 601 asm int
 602 tas(volatile slock_t *s_lock)
 603 {
 604 /* UNIVEL wants %mem in column 1, so we don't pg_indent this file */
 605 %mem s_lock
 606         pushl %ebx
 607         movl s_lock, %ebx
 608         movl $255, %eax
 609         lock
 610         xchgb %al, (%ebx)
 611         popl %ebx
 612 }
 613
 614 #endif   /* defined(USE_UNIVEL_CC) */
 615
 616
 617 #if defined(__alpha) || defined(__alpha__)      /* Tru64 Unix Alpha compiler */
 618 /*
 619  * The Tru64 compiler doesn't support gcc-style inline asm, but it does
 620  * have some builtin functions that accomplish much the same results.
 621  * For simplicity, slock_t is defined as long (ie, quadword) on Alpha
 622  * regardless of the compiler in use.  LOCK_LONG and UNLOCK_LONG only
 623  * operate on an int (ie, longword), but that's OK as long as we define
 624  * S_INIT_LOCK to zero out the whole quadword.
 625  */
 626 #define HAS_TEST_AND_SET
 627
 628 typedef unsigned long slock_t;
 629
 630 #include <alpha/builtins.h>
 631 #define S_INIT_LOCK(lock)  (*(lock) = 0)
 632 #define TAS(lock)                  (__LOCK_LONG_RETRY((lock), 1) == 0)
 633 #define S_UNLOCK(lock)     __UNLOCK_LONG(lock)
 634
 635 #endif   /* __alpha || __alpha__ */
 636
 637
 638 #if defined(__hppa) || defined(__hppa__)        /* HP PA-RISC, GCC and HP compilers */
 639 /*
 640  * HP's PA-RISC
 641  *
 642  * See src/backend/port/hpux/tas.c.template for details about LDCWX.  Because
 643  * LDCWX requires a 16-byte-aligned address, we declare slock_t as a 16-byte
 644  * struct.  The active word in the struct is whichever has the aligned address;
 645  * the other three words just sit at -1.
 646  *
 647  * When using gcc, we can inline the required assembly code.
 648  */
 649 #define HAS_TEST_AND_SET
 650
 651 typedef struct
 652 {
 653         int                     sema[4];
 654 } slock_t;
 655
 656 #define TAS_ACTIVE_WORD(lock)   ((volatile int *) (((long) (lock) + 15) & ~15))
 657
 658 #if defined(__GNUC__)
 659
 660 static __inline__ int
 661 tas(volatile slock_t *lock)
 662 {
 663         volatile int *lockword = TAS_ACTIVE_WORD(lock);
 664         register int lockval;
 665
 666         __asm__ __volatile__(
 667                 "       ldcwx   0(0,%2),%0      \n"
 668 :               "=r"(lockval), "+m"(*lockword)
 669 :               "r"(lockword)
 670 :               "memory");
 671         return (lockval == 0);
 672 }
 673
 674 #endif /* __GNUC__ */
 675
 676 #define S_UNLOCK(lock)  (*TAS_ACTIVE_WORD(lock) = -1)
 677
 678 #define S_INIT_LOCK(lock) \
 679         do { \
 680                 volatile slock_t *lock_ = (lock); \
 681                 lock_->sema[0] = -1; \
 682                 lock_->sema[1] = -1; \
 683                 lock_->sema[2] = -1; \
 684                 lock_->sema[3] = -1; \
 685         } while (0)
 686
 687 #define S_LOCK_FREE(lock)       (*TAS_ACTIVE_WORD(lock) != 0)
 688
 689 #endif   /* __hppa || __hppa__ */
 690
 691
 692 #if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
 693
 694 #define HAS_TEST_AND_SET
 695
 696 typedef unsigned int slock_t;
 697
 698 #include <ia64/sys/inline.h>
 699 #define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE)
 700
 701 #endif  /* HPUX on IA64, non gcc */
 702
 703
 704 #if defined(__sgi)      /* SGI compiler */
 705 /*
 706  * SGI IRIX 5
 707  * slock_t is defined as a unsigned long. We use the standard SGI
 708  * mutex API.
 709  *
 710  * The following comment is left for historical reasons, but is probably
 711  * not a good idea since the mutex ABI is supported.
 712  *
 713  * This stuff may be supplemented in the future with Masato Kataoka's MIPS-II
 714  * assembly from his NECEWS SVR4 port, but we probably ought to retain this
 715  * for the R3000 chips out there.
 716  */
 717 #define HAS_TEST_AND_SET
 718
 719 typedef unsigned long slock_t;
 720
 721 #include "mutex.h"
 722 #define TAS(lock)       (test_and_set(lock,1))
 723 #define S_UNLOCK(lock)  (test_then_and(lock,0))
 724 #define S_INIT_LOCK(lock)       (test_then_and(lock,0))
 725 #define S_LOCK_FREE(lock)       (test_then_add(lock,0) == 0)
 726 #endif   /* __sgi */
 727
 728
 729 #if defined(sinix)              /* Sinix */
 730 /*
 731  * SINIX / Reliant UNIX
 732  * slock_t is defined as a struct abilock_t, which has a single unsigned long
 733  * member. (Basically same as SGI)
 734  */
 735 #define HAS_TEST_AND_SET
 736
 737 #include "abi_mutex.h"
 738 typedef abilock_t slock_t;
 739
 740 #define TAS(lock)       (!acquire_lock(lock))
 741 #define S_UNLOCK(lock)  release_lock(lock)
 742 #define S_INIT_LOCK(lock)       init_lock(lock)
 743 #define S_LOCK_FREE(lock)       (stat_lock(lock) == UNLOCKED)
 744 #endif   /* sinix */
 745
 746
 747 #if defined(_AIX)       /* AIX */
 748 /*
 749  * AIX (POWER)
 750  */
 751 #define HAS_TEST_AND_SET
 752
 753 #include <sys/atomic_op.h>
 754
 755 typedef int slock_t;
 756
 757 #define TAS(lock)                       _check_lock((slock_t *) (lock), 0, 1)
 758 #define S_UNLOCK(lock)          _clear_lock((slock_t *) (lock), 0)
 759 #endif   /* _AIX */
 760
 761
 762 #if defined (nextstep)          /* Nextstep */
 763 #define HAS_TEST_AND_SET
 764
 765 typedef struct mutex slock_t;
 766
 767 #define S_LOCK(lock)    mutex_lock(lock)
 768 #define S_UNLOCK(lock)  mutex_unlock(lock)
 769 #define S_INIT_LOCK(lock)       mutex_init(lock)
 770 /* For Mach, we have to delve inside the entrails of `struct mutex'.  Ick! */
 771 #define S_LOCK_FREE(alock)      ((alock)->lock == 0)
 772 #endif   /* nextstep */
 773
 774
 775 /* These are in s_lock.c */
 776
 777
 778 #if defined(sun3)               /* Sun3 */
 779 #define HAS_TEST_AND_SET
 780
 781 typedef unsigned char slock_t;
 782 #endif
 783
 784
 785 #if defined(__SUNPRO_C) && (defined(__i386) || defined(__x86_64__) || defined(__sparc__) || defined(__sparc))
 786 #define HAS_TEST_AND_SET
 787
 788 #if defined(__i386) || defined(__x86_64__) || defined(__sparcv9) || defined(__sparcv8plus)
 789 typedef unsigned int slock_t;
 790 #else
 791 typedef unsigned char slock_t;
 792 #endif
 793
 794 extern slock_t pg_atomic_cas(volatile slock_t *lock, slock_t with,
 795                                                                           slock_t cmp);
 796
 797 #define TAS(a) (pg_atomic_cas((a), 1, 0) != 0)
 798 #endif
 799
 800
 801 #ifdef WIN32_ONLY_COMPILER
 802 typedef LONG slock_t;
 803
 804 #define HAS_TEST_AND_SET
 805 #define TAS(lock) (InterlockedCompareExchange(lock, 1, 0))
 806
 807 #define SPIN_DELAY() spin_delay()
 808
 809 static __forceinline void
 810 spin_delay(void)
 811 {
 812         /* See comment for gcc code. Same code, MASM syntax */
 813         __asm rep nop;
 814 }
 815
 816 #endif
 817
 818
 819 #endif  /* !defined(HAS_TEST_AND_SET) */
 820
 821
 822 /* Blow up if we didn't have any way to do spinlocks */
 823 #ifndef HAS_TEST_AND_SET
 824 #error PostgreSQL does not have native spinlock support on this platform.  To continue the compilation, rerun configure using --disable-spinlocks.  However, performance will be poor.  Please report this to pgsql-bugs@postgresql.org.
 825 #endif
 826
 827
 828 #else   /* !HAVE_SPINLOCKS */
 829
 830
 831 /*
 832  * Fake spinlock implementation using semaphores --- slow and prone
 833  * to fall foul of kernel limits on number of semaphores, so don't use this
 834  * unless you must!  The subroutines appear in spin.c.
 835  */
 836 typedef PGSemaphoreData slock_t;
 837
 838 extern bool s_lock_free_sema(volatile slock_t *lock);
 839 extern void s_unlock_sema(volatile slock_t *lock);
 840 extern void s_init_lock_sema(volatile slock_t *lock);
 841 extern int      tas_sema(volatile slock_t *lock);
 842
 843 #define S_LOCK_FREE(lock)       s_lock_free_sema(lock)
 844 #define S_UNLOCK(lock)   s_unlock_sema(lock)
 845 #define S_INIT_LOCK(lock)       s_init_lock_sema(lock)
 846 #define TAS(lock)       tas_sema(lock)
 847
 848
 849 #endif  /* HAVE_SPINLOCKS */
 850
 851
 852 /*
 853  * Default Definitions - override these above as needed.
 854  */
 855
 856 #if !defined(S_LOCK)
 857 #define S_LOCK(lock) \
 858         do { \
 859                 if (TAS(lock)) \
 860                         s_lock((lock), __FILE__, __LINE__); \
 861         } while (0)
 862 #endif   /* S_LOCK */
 863
 864 #if !defined(S_LOCK_FREE)
 865 #define S_LOCK_FREE(lock)       (*(lock) == 0)
 866 #endif   /* S_LOCK_FREE */
 867
 868 #if !defined(S_UNLOCK)
 869 #define S_UNLOCK(lock)          (*((volatile slock_t *) (lock)) = 0)
 870 #endif   /* S_UNLOCK */
 871
 872 #if !defined(S_INIT_LOCK)
 873 #define S_INIT_LOCK(lock)       S_UNLOCK(lock)
 874 #endif   /* S_INIT_LOCK */
 875
 876 #if !defined(SPIN_DELAY)
 877 #define SPIN_DELAY()    ((void) 0)
 878 #endif   /* SPIN_DELAY */
 879
 880 #if !defined(TAS)
 881 extern int      tas(volatile slock_t *lock);            /* in port/.../tas.s, or
 882                                                                                                  * s_lock.c */
 883
 884 #define TAS(lock)               tas(lock)
 885 #endif   /* TAS */
 886
 887
 888 /*
 889  * Platform-independent out-of-line support routines
 890  */
 891 extern void s_lock(volatile slock_t *lock, const char *file, int line);
 892
 893 /* Support for dynamic adjustment of spins_per_delay */
 894 #define DEFAULT_SPINS_PER_DELAY  100
 895
 896 extern void set_spins_per_delay(int shared_spins_per_delay);
 897 extern int      update_spins_per_delay(int shared_spins_per_delay);
 898
 899 #endif   /* S_LOCK_H */