fpga/fpga_icopyx_top.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
  18 // and the ARM. In the low-frequency modes it passes the data straight
  19 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
  20 // frequency modes, the FPGA might perform some demodulation first, to
  21 // reduce the amount of data that we must send to the ARM.
  22 //-----------------------------------------------------------------------------
  23
  24 module fpga_top(
  25     input spck,
  26     output miso,
  27     input mosi,
  28     input ncs,
  29     input pck0,
  30     input ck_1356meg,
  31     input ck_1356megb,
  32     output pwr_lo,
  33     output pwr_hi,
  34     output pwr_oe1,
  35     output pwr_oe2,
  36     output pwr_oe3,
  37     output pwr_oe4,
  38     input [7:0] adc_d,
  39     output adc_clk,
  40     output adc_noe,
  41     output ssp_frame,
  42     output ssp_din,
  43     input ssp_dout,
  44     output ssp_clk,
  45     input cross_hi,
  46     input cross_lo,
  47     output dbg,
  48     output PWR_LO_EN,
  49     input FPGA_SWITCH
  50     );
  51
  52
  53 fpga_hf hfmod(
  54     hfspck, hfmiso, hfmosi, hfncs,
  55     hfpck0, hfck_1356meg, hfck_1356megb,
  56     hfpwr_lo, hfpwr_hi,
  57     hfpwr_oe1, hfpwr_oe2, hfpwr_oe3, hfpwr_oe4,
  58     adc_d, hfadc_clk, hfadc_noe,
  59     hfssp_frame, hfssp_din, hfssp_dout, hfssp_clk,
  60     hfcross_hi, hfcross_lo,
  61     hfdebug
  62 );
  63
  64 fpga_lf lfmod(
  65     lfspck, lfmiso, lfmosi, lfncs,
  66     lfpck0, lfck_1356meg, lfck_1356megb,
  67     lfpwr_lo, lfpwr_hi,
  68     lfpwr_oe1, lfpwr_oe2, lfpwr_oe3, lfpwr_oe4,
  69     adc_d, lfadc_clk, lfadc_noe,
  70     lfssp_frame, lfssp_din, lfssp_dout, lfssp_clk,
  71     lfcross_hi, lfcross_lo,
  72     lfdebug,
  73     lfPWR_LO_EN
  74 );
  75
  76 mux2_oneout         mux_spck_all                (FPGA_SWITCH, spck,         hfspck,         lfspck);
  77 mux2_one            mux_miso_all                (FPGA_SWITCH, miso,         hfmiso,         lfmiso);
  78 mux2_oneout         mux_mosi_all                (FPGA_SWITCH, mosi,         hfmosi,         lfmosi);
  79 mux2_oneout         mux_ncs_all                 (FPGA_SWITCH, ncs,          hfncs,          lfncs);
  80 mux2_oneout         mux_pck0_all                (FPGA_SWITCH, pck0,         hfpck0,         lfpck0);
  81 mux2_oneout         mux_ck_1356meg_all          (FPGA_SWITCH, ck_1356meg,   hfck_1356meg,   lfck_1356meg);
  82 mux2_oneout         mux_ck_1356megb_all         (FPGA_SWITCH, ck_1356megb,  hfck_1356megb,  lfck_1356megb);
  83 mux2_one            mux_pwr_lo_all              (FPGA_SWITCH, pwr_lo,       hfpwr_lo,       lfpwr_lo);
  84 mux2_one            mux_pwr_hi_all              (FPGA_SWITCH, pwr_hi,       hfpwr_hi,       lfpwr_hi);
  85 mux2_one            mux_pwr_oe1_all             (FPGA_SWITCH, pwr_oe1,      hfpwr_oe1,      lfpwr_oe1);
  86 mux2_one            mux_pwr_oe2_all             (FPGA_SWITCH, pwr_oe2,      hfpwr_oe2,      lfpwr_oe2);
  87 mux2_one            mux_pwr_oe3_all             (FPGA_SWITCH, pwr_oe3,      hfpwr_oe3,      lfpwr_oe3);
  88 mux2_one            mux_pwr_oe4_all             (FPGA_SWITCH, pwr_oe4,      hfpwr_oe4,      lfpwr_oe4);
  89 mux2_one            mux_adc_clk_all             (FPGA_SWITCH, adc_clk,      hfadc_clk,      lfadc_clk);
  90 mux2_one            mux_adc_noe_all             (FPGA_SWITCH, adc_noe,      adc_noe,        lfadc_noe);
  91 mux2_one            mux_ssp_frame_all           (FPGA_SWITCH, ssp_frame,    hfssp_frame,    lfssp_frame);
  92 mux2_one            mux_ssp_din_all             (FPGA_SWITCH, ssp_din,      hfssp_din,      lfssp_din);
  93 mux2_oneout         mux_ssp_dout_all            (FPGA_SWITCH, ssp_dout,     hfssp_dout,     lfssp_dout);
  94 mux2_one            mux_ssp_clk_all             (FPGA_SWITCH, ssp_clk,      hfssp_clk,      lfssp_clk);
  95 mux2_oneout         mux_cross_hi_all            (FPGA_SWITCH, cross_hi,     hfcross_hi,     lfcross_hi);
  96 mux2_oneout         mux_cross_lo_all            (FPGA_SWITCH, cross_lo,     hfcross_lo,     lfcross_lo);
  97 mux2_one            mux_dbg_all                 (FPGA_SWITCH, dbg,          hfdebug,        lfdebug);
  98 mux2_one            mux_PWR_LO_EN_all           (FPGA_SWITCH, PWR_LO_EN,    1'b0,           lfPWR_LO_EN);
  99
 100 endmodule