fpga/lo_read.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The way that we connect things in low-frequency read mode. In this case
  18 // we are generating the unmodulated low frequency carrier.
  19 // The A/D samples at that same rate and the result is serialized.
  20 //
  21 // Jonathan Westhues, April 2006
  22 //-----------------------------------------------------------------------------
  23
  24 module lo_read(
  25     input pck0,
  26     input pck_divclk,
  27     input [7:0] pck_cnt,
  28     input [7:0] adc_d,
  29     input lf_field,
  30
  31     output ssp_din,
  32     output ssp_frame,
  33     output ssp_clk,
  34     output adc_clk,
  35     output pwr_lo,
  36     output pwr_hi,
  37     output pwr_oe1,
  38     output pwr_oe2,
  39     output pwr_oe3,
  40     output pwr_oe4,
  41     output debug
  42 );
  43
  44 reg [7:0] to_arm_shiftreg;
  45
  46 // this task also runs at pck0 frequency (24MHz) and is used to serialize
  47 // the ADC output which is then clocked into the ARM SSP.
  48
  49 // because pck_divclk always transitions when pck_cnt = 0 we use the
  50 // pck_div counter to sync our other signals off it
  51 // we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
  52 always @(posedge pck0)
  53 begin
  54     if ((pck_cnt == 8'd7) && !pck_divclk)
  55         to_arm_shiftreg <= adc_d;
  56     else
  57         to_arm_shiftreg <= {to_arm_shiftreg[6:0], 1'b0};
  58 end
  59
  60 // ADC samples on falling edge of adc_clk, data available on the rising edge
  61
  62 // example of ssp transfer of binary value 1100101
  63 // start of transfer is indicated by the rise of the ssp_frame signal
  64 // ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
  65 // the ARM by the falling edge of ssp_clk
  66 //             _______________________________
  67 // ssp_frame__|                               |__
  68 //             _______         ___     ___
  69 // ssp_din  __|       |_______|   |___|   |______
  70 //         _   _   _   _   _   _   _   _   _   _
  71 // ssp_clk  |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
  72
  73 // serialized SSP data is gated by pck_divclk to suppress unwanted signal
  74 assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
  75 // SSP clock always runs at 24MHz
  76 assign ssp_clk = pck0;
  77 // SSP frame is gated by pck_divclk and goes high when pck_cnt=8..15
  78 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
  79 // unused signals tied low
  80 assign pwr_hi  = 1'b0;
  81 // always on outputs, unused
  82 assign pwr_oe1 = 1'b0;
  83 assign pwr_oe2 = 1'b0;
  84 assign pwr_oe3 = 1'b0;
  85 assign pwr_oe4 = 1'b0;
  86 // this is the antenna driver signal
  87 assign pwr_lo = lf_field & pck_divclk;
  88 // ADC clock out of phase with antenna driver
  89 assign adc_clk = ~pck_divclk;
  90 // ADC clock also routed to debug pin
  91 assign debug = adc_clk;
  92 endmodule