fpga/lo_adc.v

   1 //-----------------------------------------------------------------------------
   2 // The way that we connect things in low-frequency simulation mode. In this
   3 // case just pass everything through to the ARM, which can bit-bang this
   4 // (because it is so slow).
   5 //
   6 // Jonathan Westhues, April 2006
   7 //-----------------------------------------------------------------------------
   8
   9 module lo_adc(
  10     pck0,
  11     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
  12     adc_d, adc_clk,
  13     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  14     dbg, divisor,
  15     lf_field
  16 );
  17     input pck0;
  18     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  19     input [7:0] adc_d;
  20     output adc_clk;
  21     input ssp_dout;
  22     output ssp_frame, ssp_din, ssp_clk;
  23     output dbg;
  24     input [7:0] divisor;
  25     input lf_field;
  26
  27 reg [7:0] to_arm_shiftreg;
  28 reg [7:0] pck_divider;
  29 reg clk_state;
  30
  31 // Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
  32 wire tag_modulation = ssp_dout & !lf_field;
  33 wire reader_modulation = !ssp_dout & lf_field & clk_state;
  34
  35 // always on (High Frequency outputs, unused)
  36 assign pwr_oe1 = 1'b0;
  37 assign pwr_hi = 1'b0;
  38
  39 // low frequency outputs
  40 assign pwr_lo = reader_modulation;
  41 assign pwr_oe2 = 1'b0;  // 33 Ohms
  42 assign pwr_oe3 = tag_modulation; // base antenna load = 33 Ohms
  43 assign pwr_oe4 = 1'b0;  // 10k Ohms
  44
  45 // Debug Output ADC clock
  46 assign dbg = adc_clk;
  47
  48 // ADC clock out of phase with antenna driver
  49 assign adc_clk = ~clk_state;
  50
  51 // serialized SSP data is gated by clk_state to suppress unwanted signal
  52 assign ssp_din = to_arm_shiftreg[7] && !clk_state;
  53
  54 // SSP clock always runs at 24MHz
  55 assign ssp_clk = pck0;
  56
  57 // SSP frame is gated by clk_state and goes high when pck_divider=8..15
  58 assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
  59
  60 // divide 24mhz down to 3mhz
  61 always @(posedge pck0)
  62 begin
  63     if (pck_divider == divisor[7:0])
  64   begin
  65         pck_divider <= 8'd0;
  66         clk_state = !clk_state;
  67   end
  68     else
  69     begin
  70         pck_divider <= pck_divider + 1;
  71     end
  72 end
  73
  74 // this task also runs at pck0 frequency (24Mhz) and is used to serialize
  75 // the ADC output which is then clocked into the ARM SSP.
  76 always @(posedge pck0)
  77 begin
  78     if ((pck_divider == 8'd7) && !clk_state)
  79         to_arm_shiftreg <= adc_d;
  80     else begin
  81         to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
  82         // simulation showed a glitch occuring due to the LSB of the shifter
  83         // not being set as we shift bits out
  84         // this ensures the ssp_din remains low after a transfer and suppresses
  85         // the glitch that would occur when the last data shifted out ended in
  86         // a 1 bit and the next data shifted out started with a 0 bit
  87         to_arm_shiftreg[0] <= 1'b0;
  88     end
  89 end
  90
  91 endmodule