fpga/hi_get_trace.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // piwi, Feb 2019
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_get_trace(
   7        ck_1356megb,
   8        adc_d, trace_enable, major_mode,
   9        ssp_frame, ssp_din, ssp_clk
  10 );
  11     input ck_1356megb;
  12     input [7:0] adc_d;
  13     input trace_enable;
  14     input [2:0] major_mode;
  15     output ssp_frame, ssp_din, ssp_clk;
  16
  17 // clock divider
  18 reg [6:0] clock_cnt;
  19 always @(negedge ck_1356megb)
  20 begin
  21     clock_cnt <= clock_cnt + 1;
  22 end
  23
  24 // sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
  25 reg [2:0] sample_clock;
  26 always @(negedge ck_1356megb)
  27 begin
  28     if (sample_clock == 3'd7)
  29         sample_clock <= 3'd0;
  30     else
  31         sample_clock <= sample_clock + 1;
  32 end
  33
  34
  35 reg [11:0] addr;
  36 reg [11:0] start_addr;
  37 reg [2:0] previous_major_mode;
  38 reg write_enable1;
  39 reg write_enable2;
  40 always @(negedge ck_1356megb)
  41 begin
  42     previous_major_mode <= major_mode;
  43     if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
  44     begin
  45         write_enable1 <= 1'b0;
  46         write_enable2 <= 1'b0;
  47         if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
  48             addr <= start_addr;
  49         if (clock_cnt == 7'd0)
  50         begin
  51             if (addr == 12'd3071)
  52                 addr <= 12'd0;
  53             else
  54                 addr <= addr + 1;
  55         end
  56     end
  57     else if (major_mode != `FPGA_MAJOR_MODE_OFF)
  58     begin
  59         if (trace_enable)
  60         begin
  61             if (addr[11] == 1'b0)
  62             begin
  63                 write_enable1 <= 1'b1;
  64                 write_enable2 <= 1'b0;
  65             end
  66             else
  67             begin
  68                 write_enable1 <= 1'b0;
  69                 write_enable2 <= 1'b1;
  70             end
  71             if (sample_clock == 3'b000)
  72             begin
  73                 if (addr == 12'd3071)
  74                 begin
  75                     addr <= 12'd0;
  76                     write_enable1 <= 1'b1;
  77                     write_enable2 <= 1'b0;
  78                 end
  79                 else
  80                                 begin
  81                     addr <= addr + 1;
  82                                 end
  83             end
  84         end
  85         else
  86         begin
  87             write_enable1 <= 1'b0;
  88             write_enable2 <= 1'b0;
  89             start_addr <= addr;
  90         end
  91     end
  92     else // major_mode == `FPGA_MAJOR_MODE_OFF
  93     begin
  94         write_enable1 <= 1'b0;
  95         write_enable2 <= 1'b0;
  96         if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
  97                 begin
  98             start_addr <= addr;
  99                 end
 100     end
 101 end
 102
 103
 104 // (2+1)k RAM
 105 reg [7:0] D_out1, D_out2;
 106 reg [7:0] ram1 [2047:0]; // 2048  u8
 107 reg [7:0] ram2 [1023:0]; // 1024  u8
 108
 109 always @(negedge ck_1356megb)
 110 begin
 111     if (write_enable1)
 112     begin
 113         ram1[addr[10:0]] <= adc_d;
 114         D_out1 <= adc_d;
 115     end
 116     else
 117         D_out1 <= ram1[addr[10:0]];
 118     if (write_enable2)
 119 begin
 120         ram2[addr[9:0]] <= adc_d;
 121         D_out2 <= adc_d;
 122     end
 123     else
 124         D_out2 <= ram2[addr[9:0]];
 125 end
 126
 127
 128 // SSC communication to ARM
 129 reg ssp_clk;
 130 reg ssp_frame;
 131 reg [7:0] shift_out;
 132
 133 always @(negedge ck_1356megb)
 134 begin
 135     if (clock_cnt[3:0] == 4'd0)        // update shift register every 16 clock cycles
 136     begin
 137         if (clock_cnt[6:4] == 3'd0)    // either load new value
 138         begin
 139                     if (addr[11] == 1'b0)
 140                         shift_out <= D_out1;
 141                     else
 142                         shift_out <= D_out2;
 143         end
 144         else
 145                 begin
 146                           // or shift left
 147                     shift_out[7:1] <= shift_out[6:0];
 148                 end
 149     end
 150
 151     ssp_clk <= ~clock_cnt[3];       // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
 152
 153     if (clock_cnt[6:4] == 3'b000)    // set ssp_frame for 0...31
 154         ssp_frame <= 1'b1;
 155     else
 156         ssp_frame <= 1'b0;
 157
 158 end
 159
 160 assign ssp_din = shift_out[7];
 161
 162 endmodule