fpga/Makefile

   1 #
   2 # FPGA Makefile for all targets
   3 #
   4 # The top part of this Makefile is used to define custom options for a number of compilation targets
   5 # To define an additional target simply look at the other defined targets and add a new TARGET entry with a unique number and the custom options required
   6
   7 XILINX_TOOLS_PREFIX=
   8
   9 # Copy update (only when destination is older or missing)
  10 CP = cp -u
  11
  12 # Make directory, no error if already existing
  13 MKDIR = mkdir -p
  14
  15 # Remove recursive, force
  16 RMDIR = rm -rf
  17
  18 # Path to make
  19 MAKE = make
  20
  21 # Custom prefix for build directories, each target is built into its own separate directory name formed by combining the PREFIX and TARGET names.
  22 # This way the source is not polluted with build files and the build directories are left behind after compilation so logs and reports can be
  23 # examined or can be easily deleted with "make clean"
  24 PREFIX = __
  25
  26 # Options to be passed to XST
  27 XST_OPTS_BASE  = run
  28 XST_OPTS_BASE += -ifn xst.prj
  29 XST_OPTS_BASE += -ifmt mixed
  30 XST_OPTS_BASE += -ofmt NGC
  31 XST_OPTS_BASE += -lso xst.lso
  32 XST_OPTS_BASE += -top fpga_top
  33 XST_OPTS_BASE += -resource_sharing yes
  34
  35 # Optimizations for speed (default)
  36 XST_OPTS_SPEED  = -opt_mode Speed
  37 XST_OPTS_SPEED += -opt_level 1
  38 XST_OPTS_SPEED += -fsm_style lut
  39 XST_OPTS_SPEED += -fsm_encoding auto
  40
  41 # Optimization for reduced space
  42 XST_OPTS_AREA  = -opt_mode area
  43 XST_OPTS_AREA += -opt_level 2
  44 XST_OPTS_AREA += -fsm_style bram
  45 XST_OPTS_AREA += -fsm_encoding compact
  46
  47 # Types of selective module compilation:
  48 # WITH_LF  Enables selection of LF modules (and disables all HF)
  49
  50 # To enable these modules WITH_LF _MUST_ be defined
  51 # WITH_LF0 enable LF reader (generic)
  52 # WITH_LF1 enable LF edge detect (generic)
  53 # WITH_LF2 enable LF passthrough
  54 # WITH_LF3 enable LF ADC (read/write)
  55
  56 # To enable these modules WITH_LF _MUST_NOT_ be defined
  57 # WITH_HF0 enable HF reader (see also WITH_HF_15 below)
  58 # WITH_HF_15 select "iso15 2sc mode" extensions instead of original
  59 # WITH_HF1 enable HF simulated tag
  60 # WITH_HF2 enable HF ISO14443-A
  61 # WITH_HF3 enable sniff
  62 # WITH_HF4 enable HF ISO18092 FeliCa
  63 # WITH_HF5 enable HF get trace
  64
  65 # RDV40/Generic - Enable LF and all the LF modules
  66 TARGET1_OPTIONS = -define \{WITH_LF WITH_LF0 WITH_LF1 WITH_LF2 WITH_LF3\}
  67 # RDV40/Generic - Enable all HF modules except Felica
  68 TARGET2_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF2 WITH_HF3 WITH_HF5\}
  69 # RDV40/Generic - Enable all HF modules except Felica and ISO14443, select HF_15 instead of HF
  70 TARGET3_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF5 WITH_HF_15 WITH_HF_15_LOWSIGNAL\}
  71 # RDV40/Generic - Enable all HF modules except ISO14443
  72 TARGET4_OPTIONS = -define \{WITH_HF0 WITH_HF1 WITH_HF3 WITH_HF4 WITH_HF5\}
  73 # ICOPYX
  74 TARGET5_OPTIONS = -define {PM3ICOPYX} -rtlview Yes
  75
  76 # Here we list the target names
  77 TARGET1_NAME = fpga_pm3_lf
  78 TARGET2_NAME = fpga_pm3_hf
  79 TARGET3_NAME = fpga_pm3_hf_15
  80 TARGET4_NAME = fpga_pm3_felica
  81 TARGET5_NAME = fpga_icopyx_hf
  82
  83 # Targets can be compiled for different FPGA flavours
  84 TARGET1_FPGA = xc2s30-5-vq100
  85 TARGET2_FPGA = $(TARGET1_FPGA)
  86 TARGET3_FPGA = $(TARGET1_FPGA)
  87 TARGET4_FPGA = $(TARGET1_FPGA)
  88 TARGET5_FPGA = xc3s100e-4-vq100
  89
  90 # Assemble the final XST options for each target
  91 TARGET1_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET1_FPGA) -ofn $(TARGET1_NAME) $(TARGET1_OPTIONS)
  92 TARGET2_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET2_FPGA) -ofn $(TARGET2_NAME) $(TARGET2_OPTIONS)
  93 TARGET3_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET3_FPGA) -ofn $(TARGET3_NAME) $(TARGET3_OPTIONS)
  94 TARGET4_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_AREA)  -p $(TARGET4_FPGA) -ofn $(TARGET4_NAME) $(TARGET4_OPTIONS)
  95 TARGET5_XST_OPTS = $(XST_OPTS_BASE) $(XST_OPTS_SPEED) -p $(TARGET5_FPGA) -ofn $(TARGET5_NAME) $(TARGET5_OPTIONS)
  96
  97 # these files are common for all targets
  98 TARGET_COMMON_FILES  = define.v
  99 TARGET_COMMON_FILES += mux8.v
 100 TARGET_COMMON_FILES += clk_divider.v
 101 TARGET_COMMON_FILES += lp20khz_1MSa_iir_filter.v
 102 TARGET_COMMON_FILES += min_max_tracker.v
 103 TARGET_COMMON_FILES += hi_flite.v
 104 TARGET_COMMON_FILES += hi_get_trace.v
 105 TARGET_COMMON_FILES += hi_iso14443a.v
 106 TARGET_COMMON_FILES += hi_reader.v
 107 TARGET_COMMON_FILES += hi_simulate.v
 108 TARGET_COMMON_FILES += hi_sniffer.v
 109 TARGET_COMMON_FILES += lf_edge_detect.v
 110 TARGET_COMMON_FILES += lo_adc.v
 111 TARGET_COMMON_FILES += lo_edge_detect.v
 112 TARGET_COMMON_FILES += lo_passthru.v
 113 TARGET_COMMON_FILES += lo_read.v
 114
 115 # Add the files that are unique per target and all the common files
 116 TARGET1_FILES = $(TARGET_COMMON_FILES) fpga_pm3_top.v
 117 TARGET2_FILES = $(TARGET1_FILES)
 118 TARGET3_FILES = $(TARGET1_FILES)
 119 TARGET4_FILES = $(TARGET1_FILES)
 120 TARGET5_FILES = $(TARGET_COMMON_FILES) mux2_onein.v mux2_oneout.v fpga_icopyx_hf.v fpga_icopyx_lf.v fpga_icopyx_top.v
 121
 122 # List of all valid target FPGA images to build
 123 TARGETS = $(TARGET1_NAME) $(TARGET2_NAME) $(TARGET3_NAME) $(TARGET4_NAME) $(TARGET5_NAME)
 124
 125 #  Verbosity type for ISE tools ise|xflow|silent
 126 VERBOSITY = -intstyle silent
 127 # Echo (Q=) or not echo (Q=@) build commands to the terminal
 128 Q=@
 129
 130 # Pass the custom variables to the lower make rules
 131 $(TARGET1_NAME).bit: TARGET_FPGA = $(TARGET1_FPGA)
 132 $(TARGET1_NAME).bit: TARGET_FILES = $(TARGET1_FILES)
 133 $(TARGET1_NAME).bit: TARGET_XST_OPTS = $(TARGET1_XST_OPTS)
 134
 135 $(TARGET2_NAME).bit: TARGET_FPGA = $(TARGET2_FPGA)
 136 $(TARGET2_NAME).bit: TARGET_FILES = $(TARGET2_FILES)
 137 $(TARGET2_NAME).bit: TARGET_XST_OPTS = $(TARGET2_XST_OPTS)
 138
 139 $(TARGET3_NAME).bit: TARGET_FPGA = $(TARGET3_FPGA)
 140 $(TARGET3_NAME).bit: TARGET_FILES = $(TARGET3_FILES)
 141 $(TARGET3_NAME).bit: TARGET_XST_OPTS = $(TARGET3_XST_OPTS)
 142
 143 $(TARGET4_NAME).bit: TARGET_FPGA = $(TARGET4_FPGA)
 144 $(TARGET4_NAME).bit: TARGET_FILES = $(TARGET4_FILES)
 145 $(TARGET4_NAME).bit: TARGET_XST_OPTS = $(TARGET4_XST_OPTS)
 146
 147 $(TARGET5_NAME).bit: TARGET_FPGA = $(TARGET5_FPGA)
 148 $(TARGET5_NAME).bit: TARGET_FILES = $(TARGET5_FILES)
 149 $(TARGET5_NAME).bit: TARGET_XST_OPTS = $(TARGET5_XST_OPTS)
 150
 151 $(TARGETS):
 152         $(Q)$(MKDIR) $(PREFIX)build_$@
 153         $(Q)$(MAKE) -C $(PREFIX)build_$@ -f ../Makefile $(notdir $@).bit
 154
 155 work:
 156         $(Q)$(RM) xst.prj
 157         $(Q)for item in $(TARGET_FILES); do echo verilog work ../$$item>>xst.prj; done
 158         $(Q)echo work> xst.lso
 159
 160 %.xst: work
 161         $(Q)$(RM) $@
 162         $(Q)echo $(TARGET_XST_OPTS)> $@
 163
 164 %.ngc: %.xst
 165         $(Q)$(RM) $@
 166         $(info [-] XST $@)
 167         $(Q)$(XILINX_TOOLS_PREFIX)xst $(VERBOSITY) -ifn $<
 168
 169 %.ngd: %.ngc
 170         $(Q)$(RM) $@
 171         $(info [-] NGD $@)
 172         $(Q)$(XILINX_TOOLS_PREFIX)ngdbuild $(VERBOSITY) -quiet -p $(TARGET_FPGA) -nt timestamp -uc ../$(TARGET_FPGA).ucf $< $@
 173
 174 %_map.ncd: %.ngd
 175         $(Q)$(RM) $@
 176         $(info [-] MAP $@)
 177         $(Q)$(XILINX_TOOLS_PREFIX)map $(VERBOSITY) -p $(TARGET_FPGA) -o $*_map $*
 178
 179 %.ncd: %_map.ncd
 180         $(Q)$(RM) $@
 181         $(info [-] PAR $@)
 182         $(Q)$(XILINX_TOOLS_PREFIX)par $(VERBOSITY) -w $< $@
 183
 184 %.bit: %.ncd
 185         # Hacky hack, make empty files for icopyx
 186         if echo "$@" | grep -qi "icopyx"; then \
 187                 truncate -s0 ../fpga_icopyx_lf.bit; \
 188                 truncate -s0 ../fpga_icopyx_hf_15.bit; \
 189                 truncate -s0 ../fpga_icopyx_felica.bit; \
 190         fi
 191         $(Q)$(RM) $@ $*.drc $*.rbt
 192         $(info [=] BITGEN $@)
 193         $(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
 194         $(Q)$(CP) $@ ..
 195
 196 # Build all targets
 197 all: $(TARGETS)
 198
 199 # ALWAYS have some hardcoded text after $(PREFIX) to avoid rm -rf * or rm -rf /* situations if PREFIX is incorrectly set to empty "" or just "/"
 200 clean:
 201         $(Q)$(RMDIR) $(PREFIX)build_*
 202         $(info [-] Build files deleted)
 203
 204 .DEFAULT:
 205         @if [ "$@" != "all" ] && [ ! "$(filter $@,$(TARGETS))" ]; then \
 206                 make help; \
 207         else \
 208                 make all; \
 209         fi
 210
 211 .PHONY: all help clean
 212
 213 help:
 214         @echo "################################################################"
 215         @echo "#"
 216         @echo "#   <target> - Builds only one of the above listed targets"
 217         @echo "#   all      - Builds the FPGA bitstreams for all targets"
 218         @echo "#   clean    - Keeps .bit files but cleans intermediate build files for all targets"
 219         @echo "#"
 220         @echo "#"
 221         @echo "# Valid targets are:"
 222         @echo "#   $(TARGETS)"
 223         @echo "#"
 224         @echo "################################################################"
 225