armsrc/fpgaloader.h

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 // Routines to load the FPGA image, and then to configure the FPGA's major
  17 // mode once it is configured.
  18 //-----------------------------------------------------------------------------
  19 #ifndef __FPGALOADER_H
  20 #define __FPGALOADER_H
  21
  22 #include "common.h"
  23 #include "fpga.h"
  24
  25 #define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
  26 #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
  27
  28 /*
  29  Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
  30  Send 16 bit command / data pair to FPGA with the bit format:
  31
  32 +------ frame layout circa 2020 ------------------+
  33 | 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 |
  34 +-------------------------------------------------+
  35 |  C  C  C  C  M  M  M  M  P  P  P  P  P  P  P  P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
  36 |  C  C  C  C              D  D  D  D  D  D  D  D | C = FPGA_CMD_SET_DIVISOR, D = divisor
  37 |  C  C  C  C              T  T  T  T  T  T  T  T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
  38 |  C  C  C  C                                   E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
  39 +-------------------------------------------------+
  40
  41 +------ frame layout current ---------------------+
  42 | 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 |
  43 +-------------------------------------------------+
  44 |  C  C  C  C           M  M  M  P  P  P  P  P  P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
  45 |  C  C  C  C              D  D  D  D  D  D  D  D | C = FPGA_CMD_SET_DIVISOR, D = divisor
  46 |  C  C  C  C              T  T  T  T  T  T  T  T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
  47 |  C  C  C  C                                   E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
  48 +-------------------------------------------------+
  49
  50   shift_reg receive this 16bit frame
  51
  52   LF command
  53   ----------
  54   shift_reg[15:12] == 4bit command
  55   LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
  56   Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
  57
  58   LF data
  59   -------
  60   shift_reg[11:0] == 12bit data
  61   lf data is divided into MAJOR MODES and configuration values.
  62
  63   The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
  64     000 FPGA_MAJOR_MODE_LF_READER        = Act as LF reader (modulate)
  65     001 FPGA_MAJOR_MODE_LF_EDGE_DETECT   = Simulate LF
  66     010 FPGA_MAJOR_MODE_LF_PASSTHRU      = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
  67     011 FPGA_MAJOR_MODE_LF_ADC           = refactor hitag 2, clear ADC sampling
  68     111 FPGA_MAJOR_MODE_OFF              = turn off sampling.
  69
  70   Each one of this major modes can have options. Currently these two major modes uses options.
  71    - FPGA_MAJOR_MODE_LF_READER
  72    - FPGA_MAJOR_MODE_LF_EDGE_DETECT
  73
  74    FPGA_MAJOR_MODE_LF_READER
  75    -------------------------------------
  76     lf_field = 1bit  (FPGA_LF_ADC_READER_FIELD)
  77
  78     You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
  79     divisor = 8bits shift_reg[7:0]
  80
  81    FPGA_MAJOR_MODE_LF_EDGE_DETECT
  82    ------------------------------------------
  83     lf_ed_toggle_mode = 1bits
  84     lf_ed_threshold = 8bits threshold defaults to 127
  85
  86     You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
  87     lf_ed_threshold = 8bits threshold value.
  88
  89   conf_word 12bits
  90     conf_word[7:5]  = 3bit major mode.
  91     conf_word[0]    = 1bit lf_field
  92     conf_word[1]    = 1bit lf_ed_toggle_mode
  93     conf_word[7:0]  = 8bit divisor
  94     conf_word[7:0]  = 8bit threshold
  95
  96 */
  97 // Defining commands, modes and options. This must be aligned to the definitions in fpga/define.v
  98 #define FPGA_MAJOR_MODE_MASK                        0x01C0
  99 #define FPGA_MINOR_MODE_MASK                        0x003F
 100
 101 // Definitions for the FPGA commands.
 102 #define FPGA_CMD_SET_CONFREG                        (1<<12)
 103 #define FPGA_CMD_SET_DIVISOR                        (2<<12)
 104 #define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD          (3<<12)
 105 #define FPGA_CMD_TRACE_ENABLE                       (2<<12)
 106
 107 // Major modes
 108 #define FPGA_MAJOR_MODE_LF_READER                   (0<<6)
 109 #define FPGA_MAJOR_MODE_LF_EDGE_DETECT              (1<<6)
 110 #define FPGA_MAJOR_MODE_LF_PASSTHRU                 (2<<6)
 111 #define FPGA_MAJOR_MODE_LF_ADC                      (3<<6)
 112
 113 #define FPGA_MAJOR_MODE_HF_READER                   (0<<6)
 114 #define FPGA_MAJOR_MODE_HF_SIMULATOR                (1<<6)
 115 #define FPGA_MAJOR_MODE_HF_ISO14443A                (2<<6)
 116 #define FPGA_MAJOR_MODE_HF_SNIFF                    (3<<6)
 117 #define FPGA_MAJOR_MODE_HF_ISO18092                 (4<<6)
 118 #define FPGA_MAJOR_MODE_HF_GET_TRACE                (5<<6)
 119 #define FPGA_MAJOR_MODE_OFF                         (7<<6)
 120
 121 // Options for LF_READER
 122 #define FPGA_LF_ADC_READER_FIELD                    ( 1 )
 123
 124 // Options for LF_EDGE_DETECT
 125 #define FPGA_LF_EDGE_DETECT_READER_FIELD            ( 1 )
 126 #define FPGA_LF_EDGE_DETECT_TOGGLE_MODE             ( 2 )
 127
 128 // Options for the generic HF reader
 129 #define FPGA_HF_READER_MODE_RECEIVE_IQ              ( 0 )
 130 #define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE       ( 1 )
 131 #define FPGA_HF_READER_MODE_RECEIVE_PHASE           ( 2 )
 132 #define FPGA_HF_READER_MODE_SEND_FULL_MOD           ( 3 )
 133 #define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD        ( 4 )
 134 #define FPGA_HF_READER_MODE_SNIFF_IQ                ( 5 )
 135 #define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE         ( 6 )
 136 #define FPGA_HF_READER_MODE_SNIFF_PHASE             ( 7 )
 137 #define FPGA_HF_READER_MODE_SEND_JAM                ( 8 )
 138 #define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4   ( 9 )
 139
 140 #define FPGA_HF_READER_SUBCARRIER_848_KHZ           (0<<4)
 141 #define FPGA_HF_READER_SUBCARRIER_424_KHZ           (1<<4)
 142 #define FPGA_HF_READER_SUBCARRIER_212_KHZ           (2<<4)
 143 #define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ     (3<<4)
 144
 145 // Options for the HF simulated tag, how to modulate
 146 #define FPGA_HF_SIMULATOR_NO_MODULATION             ( 0 )
 147 #define FPGA_HF_SIMULATOR_MODULATE_BPSK             ( 1 )
 148 #define FPGA_HF_SIMULATOR_MODULATE_212K             ( 2 )
 149 #define FPGA_HF_SIMULATOR_MODULATE_424K             ( 4 )
 150 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT        ( 5 )
 151
 152 // Options for ISO14443A
 153 #define FPGA_HF_ISO14443A_SNIFFER                   ( 0 )
 154 #define FPGA_HF_ISO14443A_TAGSIM_LISTEN             ( 1 )
 155 #define FPGA_HF_ISO14443A_TAGSIM_MOD                ( 2 )
 156 #define FPGA_HF_ISO14443A_READER_LISTEN             ( 3 )
 157 #define FPGA_HF_ISO14443A_READER_MOD                ( 4 )
 158
 159 // Options for ISO18092 / Felica
 160 #define FPGA_HF_ISO18092_FLAG_NOMOD                 ( 1 ) // 0001 disable modulation module
 161 #define FPGA_HF_ISO18092_FLAG_424K                  ( 2 ) // 0010 should enable 414k mode (untested). No autodetect
 162 #define FPGA_HF_ISO18092_FLAG_READER                ( 4 ) // 0100 enables antenna power, to act as a reader instead of tag
 163
 164 void FpgaSendCommand(uint16_t cmd, uint16_t v);
 165 void FpgaWriteConfWord(uint16_t v);
 166 void FpgaEnableTracing(void);
 167 void FpgaDisableTracing(void);
 168 void FpgaDownloadAndGo(int bitstream_target);
 169 // void FpgaGatherVersion(int bitstream_target, char *dst, int len);
 170 void FpgaSetupSsc(uint16_t fpga_mode);
 171 void SetupSpi(int mode);
 172 bool FpgaSetupSscDma(uint8_t *buf, uint16_t len);
 173 void Fpga_print_status(void);
 174 int FpgaGetCurrent(void);
 175 void SetAdcMuxFor(uint32_t whichGpio);
 176
 177 // extern and generel turn off the antenna method
 178 void switch_off(void);
 179
 180 #endif