updated the uniq.yaml workflow to be case insensitive
[RRG-proxmark3.git] / fpga / hi_simulate.v
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1 //-----------------------------------------------------------------------------
2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
3 //
4 // This program is free software: you can redistribute it and/or modify
5 // it under the terms of the GNU General Public License as published by
6 // the Free Software Foundation, either version 3 of the License, or
7 // (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful,
10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 // GNU General Public License for more details.
14 // See LICENSE.txt for the text of the license.
15 //-----------------------------------------------------------------------------
17 // Pretend to be an ISO 14443 tag. We will do this by alternately short-
18 // circuiting and open-circuiting the antenna coil, with the tri-state
19 // pins.
21 // We communicate over the SSP, as a bitstream (i.e., might as well be
22 // unframed, though we still generate the word sync signal). The output
23 // (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
24 // -> ARM) is us using the A/D as a fancy comparator; this is with
25 // (software-added) hysteresis, to undo the high-pass filter.
27 // At this point only Type A is implemented. This means that we are using a
28 // bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
29 // things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
31 // Jonathan Westhues, October 2006
32 //-----------------------------------------------------------------------------
34 module hi_simulate(
35 input ck_1356meg,
36 input [7:0] adc_d,
37 input [3:0] mod_type,
38 input ssp_dout,
40 output reg ssp_din,
41 output reg ssp_frame,
42 output reg ssp_clk,
43 output adc_clk,
44 output pwr_lo,
45 output pwr_hi,
46 output pwr_oe1,
47 output pwr_oe2,
48 output pwr_oe3,
49 output pwr_oe4,
50 output debug
53 // Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
54 // always be low.
55 assign pwr_hi = 1'b0; // HF antenna connected to GND
56 assign pwr_lo = 1'b0; // LF antenna connected to GND
58 // This one is all LF, so doesn't matter
59 assign pwr_oe2 = 1'b0;
61 assign adc_clk = ck_1356meg;
62 assign debug = ssp_frame;
64 // The comparator with hysteresis on the output from the peak detector.
65 reg after_hysteresis;
66 reg [11:0] has_been_low_for;
68 always @(negedge adc_clk)
69 begin
70 if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
71 else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
73 if (adc_d >= 224)
74 begin
75 has_been_low_for <= 12'd0;
76 end
77 else
78 begin
79 if (has_been_low_for == 12'd4095)
80 begin
81 has_been_low_for <= 12'd0;
82 after_hysteresis <= 1'b1;
83 end
84 else
85 begin
86 has_been_low_for <= has_been_low_for + 1;
87 end
88 end
89 end
91 // Divide 13.56 MHz to produce various frequencies for SSP_CLK
92 // and modulation.
93 reg [8:0] ssp_clk_divider;
95 always @(negedge adc_clk)
96 ssp_clk_divider <= (ssp_clk_divider + 1);
98 always @(negedge adc_clk)
99 begin
100 if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
101 // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
102 ssp_clk <= ~ssp_clk_divider[7];
103 else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
104 // Get next bit at 212kHz
105 ssp_clk <= ~ssp_clk_divider[5];
106 else
107 // Get next bit at 424kHz
108 ssp_clk <= ~ssp_clk_divider[4];
111 // Produce the byte framing signal; the phase of this signal
112 // is arbitrary, because it's just a bit stream in this module.
113 always @(negedge adc_clk)
114 begin
115 if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
116 begin
117 if (ssp_clk_divider[8:5] == 4'd1)
118 ssp_frame <= 1'b1;
119 if (ssp_clk_divider[8:5] == 4'd5)
120 ssp_frame <= 1'b0;
122 else
123 begin
124 if (ssp_clk_divider[7:4] == 4'd1)
125 ssp_frame <= 1'b1;
126 if (ssp_clk_divider[7:4] == 4'd5)
127 ssp_frame <= 1'b0;
131 // Synchronize up the after-hysteresis signal, to produce DIN.
132 always @(posedge ssp_clk)
133 ssp_din = after_hysteresis;
135 // Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
136 reg modulating_carrier;
137 always @(*)
138 if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
139 modulating_carrier <= 1'b0; // no modulation
140 else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
141 modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
142 else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
143 modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
144 else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
145 modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
146 else
147 modulating_carrier <= 1'b0; // yet unused
149 // Load modulation. Toggle only one of these, since we are already producing much deeper
150 // modulation than a real tag would.
151 assign pwr_oe1 = 1'b0; // 33 Ohms Load
152 assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
153 // This one is always on, so that we can watch the carrier.
154 assign pwr_oe3 = 1'b0; // 10k Load
156 endmodule