fpga/fpga_pm3_top.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
  18 // and the ARM. In the low-frequency modes it passes the data straight
  19 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
  20 // frequency modes, the FPGA might perform some demodulation first, to
  21 // reduce the amount of data that we must send to the ARM.
  22 //-----------------------------------------------------------------------------
  23
  24 // These defines are for reference only, they are passed by the Makefile so do not uncomment them here
  25 // Proxmark3 RDV4 target
  26 //`define PM3RDV4
  27 // Proxmark3 generic target
  28 //`define PM3GENERIC
  29 // iCopy-X with XC3S100E
  30 //`define PM3ICOPYX
  31
  32 // Pass desired defines to compiler to enable required modules
  33 // WITH_LF  enables Low Frequency mode when defined else HF is enabled
  34 //`define WITH_LF
  35 // WITH_LF0 enables module reader
  36 //`define WITH_LF0
  37 // WITH_LF1 enables module edge detect
  38 //`define WITH_LF1
  39 // WITH_LF2 enables module passthrough
  40 //`define WITH_LF2
  41 // WITH_LF3 enables module ADC
  42 //`define WITH_LF3
  43
  44 // WITH_HF0 enables module HF reader
  45 //`define WITH_HF0
  46 // WITH_HF1 enables module simulated tag
  47 //`define WITH_HF1
  48 // WITH_HF2 enables module ISO14443-A
  49 //`define WITH_HF2
  50 // WITH_HF3 enables module sniff
  51 //`define WITH_HF3
  52 // WITH_HF4 enables module ISO18092 FeliCa
  53 //`define WITH_HF4
  54 // WITH_HF5 enables module get trace
  55 //`define WITH_HF5
  56
  57 //`ifdef WITH_LF  `include "clk_divider.v"    `endif
  58 //`ifdef WITH_LF0 `include "lo_read.v"        `endif
  59 //`ifdef WITH_LF1 `include "lo_edge_detect.v" `endif
  60 //`ifdef WITH_LF2 `include "lo_passthru.v"    `endif
  61 //`ifdef WITH_LF3 `include "lo_adc.v"         `endif
  62 //
  63 //`ifdef WITH_HF0 `include "hi_reader.v"      `endif
  64 //`ifdef WITH_HF1 `include "hi_simulate.v"    `endif
  65 //`ifdef WITH_HF2 `include "hi_iso14443a.v"   `endif
  66 //`ifdef WITH_HF3 `include "hi_sniffer.v"     `endif
  67 //`ifdef WITH_HF4 `include "hi_flite.v"       `endif
  68 //`ifdef WITH_HF5 `include "hi_get_trace.v"   `endif
  69
  70 module fpga_top(
  71     input ck_1356meg,
  72     input ck_1356megb,
  73     input spck,
  74     input pck0,
  75     input ncs,
  76     input [7:0] adc_d,
  77     input cross_hi,
  78     input cross_lo,
  79     input mosi,
  80     input ssp_dout,
  81
  82     output ssp_din,
  83     output ssp_frame,
  84     output ssp_clk,
  85     output adc_clk,
  86     output adc_noe,
  87     output miso,
  88     output pwr_lo,
  89     output pwr_hi,
  90     output pwr_oe1,
  91     output pwr_oe2,
  92     output pwr_oe3,
  93     output pwr_oe4,
  94     output dbg
  95 );
  96
  97 // In all modes, let the ADC's outputs be enabled.
  98 assign adc_noe = 1'b0;
  99
 100 //-----------------------------------------------------------------------------
 101 // The SPI receiver. This sets up the configuration word, which the rest of
 102 // the logic looks at to determine how to connect the A/D and the coil
 103 // drivers (i.e., which section gets it). Also assign some symbolic names
 104 // to the configuration bits, for use below.
 105 //-----------------------------------------------------------------------------
 106
 107 // Receive 16bits of data from ARM here.
 108 reg [15:0] shift_reg;
 109 always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
 110
 111 reg trace_enable;
 112
 113 reg [7:0] lf_ed_threshold;
 114 reg [5:0] hf_edge_detect_threshold;
 115 reg [5:0] hf_edge_detect_threshold_high;
 116
 117 // adjustable frequency clock
 118 wire [7:0] pck_cnt;
 119 wire pck_divclk;
 120 reg [7:0] divisor;
 121 clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
 122
 123 `ifdef WITH_LF
 124 reg [11:0] conf_word;
 125 `else
 126 reg [8:0] conf_word;
 127 `endif
 128
 129 initial
 130 begin
 131     hf_edge_detect_threshold <= 7;
 132     hf_edge_detect_threshold_high <= 20;
 133 end
 134
 135 // We switch modes between transmitting to the 13.56 MHz tag and receiving
 136 // from it, which means that we must make sure that we can do so without
 137 // glitching, or else we will glitch the transmitted carrier.
 138 always @(posedge ncs)
 139 begin
 140     // 4 bit command
 141     case (shift_reg[15:12])
 142 `ifdef WITH_LF
 143         `FPGA_CMD_SET_CONFREG:
 144         begin
 145             // 12 bit data
 146             conf_word <= shift_reg[11:0];
 147             if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT) lf_ed_threshold <= 127;  // default threshold
 148         end
 149
 150         `FPGA_CMD_SET_DIVISOR:
 151             divisor <= shift_reg[7:0]; // 8bits
 152
 153         `FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
 154             lf_ed_threshold <= shift_reg[7:0];  // 8 bits
 155 `else
 156         `FPGA_CMD_SET_CONFREG:  conf_word <= shift_reg[8:0];
 157         `FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
 158         `FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
 159         begin
 160             hf_edge_detect_threshold <= shift_reg[5:0];
 161             hf_edge_detect_threshold_high <= shift_reg[11:6];
 162         end
 163 `endif
 164     endcase
 165 end
 166
 167 //-----------------------------------------------------------------------------
 168 // And then we instantiate the modules corresponding to each of the FPGA's
 169 // major modes, and use muxes to connect the outputs of the active mode to
 170 // the output pins.
 171 //-----------------------------------------------------------------------------
 172
 173 // ############################################################################
 174 // # Enable Low Frequency Modules
 175 `ifdef WITH_LF
 176
 177 //   LF reader (generic)
 178 `ifdef WITH_LF0
 179 lo_read lr(
 180     .pck0              (pck0),
 181     .pck_divclk        (pck_divclk),
 182     .pck_cnt           (pck_cnt),
 183     .adc_d             (adc_d),
 184     .lf_field          (conf_word[0]),
 185
 186     .ssp_din           (mux0_ssp_din),
 187     .ssp_frame         (mux0_ssp_frame),
 188     .ssp_clk           (mux0_ssp_clk),
 189     .adc_clk           (mux0_adc_clk),
 190     .pwr_lo            (mux0_pwr_lo),
 191     .pwr_hi            (mux0_pwr_hi),
 192     .pwr_oe1           (mux0_pwr_oe1),
 193     .pwr_oe2           (mux0_pwr_oe2),
 194     .pwr_oe3           (mux0_pwr_oe3),
 195     .pwr_oe4           (mux0_pwr_oe4),
 196     .debug             (mux0_debug)
 197 );
 198 `endif
 199
 200 //   LF edge detect (generic)
 201 `ifdef WITH_LF1
 202 lo_edge_detect le(
 203     .pck0              (pck0),
 204     .pck_divclk        (pck_divclk),
 205     .adc_d             (adc_d),
 206     .cross_lo          (cross_lo),
 207     .lf_field          (conf_word[0]),
 208     .lf_ed_toggle_mode (conf_word[1]),
 209     .lf_ed_threshold   (lf_ed_threshold),
 210     .ssp_dout          (ssp_dout),
 211
 212     .ssp_frame         (mux1_ssp_frame),
 213     .ssp_clk           (mux1_ssp_clk),
 214     .adc_clk           (mux1_adc_clk),
 215     .pwr_lo            (mux1_pwr_lo),
 216     .pwr_hi            (mux1_pwr_hi),
 217     .pwr_oe1           (mux1_pwr_oe1),
 218     .pwr_oe2           (mux1_pwr_oe2),
 219     .pwr_oe3           (mux1_pwr_oe3),
 220     .pwr_oe4           (mux1_pwr_oe4),
 221     .debug             (mux1_debug)
 222 );
 223 `endif
 224
 225 //   LF passthrough
 226 `ifdef WITH_LF2
 227 lo_passthru lp(
 228     .pck_divclk        (pck_divclk),
 229     .cross_lo          (cross_lo),
 230     .ssp_dout          (ssp_dout),
 231
 232     .ssp_din           (mux2_ssp_din),
 233     .adc_clk           (mux2_adc_clk),
 234     .pwr_lo            (mux2_pwr_lo),
 235     .pwr_hi            (mux2_pwr_hi),
 236     .pwr_oe1           (mux2_pwr_oe1),
 237     .pwr_oe2           (mux2_pwr_oe2),
 238     .pwr_oe3           (mux2_pwr_oe3),
 239     .pwr_oe4           (mux2_pwr_oe4),
 240     .debug             (mux2_debug)
 241 );
 242 `endif
 243
 244 //   LF ADC (read/write)
 245 `ifdef WITH_LF3
 246 lo_adc la(
 247     .pck0              (pck0),
 248     .adc_d             (adc_d),
 249     .divisor           (divisor),
 250     .lf_field          (conf_word[0]),
 251     .ssp_dout          (ssp_dout),
 252
 253     .ssp_din           (mux3_ssp_din),
 254     .ssp_frame         (mux3_ssp_frame),
 255     .ssp_clk           (mux3_ssp_clk),
 256     .adc_clk           (mux3_adc_clk),
 257     .pwr_lo            (mux3_pwr_lo ),
 258     .pwr_hi            (mux3_pwr_hi ),
 259     .pwr_oe1           (mux3_pwr_oe1),
 260     .pwr_oe2           (mux3_pwr_oe2),
 261     .pwr_oe3           (mux3_pwr_oe3),
 262     .pwr_oe4           (mux3_pwr_oe4),
 263     .debug             (mux3_debug)
 264 );
 265 `endif // WITH_LF3
 266
 267 assign mux6_pwr_lo = 1'b1;
 268 //   7 -- SPARE
 269
 270 `else // if WITH_LF not defined
 271 // ############################################################################
 272 // # Enable High Frequency Modules
 273
 274 //   HF reader
 275 `ifdef WITH_HF0
 276 hi_reader hr(
 277     .ck_1356meg (ck_1356megb),
 278     .adc_d      (adc_d),
 279     .subcarrier_frequency (conf_word[5:4]),
 280     .minor_mode (conf_word[3:0]),
 281     .ssp_dout   (ssp_dout),
 282
 283     .ssp_din    (mux0_ssp_din),
 284     .ssp_frame  (mux0_ssp_frame),
 285     .ssp_clk    (mux0_ssp_clk),
 286     .adc_clk    (mux0_adc_clk),
 287     .pwr_lo     (mux0_pwr_lo),
 288     .pwr_hi     (mux0_pwr_hi),
 289     .pwr_oe1    (mux0_pwr_oe1),
 290     .pwr_oe2    (mux0_pwr_oe2),
 291     .pwr_oe3    (mux0_pwr_oe3),
 292     .pwr_oe4    (mux0_pwr_oe4),
 293     .debug      (mux0_debug)
 294 );
 295 `endif // WITH_HF0
 296
 297 //   HF simulated tag
 298 `ifdef WITH_HF1
 299 hi_simulate hs(
 300     .ck_1356meg (ck_1356meg),
 301     .adc_d      (adc_d),
 302     .mod_type   (conf_word[3:0]),
 303     .ssp_dout   (ssp_dout),
 304
 305     .ssp_din    (mux1_ssp_din),
 306     .ssp_frame  (mux1_ssp_frame),
 307     .ssp_clk    (mux1_ssp_clk),
 308     .adc_clk    (mux1_adc_clk),
 309     .pwr_lo     (mux1_pwr_lo),
 310     .pwr_hi     (mux1_pwr_hi),
 311     .pwr_oe1    (mux1_pwr_oe1),
 312     .pwr_oe2    (mux1_pwr_oe2),
 313     .pwr_oe3    (mux1_pwr_oe3),
 314     .pwr_oe4    (mux1_pwr_oe4),
 315     .debug      (mux1_debug)
 316 );
 317 `endif // WITH_HF1
 318
 319 //   HF ISO14443-A
 320 `ifdef WITH_HF2
 321 hi_iso14443a hisn(
 322     .ck_1356meg (ck_1356meg),
 323     .adc_d      (adc_d),
 324     .mod_type   (conf_word[3:0]),
 325     .ssp_dout   (ssp_dout),
 326
 327     .ssp_din    (mux2_ssp_din),
 328     .ssp_frame  (mux2_ssp_frame),
 329     .ssp_clk    (mux2_ssp_clk),
 330     .adc_clk    (mux2_adc_clk),
 331     .pwr_lo     (mux2_pwr_lo),
 332     .pwr_hi     (mux2_pwr_hi),
 333     .pwr_oe1    (mux2_pwr_oe1),
 334     .pwr_oe2    (mux2_pwr_oe2),
 335     .pwr_oe3    (mux2_pwr_oe3),
 336     .pwr_oe4    (mux2_pwr_oe4),
 337     .debug      (mux2_debug),
 338     .edge_detect_threshold (hf_edge_detect_threshold),
 339     .edge_detect_threshold_high (hf_edge_detect_threshold_high)
 340 );
 341 `endif // WITH_HF2
 342
 343 //   HF sniff
 344 `ifdef WITH_HF3
 345 hi_sniffer he(
 346     .ck_1356meg  (ck_1356megb),
 347     .adc_d       (adc_d),
 348
 349     .ssp_din     (mux3_ssp_din),
 350     .ssp_frame   (mux3_ssp_frame),
 351     .ssp_clk     (mux3_ssp_clk),
 352     .adc_clk     (mux3_adc_clk),
 353     .pwr_lo      (mux3_pwr_lo),
 354     .pwr_hi      (mux3_pwr_hi),
 355     .pwr_oe1     (mux3_pwr_oe1),
 356     .pwr_oe2     (mux3_pwr_oe2),
 357     .pwr_oe3     (mux3_pwr_oe3),
 358     .pwr_oe4     (mux3_pwr_oe4)
 359 );
 360 `endif //WITH_HF3
 361
 362 //   HF ISO18092 FeliCa
 363 `ifdef WITH_HF4
 364 hi_flite hfl(
 365     .ck_1356meg  (ck_1356megb),
 366     .adc_d       (adc_d),
 367     .mod_type    (conf_word[3:0]),
 368     .ssp_dout    (ssp_dout),
 369
 370     .ssp_din     (mux4_ssp_din),
 371     .ssp_frame   (mux4_ssp_frame),
 372     .ssp_clk     (mux4_ssp_clk),
 373     .adc_clk     (mux4_adc_clk),
 374     .pwr_lo      (mux4_pwr_lo),
 375     .pwr_hi      (mux4_pwr_hi),
 376     .pwr_oe1     (mux4_pwr_oe1),
 377     .pwr_oe2     (mux4_pwr_oe2),
 378     .pwr_oe3     (mux4_pwr_oe3),
 379     .pwr_oe4     (mux4_pwr_oe4),
 380     .debug       (mux4_debug)
 381 );
 382 `endif // WITH_HF4
 383
 384 //   HF get trace
 385 `ifdef WITH_HF5
 386 hi_get_trace gt(
 387     .ck_1356megb  (ck_1356megb),
 388     .adc_d        (adc_d),
 389     .trace_enable (trace_enable),
 390     .major_mode   (conf_word[8:6]),
 391     .ssp_din      (mux5_ssp_din),
 392     .ssp_frame    (mux5_ssp_frame),
 393     .ssp_clk      (mux5_ssp_clk)
 394 );
 395 `endif // WITH_HF5
 396
 397 `endif // WITH_LF
 398
 399 // These assignments must agree with the defines in fpgaloader.h
 400 // Major modes Low Frequency
 401 //   mux0 = LF reader (generic)
 402 //   mux1 = LF edge detect (generic)
 403 //   mux2 = LF passthrough
 404 //   mux3 = LF ADC (read/write)
 405 //   mux4 = SPARE
 406 //   mux5 = SPARE
 407 //   mux6 = SPARE
 408 //   mux7 = FPGA_MAJOR_MODE_OFF
 409
 410 // Major modes High Frequency
 411 //   mux0 = HF reader
 412 //   mux1 = HF simulated tag
 413 //   mux2 = HF ISO14443-A
 414 //   mux3 = HF sniff
 415 //   mux4 = HF ISO18092 FeliCa
 416 //   mux5 = HF get trace
 417 //   mux6 = unused
 418 //   mux7 = FPGA_MAJOR_MODE_OFF
 419
 420 mux8 mux_ssp_clk   (.sel(conf_word[8:6]), .y(ssp_clk  ), .x0(mux0_ssp_clk  ), .x1(mux1_ssp_clk  ), .x2(mux2_ssp_clk  ), .x3(mux3_ssp_clk  ), .x4(mux4_ssp_clk  ), .x5(mux5_ssp_clk  ), .x6(mux6_ssp_clk  ), .x7(mux7_ssp_clk  ) );
 421 mux8 mux_ssp_din   (.sel(conf_word[8:6]), .y(ssp_din  ), .x0(mux0_ssp_din  ), .x1(mux1_ssp_din  ), .x2(mux2_ssp_din  ), .x3(mux3_ssp_din  ), .x4(mux4_ssp_din  ), .x5(mux5_ssp_din  ), .x6(mux6_ssp_din  ), .x7(mux7_ssp_din  ) );
 422 mux8 mux_ssp_frame (.sel(conf_word[8:6]), .y(ssp_frame), .x0(mux0_ssp_frame), .x1(mux1_ssp_frame), .x2(mux2_ssp_frame), .x3(mux3_ssp_frame), .x4(mux4_ssp_frame), .x5(mux5_ssp_frame), .x6(mux6_ssp_frame), .x7(mux7_ssp_frame) );
 423 mux8 mux_pwr_oe1   (.sel(conf_word[8:6]), .y(pwr_oe1  ), .x0(mux0_pwr_oe1  ), .x1(mux1_pwr_oe1  ), .x2(mux2_pwr_oe1  ), .x3(mux3_pwr_oe1  ), .x4(mux4_pwr_oe1  ), .x5(mux5_pwr_oe1  ), .x6(mux6_pwr_oe1  ), .x7(mux7_pwr_oe1  ) );
 424 mux8 mux_pwr_oe2   (.sel(conf_word[8:6]), .y(pwr_oe2  ), .x0(mux0_pwr_oe2  ), .x1(mux1_pwr_oe2  ), .x2(mux2_pwr_oe2  ), .x3(mux3_pwr_oe2  ), .x4(mux4_pwr_oe2  ), .x5(mux5_pwr_oe2  ), .x6(mux6_pwr_oe2  ), .x7(mux7_pwr_oe2  ) );
 425 mux8 mux_pwr_oe3   (.sel(conf_word[8:6]), .y(pwr_oe3  ), .x0(mux0_pwr_oe3  ), .x1(mux1_pwr_oe3  ), .x2(mux2_pwr_oe3  ), .x3(mux3_pwr_oe3  ), .x4(mux4_pwr_oe3  ), .x5(mux5_pwr_oe3  ), .x6(mux6_pwr_oe3  ), .x7(mux7_pwr_oe3  ) );
 426 mux8 mux_pwr_oe4   (.sel(conf_word[8:6]), .y(pwr_oe4  ), .x0(mux0_pwr_oe4  ), .x1(mux1_pwr_oe4  ), .x2(mux2_pwr_oe4  ), .x3(mux3_pwr_oe4  ), .x4(mux4_pwr_oe4  ), .x5(mux5_pwr_oe4  ), .x6(mux6_pwr_oe4  ), .x7(mux7_pwr_oe4  ) );
 427 mux8 mux_pwr_lo    (.sel(conf_word[8:6]), .y(pwr_lo   ), .x0(mux0_pwr_lo   ), .x1(mux1_pwr_lo   ), .x2(mux2_pwr_lo   ), .x3(mux3_pwr_lo   ), .x4(mux4_pwr_lo   ), .x5(mux5_pwr_lo   ), .x6(mux6_pwr_lo   ), .x7(mux7_pwr_lo   ) );
 428 mux8 mux_pwr_hi    (.sel(conf_word[8:6]), .y(pwr_hi   ), .x0(mux0_pwr_hi   ), .x1(mux1_pwr_hi   ), .x2(mux2_pwr_hi   ), .x3(mux3_pwr_hi   ), .x4(mux4_pwr_hi   ), .x5(mux5_pwr_hi   ), .x6(mux6_pwr_hi   ), .x7(mux7_pwr_hi   ) );
 429 mux8 mux_adc_clk   (.sel(conf_word[8:6]), .y(adc_clk  ), .x0(mux0_adc_clk  ), .x1(mux1_adc_clk  ), .x2(mux2_adc_clk  ), .x3(mux3_adc_clk  ), .x4(mux4_adc_clk  ), .x5(mux5_adc_clk  ), .x6(mux6_adc_clk  ), .x7(mux7_adc_clk  ) );
 430 mux8 mux_dbg       (.sel(conf_word[8:6]), .y(dbg      ), .x0(mux0_debug    ), .x1(mux1_debug    ), .x2(mux2_debug    ), .x3(mux3_debug    ), .x4(mux4_debug    ), .x5(mux5_debug    ), .x6(mux6_debug    ), .x7(mux7_debug    ) );
 431
 432 endmodule