fpga/hi_get_trace.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16
  17 module hi_get_trace(
  18     input ck_1356megb,
  19     input [7:0] adc_d,
  20     input trace_enable,
  21     input [2:0] major_mode,
  22
  23     output ssp_din,
  24     output reg ssp_frame,
  25     output reg ssp_clk
  26 );
  27
  28 // clock divider
  29 reg [6:0] clock_cnt;
  30 always @(negedge ck_1356megb)
  31 begin
  32     clock_cnt <= clock_cnt + 1;
  33 end
  34
  35 // sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
  36 reg [2:0] sample_clock;
  37 always @(negedge ck_1356megb)
  38 begin
  39     if (sample_clock == 3'd7)
  40         sample_clock <= 3'd0;
  41     else
  42         sample_clock <= sample_clock + 1;
  43 end
  44
  45
  46 reg [11:0] addr;
  47 reg [11:0] start_addr;
  48 reg [2:0] previous_major_mode;
  49 reg write_enable1;
  50 reg write_enable2;
  51 always @(negedge ck_1356megb)
  52 begin
  53     previous_major_mode <= major_mode;
  54     if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
  55     begin
  56         write_enable1 <= 1'b0;
  57         write_enable2 <= 1'b0;
  58         if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
  59             addr <= start_addr;
  60         if (clock_cnt == 7'd0)
  61         begin
  62             if (addr == 12'd3071)
  63                 addr <= 12'd0;
  64             else
  65                 addr <= addr + 1;
  66         end
  67     end
  68     else if (major_mode != `FPGA_MAJOR_MODE_OFF)
  69     begin
  70         if (trace_enable)
  71         begin
  72             if (addr[11] == 1'b0)
  73             begin
  74                 write_enable1 <= 1'b1;
  75                 write_enable2 <= 1'b0;
  76             end
  77             else
  78             begin
  79                 write_enable1 <= 1'b0;
  80                 write_enable2 <= 1'b1;
  81             end
  82             if (sample_clock == 3'b000)
  83             begin
  84                 if (addr == 12'd3071)
  85                 begin
  86                     addr <= 12'd0;
  87                     write_enable1 <= 1'b1;
  88                     write_enable2 <= 1'b0;
  89                 end
  90                 else
  91                 begin
  92                     addr <= addr + 1;
  93                 end
  94             end
  95         end
  96         else
  97         begin
  98             write_enable1 <= 1'b0;
  99             write_enable2 <= 1'b0;
 100             start_addr <= addr;
 101         end
 102     end
 103     else // major_mode == `FPGA_MAJOR_MODE_OFF
 104     begin
 105         write_enable1 <= 1'b0;
 106         write_enable2 <= 1'b0;
 107         if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
 108         begin
 109             start_addr <= addr;
 110         end
 111     end
 112 end
 113
 114 // (2+1)k RAM
 115 reg [7:0] D_out1, D_out2;
 116 reg [7:0] ram1 [2047:0]; // 2048  u8
 117 reg [7:0] ram2 [1023:0]; // 1024  u8
 118
 119 always @(negedge ck_1356megb)
 120 begin
 121     if (write_enable1)
 122     begin
 123         ram1[addr[10:0]] <= adc_d;
 124         D_out1 <= adc_d;
 125     end
 126     else
 127         D_out1 <= ram1[addr[10:0]];
 128     if (write_enable2)
 129     begin
 130         ram2[addr[9:0]] <= adc_d;
 131         D_out2 <= adc_d;
 132     end
 133     else
 134         D_out2 <= ram2[addr[9:0]];
 135 end
 136
 137 reg [7:0] shift_out;
 138
 139 always @(negedge ck_1356megb)
 140 begin
 141     if (clock_cnt[3:0] == 4'd0)        // update shift register every 16 clock cycles
 142     begin
 143         if (clock_cnt[6:4] == 3'd0)    // either load new value
 144         begin
 145             if (addr[11] == 1'b0)
 146                 shift_out <= D_out1;
 147             else
 148                 shift_out <= D_out2;
 149         end
 150         else
 151         begin
 152             // or shift left
 153             shift_out[7:1] <= shift_out[6:0];
 154         end
 155     end
 156
 157     ssp_clk <= ~clock_cnt[3];       // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
 158
 159     if (clock_cnt[6:4] == 3'b000)    // set ssp_frame for 0...31
 160         ssp_frame <= 1'b1;
 161     else
 162         ssp_frame <= 1'b0;
 163
 164 end
 165
 166 assign ssp_din = shift_out[7];
 167
 168 endmodule