fpga/lo_adc.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The way that we connect things in low-frequency simulation mode. In this
  18 // case just pass everything through to the ARM, which can bit-bang this
  19 // (because it is so slow).
  20 //
  21 // Jonathan Westhues, April 2006
  22 //-----------------------------------------------------------------------------
  23
  24 module lo_adc(
  25     input pck0,
  26     input [7:0] adc_d,
  27     input [7:0] divisor,
  28     input lf_field,
  29     input ssp_dout,
  30
  31     output ssp_din,
  32     output ssp_frame,
  33     output ssp_clk,
  34     output adc_clk,
  35     output pwr_lo,
  36     output pwr_hi,
  37     output pwr_oe1,
  38     output pwr_oe2,
  39     output pwr_oe3,
  40     output pwr_oe4,
  41     output debug
  42 );
  43
  44 reg [7:0] to_arm_shiftreg;
  45 reg [7:0] pck_divider;
  46 reg clk_state;
  47
  48 // Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
  49 wire tag_modulation = ssp_dout & !lf_field;
  50 wire reader_modulation = !ssp_dout & lf_field & clk_state;
  51
  52 // always on (High Frequency outputs, unused)
  53 assign pwr_oe1 = 1'b0;
  54 assign pwr_hi  = 1'b0;
  55
  56 // low frequency outputs
  57 assign pwr_lo  = reader_modulation;
  58 assign pwr_oe2 = 1'b0;  // 33 Ohms
  59 assign pwr_oe3 = tag_modulation; // base antenna load = 33 Ohms
  60 assign pwr_oe4 = 1'b0;  // 10k Ohms
  61
  62 // Debug Output ADC clock
  63 assign debug = adc_clk;
  64
  65 // ADC clock out of phase with antenna driver
  66 assign adc_clk = ~clk_state;
  67
  68 // serialized SSP data is gated by clk_state to suppress unwanted signal
  69 assign ssp_din = to_arm_shiftreg[7] && !clk_state;
  70
  71 // SSP clock always runs at 24MHz
  72 assign ssp_clk = pck0;
  73
  74 // SSP frame is gated by clk_state and goes high when pck_divider=8..15
  75 assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
  76
  77 // divide 24mhz down to 3mhz
  78 always @(posedge pck0)
  79 begin
  80     if (pck_divider == divisor[7:0])
  81     begin
  82         pck_divider <= 8'd0;
  83         clk_state = !clk_state;
  84     end
  85     else
  86     begin
  87         pck_divider <= pck_divider + 1;
  88     end
  89 end
  90
  91 // this task also runs at pck0 frequency (24Mhz) and is used to serialize
  92 // the ADC output which is then clocked into the ARM SSP.
  93 always @(posedge pck0)
  94 begin
  95     if ((pck_divider == 8'd7) && !clk_state)
  96         to_arm_shiftreg <= adc_d;
  97     else
  98     begin
  99         to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
 100         to_arm_shiftreg[0] <= 1'b0;
 101     end
 102 end
 103
 104 endmodule