fpga/lo_edge_detect.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // There are two modes:
  18 // - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
  19 //   (resp. high) edge/peak is detected, with hysteresis
  20 // - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
  21 //   is detected.
  22 //   That way you can detect two consecutive edges/peaks at the same level (L/H)
  23 //
  24 // Output:
  25 // - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
  26 // - ssp_clk: cross_lo
  27
  28 module lo_edge_detect(
  29     input pck0,
  30     input pck_divclk,
  31     input [7:0] adc_d,
  32     input cross_lo,
  33     input lf_field,
  34     input lf_ed_toggle_mode,
  35     input [7:0] lf_ed_threshold,
  36     input ssp_dout,
  37
  38     output ssp_frame,
  39     output ssp_clk,
  40     output adc_clk,
  41     output pwr_lo,
  42     output pwr_hi,
  43     output pwr_oe1,
  44     output pwr_oe2,
  45     output pwr_oe3,
  46     output pwr_oe4,
  47     output debug
  48 );
  49
  50 wire tag_modulation = ssp_dout & !lf_field;
  51 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
  52
  53 // No logic, straight through.
  54 assign pwr_oe1 = 1'b0; // not used in LF mode
  55 assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
  56 // when modulating, add another 33 Ohms and 10k Ohms in parallel:
  57 assign pwr_oe2 = tag_modulation;
  58 assign pwr_oe4 = tag_modulation;
  59
  60 assign ssp_clk = cross_lo;
  61 assign pwr_lo = reader_modulation;
  62 assign pwr_hi = 1'b0;
  63
  64 // filter the ADC values
  65 wire data_rdy;
  66 wire [7:0] adc_filtered;
  67 assign adc_clk = pck0;
  68
  69 lp20khz_1MSa_iir_filter adc_filter(
  70     .clk   (pck0),
  71     .adc_d (adc_d),
  72     .rdy   (data_rdy),
  73     .out   (adc_filtered)
  74 );
  75
  76 // detect edges
  77 wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
  78 wire [7:0] max, min;
  79 wire edge_state, edge_toggle;
  80
  81 lf_edge_detect lf_ed(
  82     .clk             (pck0),
  83     .adc_d           (adc_filtered),
  84     .lf_ed_threshold (lf_ed_threshold),
  85     .max             (max),
  86     .min             (min),
  87     .high_threshold  (high_threshold),
  88     .highz_threshold (highz_threshold),
  89     .lowz_threshold  (lowz_threshold),
  90     .low_threshold   (low_threshold),
  91     .edge_state      (edge_state),
  92     .edge_toggle     (edge_toggle)
  93 );
  94
  95 assign debug = lf_ed_toggle_mode ? edge_toggle : edge_state;
  96
  97 assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
  98
  99 endmodule
 100