| blob | 90c7348b1824e19f645c5933a2878f628c1567e8 |
1 /*
2 * Copyright (C) 2024 Mikulas Patocka
3 *
4 * This file is part of Ajla.
5 *
6 * Ajla is free software: you can redistribute it and/or modify it under the
7 * terms of the GNU General Public License as published by the Free Software
8 * Foundation, either version 3 of the License, or (at your option) any later
9 * version.
10 *
11 * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * Ajla. If not, see <https://www.gnu.org/licenses/>.
17 */
19 #if !defined(ARCH_SPARC64)
20 #define SPARC_9 cpu_test_feature(CPU_FEATURE_sparc9)
21 #define FRAME_SIZE 0x60
22 #define OP_SIZE_NATIVE (SPARC_9 ? OP_SIZE_8 : OP_SIZE_4)
23 #define OP_SIZE_ADDRESS OP_SIZE_4
24 #else
25 #define SPARC_9 1
26 #define FRAME_SIZE 0xb0
27 #define OP_SIZE_NATIVE OP_SIZE_8
28 #define OP_SIZE_ADDRESS OP_SIZE_8
29 #endif
31 #define JMP_LIMIT JMP_LONG
33 #define UNALIGNED_TRAP 1
35 #define ALU_WRITES_FLAGS(alu, im) 0
36 #define ALU1_WRITES_FLAGS(alu) 0
37 #define ROT_WRITES_FLAGS(alu, size, im) 0
38 #define COND_IS_LOGICAL(cond) 0
40 #define ARCH_PARTIAL_ALU(size) 0
41 #define ARCH_IS_3ADDRESS(alu, f) 1
42 #define ARCH_IS_3ADDRESS_IMM(alu, f) 1
43 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
44 #define ARCH_IS_3ADDRESS_ROT_IMM(alu) 1
45 #define ARCH_IS_2ADDRESS(alu) 1
46 #define ARCH_IS_3ADDRESS_FP 1
47 #define ARCH_HAS_JMP_2REGS(cond) 0
48 #define ARCH_HAS_FLAGS 1
49 #define ARCH_PREFERS_SX(size) 0
50 #define ARCH_HAS_BWX 1
51 #define ARCH_HAS_MUL SPARC_9
52 #define ARCH_HAS_DIV SPARC_9
53 #define ARCH_HAS_ANDN 1
54 #define ARCH_HAS_SHIFTED_ADD(bits) 0
55 #define ARCH_HAS_BTX(btx, size, cnst) 0
56 #define ARCH_SHIFT_SIZE OP_SIZE_4
57 #define ARCH_HAS_FP_GP_MOV 0
58 #define ARCH_NEEDS_BARRIER 0
60 #define i_size(size) OP_SIZE_NATIVE
61 #define i_size_rot(size) maximum(size, OP_SIZE_4)
62 #define i_size_cmp(size) maximum(size, OP_SIZE_4)
64 /*#define SUPPORT_QUAD_PRECISION*/
66 #define R_G0 0x00
67 #define R_G1 0x01
68 #define R_G2 0x02
69 #define R_G3 0x03
70 #define R_G4 0x04
71 #define R_G5 0x05
72 #define R_G6 0x06
73 #define R_G7 0x07
74 #define R_O0 0x08
75 #define R_O1 0x09
76 #define R_O2 0x0a
77 #define R_O3 0x0b
78 #define R_O4 0x0c
79 #define R_O5 0x0d
80 #define R_O6 0x0e
81 #define R_O7 0x0f
82 #define R_L0 0x10
83 #define R_L1 0x11
84 #define R_L2 0x12
85 #define R_L3 0x13
86 #define R_L4 0x14
87 #define R_L5 0x15
88 #define R_L6 0x16
89 #define R_L7 0x17
90 #define R_I0 0x18
91 #define R_I1 0x19
92 #define R_I2 0x1a
93 #define R_I3 0x1b
94 #define R_I4 0x1c
95 #define R_I5 0x1d
96 #define R_I6 0x1e
97 #define R_I7 0x1f
99 #define FSR_0 0x20
100 #define FSR_1 0x21
101 #define FSR_2 0x22
102 #define FSR_3 0x23
103 #define FSR_4 0x24
104 #define FSR_5 0x25
105 #define FSR_6 0x26
106 #define FSR_7 0x27
107 #define FSR_8 0x28
108 #define FSR_9 0x29
109 #define FSR_10 0x2a
110 #define FSR_11 0x2b
111 #define FSR_12 0x2c
112 #define FSR_13 0x2d
113 #define FSR_14 0x2e
114 #define FSR_15 0x2f
115 #define FSR_16 0x30
116 #define FSR_17 0x31
117 #define FSR_18 0x32
118 #define FSR_19 0x33
119 #define FSR_20 0x34
120 #define FSR_21 0x35
121 #define FSR_22 0x36
122 #define FSR_23 0x37
123 #define FSR_24 0x38
124 #define FSR_25 0x39
125 #define FSR_26 0x3a
126 #define FSR_27 0x3b
127 #define FSR_28 0x3c
128 #define FSR_29 0x3d
129 #define FSR_30 0x3e
130 #define FSR_31 0x3f
132 #define FDR_0 0x20
133 #define FDR_2 0x22
134 #define FDR_4 0x24
135 #define FDR_6 0x26
136 #define FDR_8 0x28
137 #define FDR_10 0x2a
138 #define FDR_12 0x2c
139 #define FDR_14 0x2e
140 #define FDR_16 0x30
141 #define FDR_18 0x32
142 #define FDR_20 0x34
143 #define FDR_22 0x36
144 #define FDR_24 0x38
145 #define FDR_26 0x3a
146 #define FDR_28 0x3c
147 #define FDR_30 0x3e
148 #define FDR_32 0x21
149 #define FDR_34 0x23
150 #define FDR_36 0x25
151 #define FDR_38 0x27
152 #define FDR_40 0x29
153 #define FDR_42 0x2b
154 #define FDR_44 0x2d
155 #define FDR_46 0x2f
156 #define FDR_48 0x31
157 #define FDR_50 0x33
158 #define FDR_52 0x35
159 #define FDR_54 0x37
160 #define FDR_56 0x39
161 #define FDR_58 0x3b
162 #define FDR_60 0x3d
163 #define FDR_62 0x3f
165 #define FQR_0 0x20
166 #define FQR_4 0x24
167 #define FQR_8 0x28
168 #define FQR_12 0x2c
169 #define FQR_16 0x30
170 #define FQR_20 0x34
171 #define FQR_24 0x38
172 #define FQR_28 0x3c
173 #define FQR_32 0x21
174 #define FQR_36 0x25
175 #define FQR_40 0x29
176 #define FQR_44 0x2d
177 #define FQR_48 0x31
178 #define FQR_52 0x35
179 #define FQR_56 0x39
180 #define FQR_60 0x3d
182 #define R_ZERO 0x00
183 #define R_SP R_O6
185 #define R_FRAME R_I0
186 #define R_UPCALL R_I1
187 #define R_TIMESTAMP R_I2
189 #define R_SCRATCH_1 R_O1
190 #define R_SCRATCH_2 R_O0
191 #define R_SCRATCH_3 R_O3
192 #define R_SCRATCH_4 R_O2
194 #define R_SCRATCH_NA_1 R_O4
195 #define R_SCRATCH_NA_2 R_O5
196 #ifdef HAVE_BITWISE_FRAME
197 #define R_SCRATCH_NA_3 R_O7
198 #endif
200 #define R_SAVED_1 R_L0
201 #define R_SAVED_2 R_L1
203 #define R_ARG0 R_O0
204 #define R_ARG1 R_O1
205 #define R_ARG2 R_O2
206 #define R_ARG3 R_O3
207 #define R_RET0 R_O0
209 #define R_OFFSET_IMM R_G1
210 #define R_CONST_IMM R_G2
211 #define R_CONST_HELPER R_G3
213 #ifdef SUPPORT_QUAD_PRECISION
214 #define FR_SCRATCH_1 FDR_0
215 #define FR_SCRATCH_2 FDR_4
216 #define SUPPORTED_FP 0x16
217 #else
218 #define FR_SCRATCH_1 FDR_0
219 #define FR_SCRATCH_2 FDR_2
220 #define SUPPORTED_FP 0x6
221 #endif
223 static bool reg_is_fp(unsigned reg)
224 {
225 return reg >= 0x20 && reg < 0x40;
226 }
228 static const uint8_t regs_saved[] = { R_L2, R_L3, R_L4, R_L5, R_L6, R_L7, R_I3, R_I4, R_I5 };
229 static const uint8_t regs_volatile[] = { R_G4, R_G5,
230 #ifndef HAVE_BITWISE_FRAME
231 R_O7,
232 #endif
233 };
234 static const uint8_t fp_saved[] = { 0 };
235 #define n_fp_saved 0U
236 #ifdef SUPPORT_QUAD_PRECISION
237 static const uint8_t fp_volatile[] = { FDR_8, FDR_12, FDR_16, FDR_20, FDR_24, FDR_28 };
238 #else
239 static const uint8_t fp_volatile[] = { FDR_4, FDR_6, FDR_8, FDR_10, FDR_12, FDR_14, FDR_16, FDR_18, FDR_20, FDR_22, FDR_24, FDR_26, FDR_28, FDR_30 };
240 #endif
241 #define reg_is_saved(r) ((r) >= R_L0 && (r) <= R_I7)
243 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
244 {
245 int32_t cl;
246 if (SPARC_9) {
247 if (c >= (uint64_t)-4096) {
248 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
249 gen_one(reg);
250 gen_one(R_ZERO);
251 gen_one(ARG_IMM);
252 gen_eight(c);
253 return true;
254 }
255 if (c >= 0x100000000ULL) {
256 int32_t cu = c >> 32;
257 if (cu < -4096 || cu >= 4096) {
258 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
259 gen_one(R_CONST_HELPER);
260 gen_one(ARG_IMM);
261 gen_eight(cu & 0xFFFFFC00UL);
262 cu &= 0x3FFU;
263 if (cu) {
264 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
265 gen_one(R_CONST_HELPER);
266 gen_one(R_CONST_HELPER);
267 gen_one(ARG_IMM);
268 gen_eight(cu);
269 }
270 } else {
271 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
272 gen_one(R_CONST_HELPER);
273 gen_one(R_ZERO);
274 gen_one(ARG_IMM);
275 gen_eight(cu);
276 }
277 if (!(c & 0xFFFFFFFFULL)) {
278 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
279 gen_one(reg);
280 gen_one(R_CONST_HELPER);
281 gen_one(ARG_IMM);
282 gen_eight(32);
283 return true;
284 }
285 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
286 gen_one(R_CONST_HELPER);
287 gen_one(R_CONST_HELPER);
288 gen_one(ARG_IMM);
289 gen_eight(32);
290 }
291 }
292 cl = c;
293 if (cl < 0 || cl >= 4096) {
294 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
295 gen_one(reg);
296 gen_one(ARG_IMM);
297 gen_eight(cl & 0xFFFFFC00UL);
298 cl &= 0x3FFU;
299 if (cl) {
300 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
301 gen_one(reg);
302 gen_one(reg);
303 gen_one(ARG_IMM);
304 gen_eight(cl);
305 }
306 } else {
307 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
308 gen_one(reg);
309 gen_one(R_ZERO);
310 gen_one(ARG_IMM);
311 gen_eight(cl);
312 }
313 if (SPARC_9) {
314 if (c >= 0x100000000ULL) {
315 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_OR, 0);
316 gen_one(reg);
317 gen_one(reg);
318 gen_one(R_CONST_HELPER);
319 }
320 }
321 return true;
322 }
324 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned purpose, unsigned size)
325 {
326 ctx->base_reg = base;
327 ctx->offset_imm = imm;
328 ctx->offset_reg = false;
329 switch (purpose) {
330 case IMM_PURPOSE_LDR_OFFSET:
331 case IMM_PURPOSE_LDR_SX_OFFSET:
332 case IMM_PURPOSE_STR_OFFSET:
333 case IMM_PURPOSE_LDP_STP_OFFSET:
334 case IMM_PURPOSE_VLDR_VSTR_OFFSET:
335 case IMM_PURPOSE_MVI_CLI_OFFSET:
336 if (likely(imm >= -4096) && likely(imm < 4096))
337 return true;
338 break;
339 default:
340 internal(file_line, "gen_address: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
341 }
343 g(gen_load_constant(ctx, R_OFFSET_IMM, imm));
344 ctx->offset_reg = true;
345 return true;
346 }
348 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
349 {
350 switch (purpose) {
351 case IMM_PURPOSE_STORE_VALUE:
352 if (!imm)
353 return true;
354 break;
355 case IMM_PURPOSE_ADD:
356 case IMM_PURPOSE_SUB:
357 case IMM_PURPOSE_CMP:
358 case IMM_PURPOSE_CMP_LOGICAL:
359 case IMM_PURPOSE_AND:
360 case IMM_PURPOSE_OR:
361 case IMM_PURPOSE_XOR:
362 case IMM_PURPOSE_ANDN:
363 case IMM_PURPOSE_TEST:
364 case IMM_PURPOSE_MUL:
365 if (likely(imm >= -4096) && likely(imm < 4096))
366 return true;
367 break;
368 case IMM_PURPOSE_CMOV:
369 if (likely(imm >= -1024) && likely(imm < 1024))
370 return true;
371 break;
372 case IMM_PURPOSE_MOVR:
373 if (likely(imm >= -512) && likely(imm < 512))
374 return true;
375 break;
376 default:
377 internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
378 }
379 return false;
380 }
382 static bool attr_w gen_imm(struct codegen_context *ctx, int64_t imm, unsigned purpose, unsigned size)
383 {
384 if (is_direct_const(imm, purpose, size)) {
385 ctx->const_imm = imm;
386 ctx->const_reg = false;
387 } else {
388 g(gen_load_constant(ctx, R_CONST_IMM, imm));
389 ctx->const_reg = true;
390 }
391 return true;
392 }
394 static bool attr_w gen_entry(struct codegen_context *ctx)
395 {
396 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_SAVE, 0);
397 gen_one(R_SP);
398 gen_one(R_SP);
399 gen_one(ARG_IMM);
400 gen_eight(-FRAME_SIZE);
402 gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
403 gen_one(R_I3);
405 return true;
406 }
408 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
409 {
410 g(gen_load_constant(ctx, R_I1, ip));
412 gen_insn(INSN_JMP, 0, 0, 0);
413 gen_four(escape_label);
415 return true;
416 }
418 static bool attr_w gen_escape(struct codegen_context *ctx)
419 {
420 gen_insn(INSN_RET, 0, 0, 0);
422 return true;
423 }
425 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
426 {
427 return true;
428 }
430 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
431 {
432 g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_ADDRESS));
433 gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
434 gen_one(R_SCRATCH_NA_1);
435 gen_address_offset();
437 gen_insn(INSN_CALL_INDIRECT, OP_SIZE_NATIVE, 0, 0);
438 gen_one(R_SCRATCH_NA_1);
440 g(gen_upcall_end(ctx, n_args));
442 return true;
443 }
445 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
446 {
447 g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
448 gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
449 gen_one(R_SCRATCH_1);
450 gen_address_offset();
452 gen_insn(INSN_CMP, OP_SIZE_4, 0, 1);
453 gen_one(R_SCRATCH_1);
454 gen_one(R_TIMESTAMP);
456 gen_insn(INSN_JMP_COND, OP_SIZE_4, COND_NE, 0);
457 gen_four(escape_label);
459 return true;
460 }