x86: fix a bug that we misgenerated the the 8-bit imul with a constant
[ajla.git] / arithm-r.inc
blob12fd731f0a3247c5d3dc685d36a18b75295545d6
1 /*
2  * Copyright (C) 2024 Mikulas Patocka
3  *
4  * This file is part of Ajla.
5  *
6  * Ajla is free software: you can redistribute it and/or modify it under the
7  * terms of the GNU General Public License as published by the Free Software
8  * Foundation, either version 3 of the License, or (at your option) any later
9  * version.
10  *
11  * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * Ajla. If not, see <https://www.gnu.org/licenses/>.
17  */
19 #if INT_DEFAULT_BITS == 8
20 #define z                       b
21 #elif INT_DEFAULT_BITS == 16
22 #define z                       w
23 #elif INT_DEFAULT_BITS == 32
24 #define z                       l
25 #elif INT_DEFAULT_BITS == 64
26 #define z                       q
27 #endif
29 #if defined(INLINE_ASM_GCC_X86) && defined(HAVE_X86_ASSEMBLER_F16C) && TYPE_MASK == 0x1
30 #define REAL16_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_f16c))
31 #define REAL16_ALT1_TYPES       0x1
32 gen_f16c_ops(z)
33 #endif
34 #if defined(INLINE_ASM_GCC_X86) && defined(HAVE_X86_ASSEMBLER_SSE) && TYPE_MASK == 0x2
35 #define REAL32_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_sse))
36 #define REAL32_ALT1_TYPES       0x2
37 gen_sse_ops(type, s, z)
38 #endif
39 #if defined(INLINE_ASM_GCC_X86) && defined(HAVE_X86_ASSEMBLER_SSE2) && TYPE_MASK == 0x4
40 #define REAL64_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_sse2))
41 #define REAL64_ALT1_TYPES       0x4
42 gen_sse_ops(type, d, z)
43 #endif
44 #if defined(INLINE_ASM_GCC_X86) && defined(HAVE_X86_ASSEMBLER_AVX) && TYPE_MASK == 0x2
45 #define REAL32_ALT2_FEATURES    (cpu_feature_mask(CPU_FEATURE_avx))
46 #define REAL32_ALT2_TYPES       0x2
47 gen_avx_ops(type, s, z)
48 #endif
49 #if defined(INLINE_ASM_GCC_X86) && defined(HAVE_X86_ASSEMBLER_AVX) && TYPE_MASK == 0x4
50 #define REAL64_ALT2_FEATURES    (cpu_feature_mask(CPU_FEATURE_avx))
51 #define REAL64_ALT2_TYPES       0x4
52 gen_avx_ops(type, d, z)
53 #endif
55 #if defined(INLINE_ASM_GCC_ARM) && defined(HAVE_ARM_ASSEMBLER_HALF_PRECISION) && TYPE_MASK == 0x1
56 #define REAL16_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_half) | cpu_feature_mask(CPU_FEATURE_neon))
57 #define REAL16_ALT1_TYPES       0x1
58 gen_vfp_half_ops()
59 #endif
61 #if defined(INLINE_ASM_GCC_ARM) && defined(HAVE_ARM_ASSEMBLER_VFP) && TYPE_MASK == 0x2
62 #define REAL32_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_vfp))
63 #define REAL32_ALT1_TYPES       0x2
64 gen_vfp_ops(type, "f32", "s")
65 #endif
67 #if defined(INLINE_ASM_GCC_ARM) && defined(HAVE_ARM_ASSEMBLER_VFP) && TYPE_MASK == 0x4
68 #define REAL64_ALT1_FEATURES    (cpu_feature_mask(CPU_FEATURE_vfp))
69 #define REAL64_ALT1_TYPES       0x4
70 gen_vfp_ops(type, "f64", "d")
71 #endif