c1-alpha.inc

   1 /*
   2  * Copyright (C) 2024 Mikulas Patocka
   3  *
   4  * This file is part of Ajla.
   5  *
   6  * Ajla is free software: you can redistribute it and/or modify it under the
   7  * terms of the GNU General Public License as published by the Free Software
   8  * Foundation, either version 3 of the License, or (at your option) any later
   9  * version.
  10  *
  11  * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
  12  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * Ajla. If not, see <https://www.gnu.org/licenses/>.
  17  */
  18
  19 #define OP_SIZE_NATIVE                  OP_SIZE_8
  20 #define OP_SIZE_ADDRESS                 OP_SIZE_NATIVE
  21
  22 #define JMP_LIMIT                       JMP_SHORTEST
  23
  24 #define UNALIGNED_TRAP                  1
  25
  26 #define ALU_WRITES_FLAGS(alu, im)       0
  27 #define ALU1_WRITES_FLAGS(alu)          0
  28 #define ROT_WRITES_FLAGS(alu, size, im) 0
  29 #define COND_IS_LOGICAL(cond)           0
  30
  31 #define ARCH_PARTIAL_ALU(size)          0
  32 #define ARCH_IS_3ADDRESS(alu, f)        1
  33 #define ARCH_IS_3ADDRESS_IMM(alu, f)    1
  34 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
  35 #define ARCH_IS_3ADDRESS_ROT_IMM(alu)   1
  36 #define ARCH_IS_2ADDRESS(alu)           1
  37 #define ARCH_IS_3ADDRESS_FP             1
  38 #define ARCH_HAS_FLAGS                  0
  39 #define ARCH_SUPPORTS_TRAPS             OS_SUPPORTS_TRAPS
  40 #define ARCH_TRAP_BEFORE                0
  41 #define ARCH_PREFERS_SX(size)           ((size) == OP_SIZE_4)
  42 #define ARCH_HAS_BWX                    cpu_test_feature(CPU_FEATURE_bwx)
  43 #define ARCH_HAS_MUL                    1
  44 #define ARCH_HAS_DIV                    0
  45 #define ARCH_HAS_ANDN                   1
  46 #define ARCH_HAS_SHIFTED_ADD(bits)      ((bits) == 0 || (bits) == 2 || (bits) == 3)
  47 #define ARCH_HAS_BTX(btx, size, cnst)   0
  48 #define ARCH_SHIFT_SIZE                 OP_SIZE_8
  49 #define ARCH_HAS_FP_GP_MOV              cpu_test_feature(CPU_FEATURE_fix)
  50 #define ARCH_NEEDS_BARRIER              thread_needs_barriers
  51
  52 #define i_size(size)                    OP_SIZE_NATIVE
  53 #define i_size_rot(size)                OP_SIZE_NATIVE
  54 #define i_size_cmp(size)                OP_SIZE_NATIVE
  55
  56 /*#define TIMESTAMP_IN_REGISTER*/
  57
  58 #define R_V0            0x00
  59 #define R_T0            0x01
  60 #define R_T1            0x02
  61 #define R_T2            0x03
  62 #define R_T3            0x04
  63 #define R_T4            0x05
  64 #define R_T5            0x06
  65 #define R_T6            0x07
  66 #define R_T7            0x08
  67 #define R_S0            0x09
  68 #define R_S1            0x0a
  69 #define R_S2            0x0b
  70 #define R_S3            0x0c
  71 #define R_S4            0x0d
  72 #define R_S5            0x0e
  73 #define R_FP            0x0f
  74 #define R_A0            0x10
  75 #define R_A1            0x11
  76 #define R_A2            0x12
  77 #define R_A3            0x13
  78 #define R_A4            0x14
  79 #define R_A5            0x15
  80 #define R_T8            0x16
  81 #define R_T9            0x17
  82 #define R_T10           0x18
  83 #define R_T11           0x19
  84 #define R_RA            0x1a
  85 #define R_T12           0x1b
  86 #define R_AT            0x1c
  87 #define R_GP            0x1d
  88 #define R_SP            0x1e
  89 #define R_ZERO          0x1f
  90
  91 #define R_F0            0x20
  92 #define R_F1            0x21
  93 #define R_F2            0x22
  94 #define R_F3            0x23
  95 #define R_F4            0x24
  96 #define R_F5            0x25
  97 #define R_F6            0x26
  98 #define R_F7            0x27
  99 #define R_F8            0x28
 100 #define R_F9            0x29
 101 #define R_F10           0x2a
 102 #define R_F11           0x2b
 103 #define R_F12           0x2c
 104 #define R_F13           0x2d
 105 #define R_F14           0x2e
 106 #define R_F15           0x2f
 107 #define R_F16           0x30
 108 #define R_F17           0x31
 109 #define R_F18           0x32
 110 #define R_F19           0x33
 111 #define R_F20           0x34
 112 #define R_F21           0x35
 113 #define R_F22           0x36
 114 #define R_F23           0x37
 115 #define R_F24           0x38
 116 #define R_F25           0x39
 117 #define R_F26           0x3a
 118 #define R_F27           0x3b
 119 #define R_F28           0x3c
 120 #define R_F29           0x3d
 121 #define R_F30           0x3e
 122 #define R_FZERO         0x3f
 123
 124 #define R_FRAME         R_S0
 125 #define R_UPCALL        R_S1
 126 #ifdef TIMESTAMP_IN_REGISTER
 127 #define R_TIMESTAMP     R_S2
 128 #endif
 129
 130 #define R_SCRATCH_1     R_A0
 131 #define R_SCRATCH_2     R_A1
 132 #define R_SCRATCH_3     R_A2
 133 #define R_SCRATCH_4     R_A3
 134 #define R_SCRATCH_NA_1  R_T0
 135 #define R_SCRATCH_NA_2  R_T1
 136 #define R_SCRATCH_NA_3  R_T2
 137
 138 #define R_SAVED_1       R_S3
 139 #define R_SAVED_2       R_S4
 140
 141 #define R_ARG0          R_A0
 142 #define R_ARG1          R_A1
 143 #define R_ARG2          R_A2
 144 #define R_ARG3          R_A3
 145 #define R_ARG4          R_A4
 146 #define R_RET0          R_V0
 147
 148 #define R_OFFSET_IMM    R_T3
 149 #define R_CONST_IMM     R_T4
 150 #define R_CMP_RESULT    R_T5
 151
 152 #define FR_SCRATCH_1    R_F0
 153 #define FR_SCRATCH_2    R_F1
 154 #define FR_SCRATCH_3    R_F10
 155
 156 #define SUPPORTED_FP    0x6
 157
 158 #define FRAME_SIZE      0x50
 159
 160 static bool reg_is_fp(unsigned reg)
 161 {
 162         return reg >= 0x20 && reg < 0x40;
 163 }
 164
 165 static const uint8_t regs_saved[] = {
 166 #ifndef TIMESTAMP_IN_REGISTER
 167         R_S2,
 168 #endif
 169         R_S5, R_FP };
 170 static const uint8_t regs_volatile[] = { R_T6, R_T7, R_A4, R_A5, R_T8, R_T9, R_T10, R_T11, R_RA, R_T12, R_AT, R_GP };
 171 static const uint8_t fp_saved[] = { 0 };
 172 #define n_fp_saved 0U
 173 static const uint8_t fp_volatile[] = { R_F11, R_F12, R_F13, R_F14, R_F15, R_F16, R_F17, R_F18, R_F19, R_F20, R_F21, R_F22, R_F23, R_F24, R_F25, R_F26, R_F27, R_F28, R_F29, R_F30 };
 174 #define reg_is_saved(r) (((r) >= R_S0 && (r) <= R_FP) || ((r) >= R_F2 && (r) <= R_F9))
 175
 176 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
 177 {
 178         unsigned r = R_ZERO;
 179         int16_t c1, c2, c3, c4;
 180         c1 = (int16_t)c;
 181         c &= ~0xffffUL;
 182         if (c1 < 0)
 183                 c += 0x10000UL;
 184         c2 = (int16_t)(c >> 16);
 185         c &= ~0xffffffffUL;
 186         if (c2 < 0)
 187                 c += 0x100000000UL;
 188         c3 = (int16_t)(c >> 32);
 189         c &= ~0xffffffffffffUL;
 190         if (c3 < 0)
 191                 c += 0x1000000000000UL;
 192         c4 = (int16_t)(c >> 48);
 193         if (c4) {
 194                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 195                 gen_one(reg);
 196                 gen_one(R_ZERO);
 197                 gen_one(ARG_IMM);
 198                 gen_eight((uint64_t)c4 << 16);
 199                 r = reg;
 200         }
 201         if (c3) {
 202                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 203                 gen_one(reg);
 204                 gen_one(r);
 205                 gen_one(ARG_IMM);
 206                 gen_eight(c3);
 207                 r = reg;
 208         }
 209         if (r != R_ZERO) {
 210                 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
 211                 gen_one(reg);
 212                 gen_one(reg);
 213                 gen_one(ARG_IMM);
 214                 gen_eight(32);
 215         }
 216         if (c2) {
 217                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 218                 gen_one(reg);
 219                 gen_one(r);
 220                 gen_one(ARG_IMM);
 221                 gen_eight((uint64_t)c2 << 16);
 222                 r = reg;
 223         }
 224         if (c1 || r == R_ZERO) {
 225                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 226                 gen_one(reg);
 227                 gen_one(r);
 228                 gen_one(ARG_IMM);
 229                 gen_eight(c1);
 230         }
 231         return true;
 232 }
 233
 234 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned purpose, unsigned size)
 235 {
 236         ctx->base_reg = base;
 237         ctx->offset_imm = imm;
 238         ctx->offset_reg = false;
 239         switch (purpose) {
 240                 case IMM_PURPOSE_LDR_OFFSET:
 241                 case IMM_PURPOSE_LDR_SX_OFFSET:
 242                 case IMM_PURPOSE_STR_OFFSET:
 243                 case IMM_PURPOSE_VLDR_VSTR_OFFSET:
 244                 case IMM_PURPOSE_MVI_CLI_OFFSET:
 245                         if (likely(imm >= -0x8000) && likely(imm < 0x8000))
 246                                 return true;
 247                         break;
 248                 default:
 249                         internal(file_line, "gen_address: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 250         }
 251         g(gen_load_constant(ctx, R_OFFSET_IMM, imm));
 252         gen_insn(INSN_ALU, OP_SIZE_ADDRESS, ALU_ADD, 0);
 253         gen_one(R_OFFSET_IMM);
 254         gen_one(R_OFFSET_IMM);
 255         gen_one(base);
 256         ctx->base_reg = R_OFFSET_IMM;
 257         ctx->offset_imm = 0;
 258         return true;
 259 }
 260
 261 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
 262 {
 263         int64_t imm_copy = imm;
 264         switch (purpose) {
 265                 case IMM_PURPOSE_STORE_VALUE:
 266                         if (!imm)
 267                                 return true;
 268                         break;
 269                 case IMM_PURPOSE_SUB:
 270                         imm_copy = -(uint64_t)imm_copy;
 271                         /*-fallthrough*/
 272                 case IMM_PURPOSE_ADD:
 273                         if (likely(imm_copy >= -0x8000) && likely(imm_copy < 0x8000))
 274                                 return true;
 275                         if (imm_copy & 0xffff)
 276                                 break;
 277                         if (likely(imm_copy >= -0x80000000L) && likely(imm_copy < 0x80000000L))
 278                                 return true;
 279                         break;
 280                 case IMM_PURPOSE_CMP:
 281                 case IMM_PURPOSE_CMP_LOGICAL:
 282                 case IMM_PURPOSE_AND:
 283                 case IMM_PURPOSE_OR:
 284                 case IMM_PURPOSE_XOR:
 285                 case IMM_PURPOSE_ANDN:
 286                 case IMM_PURPOSE_TEST:
 287                 case IMM_PURPOSE_MUL:
 288                 case IMM_PURPOSE_MOVR:
 289                         if (imm >= 0 && imm < 256)
 290                                 return true;
 291                         break;
 292                 default:
 293                         internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 294         }
 295         return false;
 296 }
 297
 298 static bool attr_w gen_imm(struct codegen_context *ctx, int64_t imm, unsigned purpose, unsigned size)
 299 {
 300         if (is_direct_const(imm, purpose, size)) {
 301                 ctx->const_imm = imm;
 302                 ctx->const_reg = false;
 303         } else {
 304                 g(gen_load_constant(ctx, R_CONST_IMM, imm));
 305                 ctx->const_reg = true;
 306         }
 307         return true;
 308 }
 309
 310 static bool attr_w gen_entry(struct codegen_context *ctx)
 311 {
 312         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_SUB, OP_SIZE_NATIVE));
 313         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_SUB, 0);
 314         gen_one(R_SP);
 315         gen_one(R_SP);
 316         gen_imm_offset();
 317
 318         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 319         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 320         gen_address_offset();
 321         gen_one(R_RA);
 322
 323 #ifndef TIMESTAMP_IN_REGISTER
 324         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_STR_OFFSET, OP_SIZE_4));
 325         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 326         gen_address_offset();
 327         gen_one(R_ARG3);
 328 #endif
 329
 330         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 331         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 332         gen_address_offset();
 333         gen_one(R_S0);
 334
 335         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 336         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 337         gen_address_offset();
 338         gen_one(R_S1);
 339
 340         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 341         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 342         gen_address_offset();
 343         gen_one(R_S2);
 344
 345         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 346         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 347         gen_address_offset();
 348         gen_one(R_S3);
 349
 350         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 351         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 352         gen_address_offset();
 353         gen_one(R_S4);
 354
 355         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 356         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 357         gen_address_offset();
 358         gen_one(R_S5);
 359
 360         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 361         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 362         gen_address_offset();
 363         gen_one(R_FP);
 364
 365         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 366         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 367         gen_address_offset();
 368         gen_one(R_ARG0);
 369
 370         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 371         gen_one(R_FRAME);
 372         gen_one(R_ARG1);
 373
 374         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 375         gen_one(R_UPCALL);
 376         gen_one(R_ARG2);
 377
 378 #ifdef TIMESTAMP_IN_REGISTER
 379         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 380         gen_one(R_TIMESTAMP);
 381         gen_one(R_ARG3);
 382 #endif
 383
 384         gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
 385         gen_one(R_ARG4);
 386
 387         return true;
 388 }
 389
 390 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
 391 {
 392         g(gen_load_constant(ctx, R_SCRATCH_1, (int32_t)ip));
 393
 394         gen_insn(INSN_JMP, 0, 0, 0);
 395         gen_four(escape_label);
 396
 397         return true;
 398 }
 399
 400 static bool attr_w gen_escape(struct codegen_context *ctx)
 401 {
 402         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 403         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 404         gen_one(R_RET0);
 405         gen_address_offset();
 406
 407         g(gen_address(ctx, R_RET0, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 408         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 409         gen_address_offset();
 410         gen_one(R_FRAME);
 411
 412         g(gen_address(ctx, R_RET0, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 413         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 414         gen_address_offset();
 415         gen_one(R_SCRATCH_1);
 416
 417         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 418         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 419         gen_one(R_RA);
 420         gen_address_offset();
 421
 422         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 423         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 424         gen_one(R_S0);
 425         gen_address_offset();
 426
 427         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 428         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 429         gen_one(R_S1);
 430         gen_address_offset();
 431
 432         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 433         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 434         gen_one(R_S2);
 435         gen_address_offset();
 436
 437         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 438         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 439         gen_one(R_S3);
 440         gen_address_offset();
 441
 442         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 443         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 444         gen_one(R_S4);
 445         gen_address_offset();
 446
 447         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 448         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 449         gen_one(R_S5);
 450         gen_address_offset();
 451
 452         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 453         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 454         gen_one(R_FP);
 455         gen_address_offset();
 456
 457         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
 458         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 459         gen_one(R_SP);
 460         gen_one(R_SP);
 461         gen_imm_offset();
 462
 463         gen_insn(INSN_RET, 0, 0, 0);
 464
 465         return true;
 466 }
 467
 468 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
 469 {
 470         return true;
 471 }
 472
 473 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
 474 {
 475         g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 476         gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
 477         gen_one(R_T12);
 478         gen_address_offset();
 479
 480         gen_insn(INSN_CALL_INDIRECT, OP_SIZE_ADDRESS, 0, 0);
 481         gen_one(R_T12);
 482
 483         g(gen_upcall_end(ctx, n_args));
 484
 485         return true;
 486 }
 487
 488 static bool attr_w gen_cmp_test_jmp(struct codegen_context *ctx, unsigned insn, unsigned op_size, unsigned reg1, unsigned reg2, unsigned cond, uint32_t label);
 489
 490 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
 491 {
 492         g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_SX_OFFSET, OP_SIZE_4));
 493         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 494         gen_one(R_SCRATCH_1);
 495         gen_address_offset();
 496
 497 #ifdef TIMESTAMP_IN_REGISTER
 498         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_TIMESTAMP, COND_NE, escape_label));
 499 #else
 500         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 501         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 502         gen_one(R_SCRATCH_2);
 503         gen_address_offset();
 504
 505         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_SCRATCH_2, COND_NE, escape_label));
 506 #endif
 507         return true;
 508 }