c1-alpha.inc

   1 /*
   2  * Copyright (C) 2024 Mikulas Patocka
   3  *
   4  * This file is part of Ajla.
   5  *
   6  * Ajla is free software: you can redistribute it and/or modify it under the
   7  * terms of the GNU General Public License as published by the Free Software
   8  * Foundation, either version 3 of the License, or (at your option) any later
   9  * version.
  10  *
  11  * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
  12  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * Ajla. If not, see <https://www.gnu.org/licenses/>.
  17  */
  18
  19 #define OP_SIZE_NATIVE                  OP_SIZE_8
  20 #define OP_SIZE_ADDRESS                 OP_SIZE_NATIVE
  21
  22 #define JMP_LIMIT                       JMP_SHORTEST
  23
  24 #define UNALIGNED_TRAP                  1
  25
  26 #define ALU_WRITES_FLAGS(alu, im)       0
  27 #define ALU1_WRITES_FLAGS(alu)          0
  28 #define ROT_WRITES_FLAGS(alu, size, im) 0
  29 #define COND_IS_LOGICAL(cond)           0
  30
  31 #define ARCH_PARTIAL_ALU(size)          0
  32 #define ARCH_IS_3ADDRESS(alu, f)        1
  33 #define ARCH_IS_3ADDRESS_IMM(alu, f)    1
  34 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
  35 #define ARCH_IS_3ADDRESS_ROT_IMM(alu)   1
  36 #define ARCH_IS_2ADDRESS(alu)           1
  37 #define ARCH_IS_3ADDRESS_FP             1
  38 #define ARCH_HAS_JMP_2REGS(cond)        0
  39 #define ARCH_HAS_FLAGS                  0
  40 #define ARCH_SUPPORTS_TRAPS             OS_SUPPORTS_TRAPS
  41 #define ARCH_TRAP_BEFORE                0
  42 #define ARCH_PREFERS_SX(size)           ((size) == OP_SIZE_4)
  43 #define ARCH_HAS_BWX                    cpu_test_feature(CPU_FEATURE_bwx)
  44 #define ARCH_HAS_MUL                    1
  45 #define ARCH_HAS_DIV                    0
  46 #define ARCH_HAS_ANDN                   1
  47 #define ARCH_HAS_SHIFTED_ADD(bits)      ((bits) == 0 || (bits) == 2 || (bits) == 3)
  48 #define ARCH_HAS_BTX(btx, size, cnst)   0
  49 #define ARCH_SHIFT_SIZE                 OP_SIZE_8
  50 #define ARCH_HAS_FP_GP_MOV              cpu_test_feature(CPU_FEATURE_fix)
  51 #define ARCH_NEEDS_BARRIER              thread_needs_barriers
  52
  53 #define i_size(size)                    OP_SIZE_NATIVE
  54 #define i_size_rot(size)                OP_SIZE_NATIVE
  55 #define i_size_cmp(size)                OP_SIZE_NATIVE
  56
  57 /*#define TIMESTAMP_IN_REGISTER*/
  58
  59 #define R_V0            0x00
  60 #define R_T0            0x01
  61 #define R_T1            0x02
  62 #define R_T2            0x03
  63 #define R_T3            0x04
  64 #define R_T4            0x05
  65 #define R_T5            0x06
  66 #define R_T6            0x07
  67 #define R_T7            0x08
  68 #define R_S0            0x09
  69 #define R_S1            0x0a
  70 #define R_S2            0x0b
  71 #define R_S3            0x0c
  72 #define R_S4            0x0d
  73 #define R_S5            0x0e
  74 #define R_FP            0x0f
  75 #define R_A0            0x10
  76 #define R_A1            0x11
  77 #define R_A2            0x12
  78 #define R_A3            0x13
  79 #define R_A4            0x14
  80 #define R_A5            0x15
  81 #define R_T8            0x16
  82 #define R_T9            0x17
  83 #define R_T10           0x18
  84 #define R_T11           0x19
  85 #define R_RA            0x1a
  86 #define R_T12           0x1b
  87 #define R_AT            0x1c
  88 #define R_GP            0x1d
  89 #define R_SP            0x1e
  90 #define R_ZERO          0x1f
  91
  92 #define R_F0            0x20
  93 #define R_F1            0x21
  94 #define R_F2            0x22
  95 #define R_F3            0x23
  96 #define R_F4            0x24
  97 #define R_F5            0x25
  98 #define R_F6            0x26
  99 #define R_F7            0x27
 100 #define R_F8            0x28
 101 #define R_F9            0x29
 102 #define R_F10           0x2a
 103 #define R_F11           0x2b
 104 #define R_F12           0x2c
 105 #define R_F13           0x2d
 106 #define R_F14           0x2e
 107 #define R_F15           0x2f
 108 #define R_F16           0x30
 109 #define R_F17           0x31
 110 #define R_F18           0x32
 111 #define R_F19           0x33
 112 #define R_F20           0x34
 113 #define R_F21           0x35
 114 #define R_F22           0x36
 115 #define R_F23           0x37
 116 #define R_F24           0x38
 117 #define R_F25           0x39
 118 #define R_F26           0x3a
 119 #define R_F27           0x3b
 120 #define R_F28           0x3c
 121 #define R_F29           0x3d
 122 #define R_F30           0x3e
 123 #define R_FZERO         0x3f
 124
 125 #define R_FRAME         R_S0
 126 #define R_UPCALL        R_S1
 127 #ifdef TIMESTAMP_IN_REGISTER
 128 #define R_TIMESTAMP     R_S2
 129 #endif
 130
 131 #define R_SCRATCH_1     R_A0
 132 #define R_SCRATCH_2     R_A1
 133 #define R_SCRATCH_3     R_A2
 134 #define R_SCRATCH_4     R_A3
 135 #define R_SCRATCH_NA_1  R_T0
 136 #define R_SCRATCH_NA_2  R_T1
 137 #define R_SCRATCH_NA_3  R_T2
 138
 139 #define R_SAVED_1       R_S3
 140 #define R_SAVED_2       R_S4
 141
 142 #define R_ARG0          R_A0
 143 #define R_ARG1          R_A1
 144 #define R_ARG2          R_A2
 145 #define R_ARG3          R_A3
 146 #define R_ARG4          R_A4
 147 #define R_RET0          R_V0
 148
 149 #define R_OFFSET_IMM    R_T3
 150 #define R_CONST_IMM     R_T4
 151 #define R_CMP_RESULT    R_T5
 152
 153 #define FR_SCRATCH_1    R_F0
 154 #define FR_SCRATCH_2    R_F1
 155 #define FR_SCRATCH_3    R_F10
 156
 157 #define SUPPORTED_FP    0x6
 158
 159 #define FRAME_SIZE      0x50
 160
 161 static bool reg_is_fp(unsigned reg)
 162 {
 163         return reg >= 0x20 && reg < 0x40;
 164 }
 165
 166 static const uint8_t regs_saved[] = {
 167 #ifndef TIMESTAMP_IN_REGISTER
 168         R_S2,
 169 #endif
 170         R_S5, R_FP };
 171 static const uint8_t regs_volatile[] = { R_T6, R_T7, R_A4, R_A5, R_T8, R_T9, R_T10, R_T11, R_RA, R_T12, R_AT, R_GP };
 172 static const uint8_t fp_saved[] = { 0 };
 173 #define n_fp_saved 0U
 174 static const uint8_t fp_volatile[] = { R_F11, R_F12, R_F13, R_F14, R_F15, R_F16, R_F17, R_F18, R_F19, R_F20, R_F21, R_F22, R_F23, R_F24, R_F25, R_F26, R_F27, R_F28, R_F29, R_F30 };
 175 #define reg_is_saved(r) (((r) >= R_S0 && (r) <= R_FP) || ((r) >= R_F2 && (r) <= R_F9))
 176
 177 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
 178 {
 179         unsigned r = R_ZERO;
 180         int16_t c1, c2, c3, c4;
 181         c1 = (int16_t)c;
 182         c &= ~0xffffUL;
 183         if (c1 < 0)
 184                 c += 0x10000UL;
 185         c2 = (int16_t)(c >> 16);
 186         c &= ~0xffffffffUL;
 187         if (c2 < 0)
 188                 c += 0x100000000UL;
 189         c3 = (int16_t)(c >> 32);
 190         c &= ~0xffffffffffffUL;
 191         if (c3 < 0)
 192                 c += 0x1000000000000UL;
 193         c4 = (int16_t)(c >> 48);
 194         if (c4) {
 195                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 196                 gen_one(reg);
 197                 gen_one(R_ZERO);
 198                 gen_one(ARG_IMM);
 199                 gen_eight((uint64_t)c4 << 16);
 200                 r = reg;
 201         }
 202         if (c3) {
 203                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 204                 gen_one(reg);
 205                 gen_one(r);
 206                 gen_one(ARG_IMM);
 207                 gen_eight(c3);
 208                 r = reg;
 209         }
 210         if (r != R_ZERO) {
 211                 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
 212                 gen_one(reg);
 213                 gen_one(reg);
 214                 gen_one(ARG_IMM);
 215                 gen_eight(32);
 216         }
 217         if (c2) {
 218                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 219                 gen_one(reg);
 220                 gen_one(r);
 221                 gen_one(ARG_IMM);
 222                 gen_eight((uint64_t)c2 << 16);
 223                 r = reg;
 224         }
 225         if (c1 || r == R_ZERO) {
 226                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 227                 gen_one(reg);
 228                 gen_one(r);
 229                 gen_one(ARG_IMM);
 230                 gen_eight(c1);
 231         }
 232         return true;
 233 }
 234
 235 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned purpose, unsigned size)
 236 {
 237         ctx->base_reg = base;
 238         ctx->offset_imm = imm;
 239         ctx->offset_reg = false;
 240         switch (purpose) {
 241                 case IMM_PURPOSE_LDR_OFFSET:
 242                 case IMM_PURPOSE_LDR_SX_OFFSET:
 243                 case IMM_PURPOSE_STR_OFFSET:
 244                 case IMM_PURPOSE_VLDR_VSTR_OFFSET:
 245                 case IMM_PURPOSE_MVI_CLI_OFFSET:
 246                         if (likely(imm >= -0x8000) && likely(imm < 0x8000))
 247                                 return true;
 248                         break;
 249                 default:
 250                         internal(file_line, "gen_address: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 251         }
 252         g(gen_load_constant(ctx, R_OFFSET_IMM, imm));
 253         gen_insn(INSN_ALU, OP_SIZE_ADDRESS, ALU_ADD, 0);
 254         gen_one(R_OFFSET_IMM);
 255         gen_one(R_OFFSET_IMM);
 256         gen_one(base);
 257         ctx->base_reg = R_OFFSET_IMM;
 258         ctx->offset_imm = 0;
 259         return true;
 260 }
 261
 262 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
 263 {
 264         int64_t imm_copy = imm;
 265         switch (purpose) {
 266                 case IMM_PURPOSE_STORE_VALUE:
 267                         if (!imm)
 268                                 return true;
 269                         break;
 270                 case IMM_PURPOSE_SUB:
 271                         imm_copy = -(uint64_t)imm_copy;
 272                         /*-fallthrough*/
 273                 case IMM_PURPOSE_ADD:
 274                         if (likely(imm_copy >= -0x8000) && likely(imm_copy < 0x8000))
 275                                 return true;
 276                         if (imm_copy & 0xffff)
 277                                 break;
 278                         if (likely(imm_copy >= -0x80000000L) && likely(imm_copy < 0x80000000L))
 279                                 return true;
 280                         break;
 281                 case IMM_PURPOSE_CMP:
 282                 case IMM_PURPOSE_CMP_LOGICAL:
 283                 case IMM_PURPOSE_AND:
 284                 case IMM_PURPOSE_OR:
 285                 case IMM_PURPOSE_XOR:
 286                 case IMM_PURPOSE_ANDN:
 287                 case IMM_PURPOSE_TEST:
 288                 case IMM_PURPOSE_MUL:
 289                 case IMM_PURPOSE_MOVR:
 290                         if (imm >= 0 && imm < 256)
 291                                 return true;
 292                         break;
 293                 default:
 294                         internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 295         }
 296         return false;
 297 }
 298
 299 static bool attr_w gen_imm(struct codegen_context *ctx, int64_t imm, unsigned purpose, unsigned size)
 300 {
 301         if (is_direct_const(imm, purpose, size)) {
 302                 ctx->const_imm = imm;
 303                 ctx->const_reg = false;
 304         } else {
 305                 g(gen_load_constant(ctx, R_CONST_IMM, imm));
 306                 ctx->const_reg = true;
 307         }
 308         return true;
 309 }
 310
 311 static bool attr_w gen_entry(struct codegen_context *ctx)
 312 {
 313         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_SUB, OP_SIZE_NATIVE));
 314         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_SUB, 0);
 315         gen_one(R_SP);
 316         gen_one(R_SP);
 317         gen_imm_offset();
 318
 319         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 320         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 321         gen_address_offset();
 322         gen_one(R_RA);
 323
 324 #ifndef TIMESTAMP_IN_REGISTER
 325         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_STR_OFFSET, OP_SIZE_4));
 326         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 327         gen_address_offset();
 328         gen_one(R_ARG3);
 329 #endif
 330
 331         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 332         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 333         gen_address_offset();
 334         gen_one(R_S0);
 335
 336         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 337         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 338         gen_address_offset();
 339         gen_one(R_S1);
 340
 341         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 342         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 343         gen_address_offset();
 344         gen_one(R_S2);
 345
 346         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 347         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 348         gen_address_offset();
 349         gen_one(R_S3);
 350
 351         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 352         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 353         gen_address_offset();
 354         gen_one(R_S4);
 355
 356         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 357         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 358         gen_address_offset();
 359         gen_one(R_S5);
 360
 361         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 362         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 363         gen_address_offset();
 364         gen_one(R_FP);
 365
 366         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 367         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 368         gen_address_offset();
 369         gen_one(R_ARG0);
 370
 371         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 372         gen_one(R_FRAME);
 373         gen_one(R_ARG1);
 374
 375         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 376         gen_one(R_UPCALL);
 377         gen_one(R_ARG2);
 378
 379 #ifdef TIMESTAMP_IN_REGISTER
 380         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 381         gen_one(R_TIMESTAMP);
 382         gen_one(R_ARG3);
 383 #endif
 384
 385         gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
 386         gen_one(R_ARG4);
 387
 388         return true;
 389 }
 390
 391 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
 392 {
 393         g(gen_load_constant(ctx, R_SCRATCH_1, (int32_t)ip));
 394
 395         gen_insn(INSN_JMP, 0, 0, 0);
 396         gen_four(escape_label);
 397
 398         return true;
 399 }
 400
 401 static bool attr_w gen_escape(struct codegen_context *ctx)
 402 {
 403         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 404         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 405         gen_one(R_RET0);
 406         gen_address_offset();
 407
 408         g(gen_address(ctx, R_RET0, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 409         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 410         gen_address_offset();
 411         gen_one(R_FRAME);
 412
 413         g(gen_address(ctx, R_RET0, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 414         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 415         gen_address_offset();
 416         gen_one(R_SCRATCH_1);
 417
 418         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 419         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 420         gen_one(R_RA);
 421         gen_address_offset();
 422
 423         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 424         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 425         gen_one(R_S0);
 426         gen_address_offset();
 427
 428         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 429         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 430         gen_one(R_S1);
 431         gen_address_offset();
 432
 433         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 434         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 435         gen_one(R_S2);
 436         gen_address_offset();
 437
 438         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 439         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 440         gen_one(R_S3);
 441         gen_address_offset();
 442
 443         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 444         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 445         gen_one(R_S4);
 446         gen_address_offset();
 447
 448         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 449         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 450         gen_one(R_S5);
 451         gen_address_offset();
 452
 453         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 454         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 455         gen_one(R_FP);
 456         gen_address_offset();
 457
 458         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
 459         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 460         gen_one(R_SP);
 461         gen_one(R_SP);
 462         gen_imm_offset();
 463
 464         gen_insn(INSN_RET, 0, 0, 0);
 465
 466         return true;
 467 }
 468
 469 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
 470 {
 471         return true;
 472 }
 473
 474 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
 475 {
 476         g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 477         gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
 478         gen_one(R_T12);
 479         gen_address_offset();
 480
 481         gen_insn(INSN_CALL_INDIRECT, OP_SIZE_ADDRESS, 0, 0);
 482         gen_one(R_T12);
 483
 484         g(gen_upcall_end(ctx, n_args));
 485
 486         return true;
 487 }
 488
 489 static bool attr_w gen_cmp_test_jmp(struct codegen_context *ctx, unsigned insn, unsigned op_size, unsigned reg1, unsigned reg2, unsigned cond, uint32_t label);
 490
 491 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
 492 {
 493         g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_SX_OFFSET, OP_SIZE_4));
 494         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 495         gen_one(R_SCRATCH_1);
 496         gen_address_offset();
 497
 498 #ifdef TIMESTAMP_IN_REGISTER
 499         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_TIMESTAMP, COND_NE, escape_label));
 500 #else
 501         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 502         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 503         gen_one(R_SCRATCH_2);
 504         gen_address_offset();
 505
 506         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_SCRATCH_2, COND_NE, escape_label));
 507 #endif
 508         return true;
 509 }