| blob | 77c4d0b80a5cbf443a1c9923294d20f3e356f78a |
1 /*
2 * Copyright (C) 2024 Mikulas Patocka
3 *
4 * This file is part of Ajla.
5 *
6 * Ajla is free software: you can redistribute it and/or modify it under the
7 * terms of the GNU General Public License as published by the Free Software
8 * Foundation, either version 3 of the License, or (at your option) any later
9 * version.
10 *
11 * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * Ajla. If not, see <https://www.gnu.org/licenses/>.
17 */
19 #define OP_SIZE_NATIVE OP_SIZE_8
20 #define OP_SIZE_ADDRESS OP_SIZE_NATIVE
22 #define JMP_LIMIT (cpu_test_feature(CPU_FEATURE_brl) ? JMP_SHORT : JMP_SHORTEST)
24 #define UNALIGNED_TRAP 1
26 #define ALU_WRITES_FLAGS(size, alu, is_mem, is_imm, imm) 0
27 #define ALU1_WRITES_FLAGS(alu) 0
28 #define ROT_WRITES_FLAGS(alu, size, im) 0
29 #define COND_IS_LOGICAL(cond) 0
31 #define ARCH_PARTIAL_ALU(size) 0
32 #define ARCH_IS_3ADDRESS(alu, f) 1
33 #define ARCH_IS_3ADDRESS_IMM(alu, f) 1
34 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
35 #define ARCH_IS_3ADDRESS_ROT_IMM(alu) 1
36 #define ARCH_IS_2ADDRESS(alu) 1
37 #define ARCH_IS_3ADDRESS_FP 1
38 #define ARCH_HAS_JMP_2REGS(cond) 0
39 #define ARCH_HAS_FLAGS 0
40 #define ARCH_PREFERS_SX(size) 0
41 #define ARCH_HAS_BWX 1
42 #define ARCH_HAS_MUL 0
43 #define ARCH_HAS_DIV 0
44 #define ARCH_HAS_ANDN 1
45 #define ARCH_HAS_SHIFTED_ADD(bits) ((bits) <= 4)
46 #define ARCH_HAS_BTX(btx, size, cnst) (((btx) == BTX_BTS || (btx) == BTX_BTR) && (cnst))
47 #define ARCH_SHIFT_SIZE 32
48 #define ARCH_BOOL_SIZE OP_SIZE_NATIVE
49 #define ARCH_HAS_FP_GP_MOV 1
50 #define ARCH_NEEDS_BARRIER 0
52 #define i_size(size) OP_SIZE_NATIVE
53 #define i_size_rot(size) OP_SIZE_NATIVE
54 #define i_size_cmp(size) maximum(size, OP_SIZE_4)
56 #define N_SAVED_REGS 0x40
58 #define R_ZERO 0x00
59 #define R_GP 0x01
60 #define R_2 0x02
61 #define R_3 0x03
62 #define R_4 0x04
63 #define R_5 0x05
64 #define R_6 0x06
65 #define R_7 0x07
66 #define R_8 0x08
67 #define R_9 0x09
68 #define R_10 0x0a
69 #define R_11 0x0b
70 #define R_SP 0x0c
71 #define R_TP 0x0d
72 #define R_14 0x0e
73 #define R_15 0x0f
74 #define R_16 0x10
75 #define R_17 0x11
76 #define R_18 0x12
77 #define R_19 0x13
78 #define R_20 0x14
79 #define R_21 0x15
80 #define R_22 0x16
81 #define R_23 0x17
82 #define R_24 0x18
83 #define R_25 0x19
84 #define R_26 0x1a
85 #define R_27 0x1b
86 #define R_28 0x1c
87 #define R_29 0x1d
88 #define R_30 0x1e
89 #define R_31 0x1f
90 #define R_32 0x20
91 #define R_33 0x21
92 #define R_34 0x22
93 #define R_35 0x23
94 #define R_36 0x24
95 #define R_37 0x25
96 #define R_38 0x26
97 #define R_39 0x27
98 #define R_40 0x28
99 #define R_41 0x29
100 #define R_42 0x2a
101 #define R_43 0x2b
102 #define R_44 0x2c
103 #define R_45 0x2d
104 #define R_46 0x2e
105 #define R_47 0x2f
106 #define R_48 0x30
107 #define R_49 0x31
108 #define R_50 0x32
109 #define R_51 0x33
110 #define R_52 0x34
111 #define R_53 0x35
112 #define R_54 0x36
113 #define R_55 0x37
114 #define R_56 0x38
115 #define R_57 0x39
116 #define R_58 0x3a
117 #define R_59 0x3b
118 #define R_60 0x3c
119 #define R_61 0x3d
120 #define R_62 0x3e
121 #define R_63 0x3f
122 #define R_64 0x40
123 #define R_65 0x41
124 #define R_66 0x42
125 #define R_67 0x43
126 #define R_68 0x44
127 #define R_69 0x45
128 #define R_70 0x46
129 #define R_71 0x47
130 #define R_72 0x48
131 #define R_73 0x49
132 #define R_74 0x4a
133 #define R_75 0x4b
134 #define R_76 0x4c
135 #define R_77 0x4d
136 #define R_78 0x4e
137 #define R_79 0x4f
138 #define R_80 0x50
139 #define R_81 0x51
140 #define R_82 0x52
141 #define R_83 0x53
142 #define R_84 0x54
143 #define R_85 0x55
144 #define R_86 0x56
145 #define R_87 0x57
146 #define R_88 0x58
147 #define R_89 0x59
148 #define R_90 0x5a
149 #define R_91 0x5b
150 #define R_92 0x5c
151 #define R_93 0x5d
152 #define R_94 0x5e
153 #define R_95 0x5f
155 #define FR_ZERO 0x60
156 #define FR_ONE 0x61
157 #define FR_2 0x62
158 #define FR_3 0x63
159 #define FR_4 0x64
160 #define FR_5 0x65
161 #define FR_6 0x66
162 #define FR_7 0x67
163 #define FR_8 0x68
164 #define FR_9 0x69
165 #define FR_10 0x6a
166 #define FR_11 0x6b
167 #define FR_12 0x6c
168 #define FR_13 0x6d
169 #define FR_14 0x6e
170 #define FR_15 0x6f
171 #define FR_16 0x70
172 #define FR_17 0x71
173 #define FR_18 0x72
174 #define FR_19 0x73
175 #define FR_20 0x74
176 #define FR_21 0x75
177 #define FR_22 0x76
178 #define FR_23 0x77
179 #define FR_24 0x78
180 #define FR_25 0x79
181 #define FR_26 0x7a
182 #define FR_27 0x7b
183 #define FR_28 0x7c
184 #define FR_29 0x7d
185 #define FR_30 0x7e
186 #define FR_31 0x7f
187 #define FR_32 0x80
188 #define FR_33 0x81
189 #define FR_34 0x82
190 #define FR_35 0x83
191 #define FR_36 0x84
192 #define FR_37 0x85
193 #define FR_38 0x86
194 #define FR_39 0x87
195 #define FR_40 0x88
196 #define FR_41 0x89
197 #define FR_42 0x8a
198 #define FR_43 0x8b
199 #define FR_44 0x8c
200 #define FR_45 0x8d
201 #define FR_46 0x8e
202 #define FR_47 0x8f
203 #define FR_48 0x90
204 #define FR_49 0x91
205 #define FR_50 0x92
206 #define FR_51 0x93
207 #define FR_52 0x94
208 #define FR_53 0x95
209 #define FR_54 0x96
210 #define FR_55 0x97
211 #define FR_56 0x98
212 #define FR_57 0x99
213 #define FR_58 0x9a
214 #define FR_59 0x9b
215 #define FR_60 0x9c
216 #define FR_61 0x9d
217 #define FR_62 0x9e
218 #define FR_63 0x9f
220 #define P_0 0xa0
221 #define P_1 0xa1
222 #define P_2 0xa2
223 #define P_3 0xa3
224 #define P_4 0xa4
225 #define P_5 0xa5
226 #define P_6 0xa6
227 #define P_7 0xa7
229 #define B_0 0xb0
230 #define B_1 0xb1
231 #define B_2 0xb2
232 #define B_3 0xb3
233 #define B_4 0xb4
234 #define B_5 0xb5
235 #define B_6 0xb6
236 #define B_7 0xb7
238 #define R_FRAME R_32
239 #define R_UPCALL R_33
240 #define R_TIMESTAMP R_34
241 #define R_ENTRY R_35
242 #define R_SAVED_1 R_35
243 #define R_SAVED_2 R_36
244 #define R_SAVED_B0 R_37
245 #define R_SAVED_AR_PFS R_38
246 #define R_ARG0 (R_32 + N_SAVED_REGS - 4)
247 #define R_ARG1 (R_32 + N_SAVED_REGS - 3)
248 #define R_ARG2 (R_32 + N_SAVED_REGS - 2)
249 #define R_ARG3 (R_32 + N_SAVED_REGS - 1)
251 #define R_RET0 R_8
252 #define R_RET1 R_9
253 #define R_CG_SCRATCH R_10
254 #define R_SCRATCH_NA_1 R_14
255 #define R_SCRATCH_NA_2 R_15
256 #define R_SCRATCH_NA_3 R_16
257 #define R_SCRATCH_1 R_17
258 #define R_SCRATCH_2 R_18
259 #define R_SCRATCH_3 R_19
260 #define R_SCRATCH_4 R_20
262 #define R_OFFSET_IMM R_2
263 #define R_CONST_IMM R_3
264 #define R_CMP_RESULT P_6
266 #define R_SCRATCH_B B_6
268 #define FR_SCRATCH_1 FR_6
269 #define FR_SCRATCH_2 FR_7
271 #define SUPPORTED_FP 0xe
273 static inline bool reg_is_gr(unsigned reg)
274 {
275 return reg < 0x60;
276 }
278 static inline bool reg_is_fp(unsigned reg)
279 {
280 return reg >= 0x60 && reg < 0xa0;
281 }
283 static inline bool reg_is_p(unsigned reg)
284 {
285 return reg >= 0xa0 && reg < 0xa8;
286 }
288 static inline bool reg_is_b(unsigned reg)
289 {
290 return reg >= 0xb0 && reg < 0xb8;
291 }
293 static inline uint64_t bits_gr(unsigned reg)
294 {
295 ajla_assert_lo(reg_is_gr(reg), (file_line, "bits_gr: register %x", reg));
296 return reg;
297 }
299 static inline uint64_t bits_fp(unsigned reg)
300 {
301 ajla_assert_lo(reg_is_fp(reg), (file_line, "bits_fp: register %x", reg));
302 return reg - 0x60;
303 }
305 static inline uint64_t bits_p(unsigned reg)
306 {
307 ajla_assert_lo(reg_is_p(reg), (file_line, "bits_p: register %x", reg));
308 return reg - 0xa0;
309 }
311 static inline uint64_t bits_b(unsigned reg)
312 {
313 ajla_assert_lo(reg_is_b(reg), (file_line, "bits_b: register %x", reg));
314 return reg - 0xb0;
315 }
317 static const uint8_t regs_saved[] = {
318 R_39,
319 R_40,
320 R_41,
321 R_42,
322 R_43,
323 R_44,
324 R_45,
325 R_46,
326 R_47,
327 R_48,
328 R_49,
329 R_50,
330 R_51,
331 R_52,
332 R_53,
333 R_54,
334 R_55,
335 R_56,
336 R_57,
337 R_58,
338 R_59,
339 R_60,
340 R_61,
341 R_62,
342 R_63,
343 R_64,
344 R_65,
345 R_66,
346 R_67,
347 R_68,
348 R_69,
349 R_70,
350 R_71,
351 R_72,
352 R_73,
353 R_74,
354 R_75,
355 R_76,
356 R_77,
357 R_78,
358 R_79,
359 R_80,
360 R_81,
361 R_82,
362 R_83,
363 R_84,
364 R_85,
365 R_86,
366 R_87,
367 R_88,
368 R_89,
369 R_90,
370 R_91,
371 };
372 static const uint8_t regs_volatile[] = {
373 R_11,
374 R_21,
375 R_22,
376 R_23,
377 R_24,
378 R_25,
379 R_26,
380 R_27,
381 R_28,
382 R_29,
383 R_30,
384 R_31,
385 };
386 static const uint8_t fp_saved[] = { 0 };
387 #define n_fp_saved 0U
388 static const uint8_t fp_volatile[] = {
389 FR_8,
390 FR_9,
391 FR_10,
392 FR_11,
393 FR_12,
394 FR_13,
395 FR_14,
396 FR_15,
397 FR_32,
398 FR_33,
399 FR_34,
400 FR_35,
401 FR_36,
402 FR_37,
403 FR_38,
404 FR_39,
405 FR_40,
406 FR_41,
407 FR_42,
408 FR_43,
409 FR_44,
410 FR_45,
411 FR_46,
412 FR_47,
413 FR_48,
414 FR_49,
415 FR_50,
416 FR_51,
417 FR_52,
418 FR_53,
419 FR_54,
420 FR_55,
421 FR_56,
422 FR_57,
423 FR_58,
424 FR_59,
425 FR_60,
426 FR_61,
427 FR_62,
428 FR_63,
429 };
430 #define reg_is_saved(r) ((r) >= R_32 && (r) <= R_95)
432 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
433 {
434 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
435 gen_one(reg);
436 gen_one(ARG_IMM);
437 gen_eight(c);
438 return true;
439 }
441 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned attr_unused purpose, unsigned attr_unused size)
442 {
443 if (!imm) {
444 ctx->offset_imm = imm;
445 ctx->offset_reg = false;
446 ctx->base_reg = base;
447 } else {
448 g(gen_imm(ctx, imm, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
449 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
450 gen_one(R_OFFSET_IMM);
451 gen_one(base);
452 gen_imm_offset();
453 ctx->offset_imm = 0;
454 ctx->offset_reg = false;
455 ctx->base_reg = R_OFFSET_IMM;
456 }
457 return true;
458 }
460 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
461 {
462 switch (purpose) {
463 case IMM_PURPOSE_STORE_VALUE:
464 if (!imm)
465 return true;
466 break;
467 case IMM_PURPOSE_ADD:
468 case IMM_PURPOSE_MOVR:
469 if (imm >= -0x2000 && imm < 0x2000)
470 return true;
471 break;
472 case IMM_PURPOSE_SUB:
473 if (imm > -0x2000 && imm <= 0x2000)
474 return true;
475 break;
476 case IMM_PURPOSE_AND:
477 case IMM_PURPOSE_OR:
478 case IMM_PURPOSE_XOR:
479 if (imm >= -0x80 && imm < 0x80)
480 return true;
481 break;
482 case IMM_PURPOSE_CMP:
483 case IMM_PURPOSE_CMP_LOGICAL:
484 if (imm > -0x80 && imm < 0x80)
485 return true;
486 break;
487 case IMM_PURPOSE_ANDN:
488 break;
489 case IMM_PURPOSE_TEST:
490 break;
491 case IMM_PURPOSE_BITWISE:
492 return true;
493 default:
494 internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
495 }
496 return false;
497 }
499 static bool attr_w gen_entry(struct codegen_context *ctx)
500 {
501 gen_insn(INSN_IA64_ALLOC, OP_SIZE_NATIVE, 0, 0);
502 gen_one(R_SAVED_AR_PFS);
503 gen_one(ARG_IMM);
504 gen_eight(N_SAVED_REGS);
505 gen_one(ARG_IMM);
506 gen_eight(N_SAVED_REGS - 4);
508 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
509 gen_one(R_SAVED_B0);
510 gen_one(B_0);
512 gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
513 gen_one(R_ENTRY);
515 gen_insn(INSN_RET, 0, 0, 0);
517 return true;
518 }
520 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
521 {
522 g(gen_load_constant(ctx, R_RET1, ip));
524 gen_insn(INSN_JMP, 0, 0, 0);
525 gen_four(escape_label);
527 return true;
528 }
530 static bool attr_w gen_escape(struct codegen_context *ctx)
531 {
532 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
533 gen_one(R_RET0);
534 gen_one(R_FRAME);
536 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
537 gen_one(B_0);
538 gen_one(R_SAVED_B0);
540 gen_insn(INSN_IA64_DEALLOC, OP_SIZE_NATIVE, 0, 0);
541 gen_one(R_SAVED_AR_PFS);
543 gen_insn(INSN_RET, 0, 0, 0);
545 return true;
546 }
548 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
549 {
550 return true;
551 }
553 static bool attr_w gen_get_upcall_pointer(struct codegen_context *ctx, unsigned offset, unsigned reg)
554 {
555 g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
556 gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
557 gen_one(reg);
558 gen_address_offset();
560 return true;
561 }
563 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
564 {
565 g(gen_get_upcall_pointer(ctx, offset, R_SCRATCH_NA_1));
567 g(gen_address(ctx, R_SCRATCH_NA_1, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
568 gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
569 gen_one(R_SCRATCH_NA_2);
570 gen_address_offset();
572 g(gen_address(ctx, R_SCRATCH_NA_1, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
573 gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
574 gen_one(R_GP);
575 gen_address_offset();
577 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
578 gen_one(R_SCRATCH_B);
579 gen_one(R_SCRATCH_NA_2);
581 gen_insn(INSN_CALL_INDIRECT, OP_SIZE_8, 0, 0);
582 gen_one(R_SCRATCH_B);
584 g(gen_upcall_end(ctx, n_args));
586 return true;
587 }
589 static bool attr_w gen_cmp_test_jmp(struct codegen_context *ctx, unsigned insn, unsigned op_size, unsigned reg1, unsigned reg2, unsigned cond, uint32_t label);
591 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
592 {
593 g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
594 gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
595 gen_one(R_SCRATCH_1);
596 gen_address_offset();
598 g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_4, R_SCRATCH_1, R_TIMESTAMP, COND_NE, escape_label));
600 return true;
601 }