c1-riscv.inc

   1 /*
   2  * Copyright (C) 2024 Mikulas Patocka
   3  *
   4  * This file is part of Ajla.
   5  *
   6  * Ajla is free software: you can redistribute it and/or modify it under the
   7  * terms of the GNU General Public License as published by the Free Software
   8  * Foundation, either version 3 of the License, or (at your option) any later
   9  * version.
  10  *
  11  * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
  12  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * Ajla. If not, see <https://www.gnu.org/licenses/>.
  17  */
  18
  19 #define OP_SIZE_NATIVE                  OP_SIZE_8
  20 #define OP_SIZE_ADDRESS                 OP_SIZE_NATIVE
  21
  22 #define JMP_LIMIT                       JMP_EXTRA_LONG
  23
  24 #define UNALIGNED_TRAP                  (!cpu_test_feature(CPU_FEATURE_unaligned))
  25
  26 #define ALU_WRITES_FLAGS(alu, im)       0
  27 #define ALU1_WRITES_FLAGS(alu)          0
  28 #define ROT_WRITES_FLAGS(alu, size, im) 0
  29 #define COND_IS_LOGICAL(cond)           0
  30
  31 #define ARCH_PARTIAL_ALU(size)          0
  32 #define ARCH_IS_3ADDRESS(alu, f)        1
  33 #define ARCH_IS_3ADDRESS_IMM(alu, f)    1
  34 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
  35 #define ARCH_IS_3ADDRESS_ROT_IMM(alu)   1
  36 #define ARCH_IS_2ADDRESS(alu)           1
  37 #define ARCH_IS_3ADDRESS_FP             1
  38 #define ARCH_HAS_JMP_2REGS(cond)        1
  39 #define ARCH_HAS_FLAGS                  0
  40 #define ARCH_PREFERS_SX(size)           0
  41 #define ARCH_HAS_BWX                    1
  42 #define ARCH_HAS_MUL                    1
  43 #define ARCH_HAS_DIV                    1
  44 #define ARCH_HAS_ANDN                   cpu_test_feature(CPU_FEATURE_zbb)
  45 #define ARCH_HAS_SHIFTED_ADD(bits)      ((bits) <= 3 && cpu_test_feature(CPU_FEATURE_zba))
  46 #define ARCH_HAS_BTX(btx, size, cnst)   (((size) == OP_SIZE_8 || (cnst)) && cpu_test_feature(CPU_FEATURE_zbs))
  47 #define ARCH_SHIFT_SIZE                 OP_SIZE_4
  48 #define ARCH_BOOL_SIZE                  OP_SIZE_NATIVE
  49 #define ARCH_HAS_FP_GP_MOV              0
  50 #define ARCH_NEEDS_BARRIER              0
  51
  52 #define i_size(size)                    OP_SIZE_NATIVE
  53 #define i_size_rot(size)                maximum(size, OP_SIZE_4)
  54 #define i_size_cmp(size)                OP_SIZE_NATIVE
  55
  56 #define R_ZERO          0x00
  57 #define R_RA            0x01
  58 #define R_SP            0x02
  59 #define R_GP            0x03
  60 #define R_TP            0x04
  61 #define R_T0            0x05
  62 #define R_T1            0x06
  63 #define R_T2            0x07
  64 #define R_S0            0x08
  65 #define R_S1            0x09
  66 #define R_A0            0x0a
  67 #define R_A1            0x0b
  68 #define R_A2            0x0c
  69 #define R_A3            0x0d
  70 #define R_A4            0x0e
  71 #define R_A5            0x0f
  72 #define R_A6            0x10
  73 #define R_A7            0x11
  74 #define R_S2            0x12
  75 #define R_S3            0x13
  76 #define R_S4            0x14
  77 #define R_S5            0x15
  78 #define R_S6            0x16
  79 #define R_S7            0x17
  80 #define R_S8            0x18
  81 #define R_S9            0x19
  82 #define R_S10           0x1a
  83 #define R_S11           0x1b
  84 #define R_T3            0x1c
  85 #define R_T4            0x1d
  86 #define R_T5            0x1e
  87 #define R_T6            0x1f
  88
  89 #define R_FT0           0x20
  90 #define R_FT1           0x21
  91 #define R_FT2           0x22
  92 #define R_FT3           0x23
  93 #define R_FT4           0x24
  94 #define R_FT5           0x25
  95 #define R_FT6           0x26
  96 #define R_FT7           0x27
  97 #define R_FS0           0x28
  98 #define R_FS1           0x29
  99 #define R_FA0           0x2a
 100 #define R_FA1           0x2b
 101 #define R_FA2           0x2c
 102 #define R_FA3           0x2d
 103 #define R_FA4           0x2e
 104 #define R_FA5           0x2f
 105 #define R_FA6           0x30
 106 #define R_FA7           0x31
 107 #define R_FS2           0x32
 108 #define R_FS3           0x33
 109 #define R_FS4           0x34
 110 #define R_FS5           0x35
 111 #define R_FS6           0x36
 112 #define R_FS7           0x37
 113 #define R_FS8           0x38
 114 #define R_FS9           0x39
 115 #define R_FS10          0x3a
 116 #define R_FS11          0x3b
 117 #define R_FT8           0x3c
 118 #define R_FT9           0x3d
 119 #define R_FT10          0x3e
 120 #define R_FT11          0x3f
 121
 122 #define R_FRAME         R_S0
 123 #define R_UPCALL        R_S1
 124 #define R_TIMESTAMP     R_S2
 125
 126 #define R_SCRATCH_1     R_A0
 127 #define R_SCRATCH_2     R_A1
 128 #define R_SCRATCH_3     R_A2
 129 #define R_SCRATCH_4     R_A3
 130 #define R_SCRATCH_NA_1  R_A4
 131 #define R_SCRATCH_NA_2  R_A5
 132 #ifdef HAVE_BITWISE_FRAME
 133 #define R_SCRATCH_NA_3  R_A6
 134 #endif
 135
 136 #define R_SAVED_1       R_S3
 137 #define R_SAVED_2       R_S4
 138
 139 #define R_ARG0          R_A0
 140 #define R_ARG1          R_A1
 141 #define R_ARG2          R_A2
 142 #define R_ARG3          R_A3
 143 #define R_RET0          R_A0
 144 #define R_RET1          R_A1
 145
 146 #define R_OFFSET_IMM    R_T0
 147 #define R_CONST_IMM     R_T1
 148 #define R_CONST_HELPER  R_T2
 149 #define R_CMP_RESULT    R_T3
 150
 151 #define FR_SCRATCH_1    R_FT0
 152 #define FR_SCRATCH_2    R_FT1
 153
 154 #define SUPPORTED_FP    0x6
 155
 156 #define FRAME_SIZE      0x70
 157
 158 static bool reg_is_fp(unsigned reg)
 159 {
 160         return reg >= 0x20 && reg < 0x40;
 161 }
 162
 163 static const uint8_t regs_saved[] = { R_S5, R_S6, R_S7, R_S8, R_S9, R_S10, R_S11 };
 164 static const uint8_t regs_volatile[] = { R_RA,
 165 #ifndef HAVE_BITWISE_FRAME
 166         R_A6,
 167 #endif
 168         R_A7, R_T4, R_T5, R_T6 };
 169 static const uint8_t fp_saved[] = { 0 };
 170 #define n_fp_saved 0U
 171 static const uint8_t fp_volatile[] = { R_FT2, R_FT3, R_FT4, R_FT5, R_FT6, R_FT7, R_FA0, R_FA1, R_FA2, R_FA3, R_FA4, R_FA5, R_FA6, R_FA7, R_FT8, R_FT9, R_FT10, R_FT11 };
 172 #define reg_is_saved(r) (((r) >= R_S0 && (r) <= R_S1) || ((r) >= R_S2 && (r) <= R_S11) || ((r) >= R_FS0 && (r) <= R_FS1) || ((r) >= R_FS2 && (r) <= R_FS11))
 173
 174 static const struct {
 175         uint32_t l;
 176         uint16_t s;
 177 } riscv_compress[] = {
 178 #include "riscv-c.inc"
 179 };
 180
 181 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
 182 {
 183         unsigned r = R_ZERO;
 184         int32_t c1, c2, c3, c4;
 185
 186         c1 = c & 0xfffUL;
 187         if (c1 & 0x800)
 188                 c1 |= -0x800;
 189         if (c1 < 0)
 190                 c += 0x1000UL;
 191
 192         c2 = (c >> 12) & 0xfffffUL;
 193         if (c2 & 0x80000)
 194                 c2 |= -0x80000;
 195         if (c2 < 0)
 196                 c += 0x100000000UL;
 197
 198         c3 = (c >> 32) & 0xfffUL;
 199         if (c3 & 0x800)
 200                 c3 |= -0x800;
 201         if (c3 < 0)
 202                 c += 0x100000000000UL;
 203
 204         c4 = c >> 44;
 205         if (c4 & 0x80000)
 206                 c4 |= -0x80000;
 207
 208         if (c4) {
 209                 gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 210                 gen_one(reg);
 211                 gen_one(ARG_IMM);
 212                 gen_eight((uint64_t)c4 << 12);
 213                 r = reg;
 214         }
 215         if (c3) {
 216                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 217                 gen_one(reg);
 218                 gen_one(r);
 219                 gen_one(ARG_IMM);
 220                 gen_eight(c3);
 221                 r = reg;
 222         }
 223         if (r != R_ZERO) {
 224                 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
 225                 gen_one(r);
 226                 gen_one(r);
 227                 gen_one(ARG_IMM);
 228                 gen_eight(32);
 229         }
 230         if (c2) {
 231                 if (r != R_ZERO) {
 232                         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 233                         gen_one(R_CONST_HELPER);
 234                         gen_one(ARG_IMM);
 235                         gen_eight((uint64_t)c2 << 12);
 236
 237                         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 238                         gen_one(r);
 239                         gen_one(r);
 240                         gen_one(R_CONST_HELPER);
 241                 } else {
 242                         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 243                         gen_one(reg);
 244                         gen_one(ARG_IMM);
 245                         gen_eight((uint64_t)c2 << 12);
 246                         r = reg;
 247                 }
 248         }
 249         if (c1 || r == R_ZERO) {
 250                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 251                 gen_one(reg);
 252                 gen_one(r);
 253                 gen_one(ARG_IMM);
 254                 gen_eight(c1);
 255         }
 256         return true;
 257 }
 258
 259 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned purpose, unsigned size)
 260 {
 261         ctx->base_reg = base;
 262         ctx->offset_imm = imm;
 263         ctx->offset_reg = false;
 264         switch (purpose) {
 265                 case IMM_PURPOSE_LDR_OFFSET:
 266                 case IMM_PURPOSE_LDR_SX_OFFSET:
 267                 case IMM_PURPOSE_STR_OFFSET:
 268                 case IMM_PURPOSE_VLDR_VSTR_OFFSET:
 269                 case IMM_PURPOSE_MVI_CLI_OFFSET:
 270                         if (likely(imm >= -0x800) && likely(imm < 0x800))
 271                                 return true;
 272                         break;
 273                 default:
 274                         internal(file_line, "gen_address: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 275         }
 276         g(gen_load_constant(ctx, R_OFFSET_IMM, imm));
 277         gen_insn(INSN_ALU, OP_SIZE_ADDRESS, ALU_ADD, 0);
 278         gen_one(R_OFFSET_IMM);
 279         gen_one(R_OFFSET_IMM);
 280         gen_one(base);
 281         ctx->base_reg = R_OFFSET_IMM;
 282         ctx->offset_imm = 0;
 283         return true;
 284 }
 285
 286 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
 287 {
 288         switch (purpose) {
 289                 case IMM_PURPOSE_STORE_VALUE:
 290                         if (!imm)
 291                                 return true;
 292                         break;
 293                 case IMM_PURPOSE_ADD:
 294                 case IMM_PURPOSE_AND:
 295                 case IMM_PURPOSE_OR:
 296                 case IMM_PURPOSE_XOR:
 297                 case IMM_PURPOSE_TEST:
 298                 case IMM_PURPOSE_CMP:
 299                 case IMM_PURPOSE_CMP_LOGICAL:
 300                         if (likely(imm >= -0x800) && likely(imm < 0x800))
 301                                 return true;
 302                         break;
 303                 case IMM_PURPOSE_SUB:
 304                         if (likely(imm > -0x800) && likely(imm <= 0x800))
 305                                 return true;
 306                         break;
 307                 case IMM_PURPOSE_ANDN:
 308                         break;
 309                 case IMM_PURPOSE_JMP_2REGS:
 310                         break;
 311                 case IMM_PURPOSE_MUL:
 312                         break;
 313                 case IMM_PURPOSE_BITWISE:
 314                         return true;
 315                 default:
 316                         internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 317         }
 318         return false;
 319 }
 320
 321 static bool attr_w gen_entry(struct codegen_context *ctx)
 322 {
 323         g(gen_imm(ctx, -FRAME_SIZE, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
 324         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 325         gen_one(R_SP);
 326         gen_one(R_SP);
 327         gen_imm_offset();
 328
 329         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x08, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 330         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 331         gen_address_offset();
 332         gen_one(R_RA);
 333
 334         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x10, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 335         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 336         gen_address_offset();
 337         gen_one(R_S0);
 338
 339         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x18, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 340         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 341         gen_address_offset();
 342         gen_one(R_S1);
 343
 344         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x20, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 345         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 346         gen_address_offset();
 347         gen_one(R_S2);
 348
 349         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x28, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 350         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 351         gen_address_offset();
 352         gen_one(R_S3);
 353
 354         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x30, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 355         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 356         gen_address_offset();
 357         gen_one(R_S4);
 358
 359         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x38, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 360         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 361         gen_address_offset();
 362         gen_one(R_S5);
 363
 364         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x40, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 365         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 366         gen_address_offset();
 367         gen_one(R_S6);
 368
 369         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x48, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 370         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 371         gen_address_offset();
 372         gen_one(R_S7);
 373
 374         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x50, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 375         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 376         gen_address_offset();
 377         gen_one(R_S8);
 378
 379         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x58, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 380         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 381         gen_address_offset();
 382         gen_one(R_S9);
 383
 384         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x60, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 385         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 386         gen_address_offset();
 387         gen_one(R_S10);
 388
 389         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x68, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 390         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 391         gen_address_offset();
 392         gen_one(R_S11);
 393
 394         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 395         gen_one(R_FRAME);
 396         gen_one(R_ARG0);
 397
 398         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 399         gen_one(R_UPCALL);
 400         gen_one(R_ARG1);
 401
 402         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 403         gen_one(R_TIMESTAMP);
 404         gen_one(R_ARG2);
 405
 406         gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
 407         gen_one(R_ARG3);
 408
 409         return true;
 410 }
 411
 412 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
 413 {
 414         g(gen_load_constant(ctx, R_RET1, (int32_t)ip));
 415
 416         gen_insn(INSN_JMP, 0, 0, 0);
 417         gen_four(escape_label);
 418
 419         return true;
 420 }
 421
 422 static bool attr_w gen_escape(struct codegen_context *ctx)
 423 {
 424         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 425         gen_one(R_RET0);
 426         gen_one(R_FRAME);
 427
 428         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x08, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 429         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 430         gen_one(R_RA);
 431         gen_address_offset();
 432
 433         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x10, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 434         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 435         gen_one(R_S0);
 436         gen_address_offset();
 437
 438         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x18, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 439         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 440         gen_one(R_S1);
 441         gen_address_offset();
 442
 443         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x20, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 444         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 445         gen_one(R_S2);
 446         gen_address_offset();
 447
 448         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x28, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 449         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 450         gen_one(R_S3);
 451         gen_address_offset();
 452
 453         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x30, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 454         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 455         gen_one(R_S4);
 456         gen_address_offset();
 457
 458         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x38, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 459         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 460         gen_one(R_S5);
 461         gen_address_offset();
 462
 463         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x40, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 464         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 465         gen_one(R_S6);
 466         gen_address_offset();
 467
 468         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x48, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 469         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 470         gen_one(R_S7);
 471         gen_address_offset();
 472
 473         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x50, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 474         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 475         gen_one(R_S8);
 476         gen_address_offset();
 477
 478         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x58, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 479         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 480         gen_one(R_S9);
 481         gen_address_offset();
 482
 483         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x60, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 484         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 485         gen_one(R_S10);
 486         gen_address_offset();
 487
 488         g(gen_address(ctx, R_SP, FRAME_SIZE - 0x68, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 489         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 490         gen_one(R_S11);
 491         gen_address_offset();
 492
 493         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
 494         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 495         gen_one(R_SP);
 496         gen_one(R_SP);
 497         gen_imm_offset();
 498
 499         gen_insn(INSN_RET, 0, 0, 0);
 500
 501         return true;
 502 }
 503
 504 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
 505 {
 506         return true;
 507 }
 508
 509 static bool attr_w gen_get_upcall_pointer(struct codegen_context *ctx, unsigned offset, unsigned reg)
 510 {
 511         g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_ADDRESS));
 512         gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
 513         gen_one(reg);
 514         gen_address_offset();
 515
 516         return true;
 517 }
 518
 519 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
 520 {
 521         g(gen_get_upcall_pointer(ctx, offset, R_SCRATCH_NA_1));
 522
 523         gen_insn(INSN_CALL_INDIRECT, OP_SIZE_ADDRESS, 0, 0);
 524         gen_one(R_SCRATCH_NA_1);
 525
 526         g(gen_upcall_end(ctx, n_args));
 527
 528         return true;
 529 }
 530
 531 static bool attr_w gen_cmp_test_jmp(struct codegen_context *ctx, unsigned insn, unsigned op_size, unsigned reg1, unsigned reg2, unsigned cond, uint32_t label);
 532
 533 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
 534 {
 535         g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_SX_OFFSET, OP_SIZE_4));
 536         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 537         gen_one(R_SCRATCH_1);
 538         gen_address_offset();
 539
 540         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_TIMESTAMP, COND_NE, escape_label));
 541
 542         return true;
 543 }