| blob | 563955bda2fe1413156964c0964fbe0cc41447f8 |
1 /*
2 * Copyright (C) 2024 Mikulas Patocka
3 *
4 * This file is part of Ajla.
5 *
6 * Ajla is free software: you can redistribute it and/or modify it under the
7 * terms of the GNU General Public License as published by the Free Software
8 * Foundation, either version 3 of the License, or (at your option) any later
9 * version.
10 *
11 * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * Ajla. If not, see <https://www.gnu.org/licenses/>.
17 */
19 #define X86_ALU_RM8_R8 0x00
20 #define X86_ALU_RM16_R16 0x01
21 #define X86_ALU_R8_RM8 0x02
22 #define X86_ALU_R16_RM16 0x03
23 #define X86_ALU_AL_IMM8 0x04
24 #define X86_ALU_AX_IMM16 0x05
25 #define X86_0F 0x0f
26 #define X86_ES 0x26
27 #define X86_CS 0x2e
28 #define X86_SS 0x36
29 #define X86_DS 0x3e
30 #define X86_REX 0x40
31 #define X86_REX_B 0x01
32 #define X86_REX_X 0x02
33 #define X86_REX_R 0x04
34 #define X86_REX_W 0x08
35 #define X86_INC_R16 0x40
36 #define X86_DEC_R16 0x48
37 #define X86_PUSH_R16 0x50
38 #define X86_POP_R16 0x58
39 #define X86_MOVSXD 0x63
40 #define X86_FS 0x64
41 #define X86_GS 0x65
42 #define X86_OP_SIZE 0x66
43 #define X86_PUSH_IMM16 0x68
44 #define X86_IMUL_R16_RM16_IMM16 0x69
45 #define X86_PUSH_IMM8 0x6a
46 #define X86_IMUL_R16_RM16_IMM8 0x6b
47 #define X86_JCC_8 0x70
48 #define X86_ALU_RM8_IMM8 0x80
49 #define X86_ALU_RM16_IMM16 0x81
50 #define X86_ALU_RM16_IMM8 0x83
51 #define X86_TEST_RM8_R8 0x84
52 #define X86_TEST_RM16_R16 0x85
53 #define X86_MOV_RM8_R8 0x88
54 #define X86_MOV_RM16_R16 0x89
55 #define X86_MOV_R8_RM8 0x8a
56 #define X86_MOV_R16_RM16 0x8b
57 #define X86_LEA_R16_RM16 0x8d
58 #define X86_CBW 0x98
59 #define X86_CWD 0x99
60 #define X86_MOV_AL_M16 0xa0
61 #define X86_MOV_AX_M16 0xa1
62 #define X86_MOV_M16_AL 0xa2
63 #define X86_MOV_M16_AX 0xa3
64 #define X86_MOVSB 0xa4
65 #define X86_TEST_AL_IMM8 0xa8
66 #define X86_TEST_AX_IMM16 0xa9
67 #define X86_STOSB 0xaa
68 #define X86_MOV_R16_IMM16 0xb8
69 #define X86_ROT_RM8_IMM8 0xc0
70 #define X86_ROT_RM16_IMM8 0xc1
71 #define X86_RET_IMM16 0xc2
72 #define X86_RET 0xc3
73 #define X86_VEX_3 0xc4
74 #define X86_VEX_2 0xc5
75 #define X86_MOV_RM8_IMM8 0xc6
76 #define X86_MOV_RM16_IMM16 0xc7
77 #define X86_MOV_R16_IMM16_REG 0x0
78 #define X86_8F 0x8f
79 #define X86_8F_POP 0x0
80 #define X86_ROT_RM8_1 0xd0
81 #define X86_ROT_RM16_1 0xd1
82 #define X86_ROT_RM8_CL 0xd2
83 #define X86_ROT_RM16_CL 0xd3
84 #define X86_JMP_16 0xe9
85 #define X86_JMP_8 0xeb
86 #define X86_REPNE 0xf2
87 #define X86_REPE 0xf3
88 #define X86_F6 0xf6
89 #define X86_F6_TEST_RM8_IMM8 0x0
90 #define X86_F6_NOT_RM8 0x2
91 #define X86_F6_NEG_RM8 0x3
92 #define X86_F6_MUL_RM8 0x4
93 #define X86_F6_IMUL_RM8 0x5
94 #define X86_F6_DIV_RM8 0x6
95 #define X86_F6_IDIV_RM8 0x7
96 #define X86_F7 0xf7
97 #define X86_F7_TEST_RM16_IMM16 0x0
98 #define X86_F7_NOT_RM16 0x2
99 #define X86_F7_NEG_RM16 0x3
100 #define X86_F7_MUL_RM16 0x4
101 #define X86_F7_IMUL_RM16 0x5
102 #define X86_F7_DIV_RM16 0x6
103 #define X86_F7_IDIV_RM16 0x7
104 #define X86_FE 0xfe
105 #define X86_FE_INC_RM8 0x0
106 #define X86_FE_DEC_RM8 0x1
107 #define X86_FF 0xff
108 #define X86_FF_INC_RM16 0x0
109 #define X86_FF_DEC_RM16 0x1
110 #define X86_FF_CALL_INDIRECT 0x2
111 #define X86_FF_JMP_INDIRECT 0x4
112 #define X86_FF_PUSH 0x6
114 #define X86_0F_MOVSS_X128_M32 0x10
115 #define X86_0F_MOVSS_M32_X128 0x11
116 #define X86_0F_MOVAPS_X128_M128 0x28
117 #define X86_0F_MOVAPS_M128_X128 0x29
118 #define X86_0F_CVTSI2SS_X128_RM32 0x2a
119 #define X86_0F_CVTTSS2SI_X128_RM32 0x2c
120 #define X86_0F_UCOMISS_X128_RM32 0x2e
121 #define X86_0F_38 0x38
122 #define X86_0F_3A 0x3a
123 #define X86_0F_CMOVCC_R16_RM16 0x40
124 #define X86_0F_SQRTPS_X128_M32 0x51
125 #define X86_0F_ANDPS_X128_M128 0x54
126 #define X86_0F_ANDNPS_X128_M128 0x55
127 #define X86_0F_ORPS_X128_M128 0x56
128 #define X86_0F_XORPS_X128_M128 0x57
129 #define X86_0F_ADDPS_X128_M32 0x58
130 #define X86_0F_MULPS_X128_M32 0x59
131 #define X86_0F_SUBPS_X128_M32 0x5c
132 #define X86_0F_DIVPS_X128_M32 0x5e
133 #define X86_0F_MOVD_X128_RM32 0x6e
134 #define X86_0F_MOVD_RM32_X128 0x7e
135 #define X86_0F_JCC_16 0x80
136 #define X86_0F_SETCC_RM8 0x90
137 #define X86_0F_BT_RM16_R16 0xa3
138 #define X86_0F_BTS_RM16_R16 0xab
139 #define X86_0F_BTR_RM16_R16 0xb3
140 #define X86_0F_BTX_RM16_IMM8 0xba
141 #define X86_0F_BTX_BT_RM16_IMM8 0x4
142 #define X86_0F_BTX_BTS_RM16_IMM8 0x5
143 #define X86_0F_BTX_BTR_RM16_IMM8 0x6
144 #define X86_0F_BTX_BTC_RM16_IMM8 0x7
145 #define X86_0F_BSWAP 0xc8
146 #define X86_0F_BTC_RM16_R16 0xbb
147 #define X86_0F_IMUL_R16_RM16 0xaf
148 #define X86_0F_MOVZX_R16_RM8 0xb6
149 #define X86_0F_MOVZX_R16_RM16 0xb7
150 #define X86_0F_POPCNT_R16_RM16 0xb8
151 #define X86_0F_BSF_R16_RM16 0xbc
152 #define X86_0F_BSR_R16_RM16 0xbd
153 #define X86_0F_MOVSX_R16_RM8 0xbe
154 #define X86_0F_MOVSX_R16_RM16 0xbf
155 #define X86_0F_PINSRW_X128_RM16_IMM8 0xc4
157 #define X86_0F_38_CVTPH2PS_X128_RM64 0x13
158 #define X86_0F_38_ROTX 0xf7
160 #define X86_0F_3A_ROUNDSS_X128_M32 0x0a
161 #define X86_0F_3A_ROUNDSD_X128_M64 0x0b
162 #define X86_0F_3A_PEXTRW_RM16_X128_IMM8 0x15
163 #define X86_0F_3A_CVTPS2PH_RM64_X128 0x1d
165 #define X87_FLD_RM32 0xd9
166 #define X87_FLD_RM32_X 0x0
167 #define X87_FLDCW 0xd9
168 #define X87_FLDCW_X 0x5
169 #define X87_FILD_M32 0xdb
170 #define X87_FILD_M32_X 0x0
171 #define X87_FISTTP_M32 0xdb
172 #define X87_FISTTP_M32_X 0x1
173 #define X87_FISTP_M32 0xdb
174 #define X87_FISTP_M32_X 0x3
175 #define X87_FLD_M80 0xdb
176 #define X87_FLD_M80_X 0x5
177 #define X87_FLD_M64 0xdd
178 #define X87_FLD_M64_X 0x0
179 #define X87_FSTP_M32 0xd9
180 #define X87_FSTP_M32_X 0x3
181 #define X87_FSTP_M80 0xdb
182 #define X87_FSTP_M80_X 0x7
183 #define X87_FSTP_RM64 0xdd
184 #define X87_FSTP_RM64_X 0x3
185 #define X87_FALU_ST_RM32 0xd8
186 #define X87_FCHS 0xd9
187 #define X87_FCHS_2 0xe0
188 #define X87_FSQRT 0xd9
189 #define X87_FSQRT_2 0xfa
190 #define X87_FRNDINT 0xd9
191 #define X87_FRNDINT_2 0xfc
192 #define X87_FALU_ST_M64 0xdc
193 #define X87_FALU_STi_ST 0xdc
194 #define X87_FISTTP_M64 0xdd
195 #define X87_FISTTP_M64_X 0x1
196 #define X87_FALUP_STi_ST0 0xde
197 #define X87_ALU_ADD 0x0
198 #define X87_ALU_MUL 0x1
199 #define X87_ALU_FCOM 0x2
200 #define X87_ALU_FCOMP 0x3
201 #define X87_ALU_SUBR 0x4
202 #define X87_ALU_SUB 0x5
203 #define X87_ALU_DIVR 0x6
204 #define X87_ALU_DIV 0x7
205 #define X87_FCOMPP 0xde
206 #define X87_FCOMPP_2 0xd9
207 #define X87_FILD_M16 0xdf
208 #define X87_FILD_M16_X 0x0
209 #define X87_FISTTP_M16 0xdf
210 #define X87_FISTTP_M16_X 0x1
211 #define X87_FISTP_M16 0xdf
212 #define X87_FISTP_M16_X 0x3
213 #define X87_FILD_M64 0xdf
214 #define X87_FILD_M64_X 0x5
215 #define X87_FISTP_M64 0xdf
216 #define X87_FISTP_M64_X 0x7
217 #define X87_FNSTSW 0xdf
218 #define X87_FNSTSW_2 0xe0
219 #define X87_FCOMIP 0xdf
220 #define X87_FCOMIP_2 0xf0
222 #define SSE_PREFIX_NONE 0
223 #define SSE_PREFIX_66 1
224 #define SSE_PREFIX_F3 2
225 #define SSE_PREFIX_F2 3
227 #define PREFIX_NONE 0
228 #define PREFIX_0F 1
229 #define PREFIX_0F_38 2
230 #define PREFIX_0F_3A 3
232 #ifdef ARCH_X86_32
233 #define cgen_rex(rex) internal(file_line, "cgen_rex: attempting to generate rex in 32-bit mode: %02x", rex)
234 #else
235 #define cgen_rex(rex) cgen_one(rex)
236 #endif
238 #define force_vex 0x10000
240 static bool attr_w cgen_rm_insn(struct codegen_context *ctx, int32_t sse_prefix, uint8_t prefix, uint8_t opcode, unsigned size, bool reg_is_reg, uint8_t reg, uint8_t *arg)
241 {
242 uint8_t rex, mod, rm;
243 int16_t sib;
244 int64_t imm = 0; /* avoid warning */
245 uint8_t addr_size;
246 uint8_t arg_reg;
247 bool need_rex;
249 if (unlikely(R_IS_XMM(reg)))
250 reg -= R_XMM0;
251 if (unlikely(R_IS_XMM(arg[0]))) {
252 arg_reg = arg[0] - R_XMM0;
253 arg = &arg_reg;
254 }
255 if (unlikely(!R_IS_GPR(reg)))
256 internal(file_line, "cgen_rm_insn: invalid register %02x", reg);
258 sib = -1;
259 rex = X86_REX;
260 if (size == OP_SIZE_8)
261 rex |= X86_REX_W;
262 if (reg & 8)
263 rex |= X86_REX_R;
264 if (arg[0] < 0x40) {
265 if (arg[0] & 8)
266 rex |= X86_REX_B;
267 mod = 0xc0;
268 rm = arg[0] & 7;
269 addr_size = 0;
270 } else {
271 uint8_t *imm_ptr = arg + arg_size(arg[0]) - 8;
272 imm = get_imm(imm_ptr);
273 if (unlikely(!imm_is_32bit(imm)))
274 internal(file_line, "cgen_rm_insn: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
275 if (arg[0] == ARG_ADDRESS_0) {
276 address_0:
277 addr_size = 4;
278 mod = 0x00;
279 rm = 0x4;
280 sib = 0x25;
281 goto gen;
282 }
283 if (!imm) {
284 addr_size = 0;
285 } else if (imm >= -0x80 && imm <= 0x7f) {
286 addr_size = 1;
287 } else {
288 addr_size = 4;
289 }
290 if ((arg[1] & 7) == 0x5 && addr_size == 0)
291 addr_size = 1;
292 if (addr_size == 0)
293 mod = 0x00;
294 else if (addr_size == 1)
295 mod = 0x40;
296 else
297 mod = 0x80;
298 if (arg[0] == ARG_ADDRESS_1) {
299 if (reg_is_segment(arg[1])) {
300 static const uint8_t segments[6] = { X86_ES, X86_CS, X86_SS, X86_DS, X86_FS, X86_GS };
301 cgen_one(segments[arg[1] - R_ES]);
302 goto address_0;
303 }
304 if (arg[1] & 8)
305 rex |= X86_REX_B;
306 if ((arg[1] & 7) == 0x4) {
307 rm = 0x4;
308 sib = 0x24;
309 goto gen;
310 }
311 rm = arg[1] & 7;
312 goto gen;
313 }
314 if (arg[0] >= ARG_ADDRESS_1_2 && arg[0] <= ARG_ADDRESS_1_8) {
315 if (unlikely(arg[1] == R_SP))
316 internal(file_line, "cgen_rm_insn: attemptint to scale SP");
317 if (arg[1] & 8)
318 rex |= X86_REX_X;
319 addr_size = 4;
320 mod = 0x00;
321 rm = 0x4;
322 sib = ((arg[0] - ARG_ADDRESS_1) << 6) | ((arg[1] & 7) << 3) | 0x5;
323 goto gen;
324 }
325 if (arg[0] >= ARG_ADDRESS_2 && arg[0] <= ARG_ADDRESS_2_8) {
326 if (unlikely(arg[2] == R_SP))
327 internal(file_line, "cgen_rm_insn: attemptint to scale SP");
328 if (arg[1] & 8)
329 rex |= X86_REX_B;
330 if (arg[2] & 8)
331 rex |= X86_REX_X;
332 rm = 0x4;
333 sib = ((arg[0] - ARG_ADDRESS_2) << 6) | ((arg[2] & 7) << 3) | (arg[1] & 7);
334 goto gen;
335 }
336 internal(file_line, "cgen_rm_insn: invalid argument %02x", arg[0]);
337 }
339 gen:
340 if (unlikely(sse_prefix >= 0)) {
341 if (likely(cpu_test_feature(CPU_FEATURE_avx)) || (sse_prefix & force_vex)) {
342 if ((rex & (X86_REX_X | X86_REX_B | X86_REX_W)) == 0 && prefix == PREFIX_0F) {
343 cgen_one(X86_VEX_2);
344 cgen_one((~rex & X86_REX_R) << 5 | (~(sse_prefix >> 8) & 0xf) << 3 | (sse_prefix & 3));
345 } else {
346 cgen_one(X86_VEX_3);
347 cgen_one((~rex & (X86_REX_R | X86_REX_X | X86_REX_B)) << 5 | prefix);
348 cgen_one((rex & X86_REX_W) << 4 | (~(sse_prefix >> 8) & 0xf) << 3 | (sse_prefix & 3));
349 }
350 goto avx_done;
351 }
352 switch (sse_prefix & 3) {
353 case SSE_PREFIX_66: cgen_one(X86_OP_SIZE); break;
354 case SSE_PREFIX_F3: cgen_one(X86_REPE); break;
355 case SSE_PREFIX_F2: cgen_one(X86_REPNE); break;
356 }
357 } else {
358 if (size == OP_SIZE_2)
359 cgen_one(X86_OP_SIZE);
360 }
361 need_rex = rex != X86_REX;
362 need_rex |= size == OP_SIZE_1 && ((reg_is_reg && !reg_is_fp(reg) && reg >= 4) || (mod == 0xc0 && !reg_is_fp(arg[0]) && arg[0] >= 4));
363 if (prefix == PREFIX_0F && (opcode == X86_0F_MOVZX_R16_RM8 || opcode == X86_0F_MOVSX_R16_RM8)) {
364 need_rex |= mod == 0xc0 && arg[0] >= 4;
365 }
366 if (need_rex)
367 cgen_rex(rex);
369 switch (prefix) {
370 case PREFIX_NONE:
371 break;
372 case PREFIX_0F:
373 cgen_one(X86_0F);
374 break;
375 case PREFIX_0F_38:
376 cgen_one(X86_0F);
377 cgen_one(X86_0F_38);
378 break;
379 case PREFIX_0F_3A:
380 cgen_one(X86_0F);
381 cgen_one(X86_0F_3A);
382 break;
383 default:
384 internal(file_line, "cgen_rm_insn: invalid prefix %u", prefix);
385 }
386 avx_done:
387 cgen_one(opcode);
388 cgen_one(mod | ((reg & 7) << 3) | (rm & 7));
389 if (sib >= 0)
390 cgen_one(sib);
391 switch (addr_size) {
392 case 1:
393 cgen_one(imm);
394 break;
395 case 4:
396 cgen_four(imm);
397 break;
398 }
399 return true;
400 }
402 static bool attr_w cgen_sse_insn(struct codegen_context *ctx, unsigned sse_prefix, unsigned sse_op_map, uint8_t opcode, bool wide, uint8_t reg, uint8_t reg2, uint8_t *arg)
403 {
404 g(cgen_rm_insn(ctx, sse_prefix + (reg2 << 8), sse_op_map, opcode, !wide ? OP_SIZE_4 : OP_SIZE_8, true, reg, arg));
405 return true;
406 }
408 static bool attr_w cgen_push(struct codegen_context *ctx)
409 {
410 uint8_t *arg1 = ctx->code_position;
411 ctx->code_position += arg_size(*arg1);
412 if (likely(R_IS_GPR(arg1[0]))) {
413 if (arg1[0] & 8)
414 cgen_rex(X86_REX | X86_REX_B);
415 cgen_one(X86_PUSH_R16 + (arg1[0] & 7));
416 return true;
417 }
418 if (arg1[0] == ARG_IMM) {
419 int64_t imm;
420 imm = get_imm(&arg1[1]);
421 if (unlikely(!imm_is_32bit(imm)))
422 internal(file_line, "cgen_push: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
423 if (imm >= -0x80 && imm <= 0x7f) {
424 cgen_one(X86_PUSH_IMM8);
425 cgen_one(imm);
426 return true;
427 } else {
428 cgen_one(X86_PUSH_IMM16);
429 cgen_four(imm);
430 return true;
431 }
432 }
433 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_FF, OP_SIZE_4, false, X86_FF_PUSH, arg1));
434 return true;
435 }
437 static bool attr_w cgen_pop(struct codegen_context *ctx)
438 {
439 uint8_t *arg1 = ctx->code_position;
440 ctx->code_position += arg_size(*arg1);
441 if (likely(R_IS_GPR(arg1[0]))) {
442 if (arg1[0] & 8)
443 cgen_rex(X86_REX | X86_REX_B);
444 cgen_one(X86_POP_R16 + (arg1[0] & 7));
445 return true;
446 }
447 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_8F, OP_SIZE_4, false, X86_8F_POP, arg1));
448 return true;
449 }
451 static bool attr_w cgen_mov(struct codegen_context *ctx, unsigned size)
452 {
453 uint8_t *arg1 = ctx->code_position;
454 uint8_t *arg2 = arg1 + arg_size(*arg1);
455 ctx->code_position = arg2 + arg_size(*arg2);
456 if (arg2[0] == ARG_IMM) {
457 int rex = X86_REX;
458 int64_t imm;
459 imm = get_imm(&arg2[1]);
460 if (R_IS_GPR(arg1[0])) {
461 if (arg1[0] & 8)
462 rex |= X86_REX_B;
463 #ifndef ARCH_X86_32
464 if (imm >= 0 && imm < 0x100000000LL)
465 #endif
466 {
467 if (rex != X86_REX)
468 cgen_rex(rex);
469 cgen_one(X86_MOV_R16_IMM16 + (arg1[0] & 7));
470 cgen_four(imm);
471 return true;
472 }
473 if (imm >= ~(int64_t)0x7fffffff && imm < 0) {
474 goto mov_rm;
475 }
476 rex |= X86_REX_W;
477 cgen_rex(rex);
478 cgen_one(X86_MOV_R16_IMM16 + (arg1[0] & 7));
479 cgen_eight(imm);
480 return true;
481 } else {
482 if (size < OP_SIZE_4) {
483 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_MOV_RM8_IMM8 : X86_MOV_RM16_IMM16, size, false, X86_MOV_R16_IMM16_REG, arg1));
484 if (size == OP_SIZE_1)
485 cgen_one(imm);
486 else
487 cgen_two(imm);
488 return true;
489 }
490 mov_rm:
491 if (unlikely(!imm_is_32bit(imm)))
492 internal(file_line, "cgen_mov: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
493 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_MOV_RM16_IMM16, maximum(size, OP_SIZE_4), false, X86_MOV_R16_IMM16_REG, arg1));
494 cgen_four(imm);
495 return true;
496 }
497 }
498 if (arg1[0] == R_AX && size >= OP_SIZE_4 && arg2[0] == ARG_ADDRESS_0) {
499 int64_t imm;
500 imm = get_imm(&arg2[1]);
501 if (size == OP_SIZE_8)
502 cgen_rex(X86_REX | X86_REX_W);
503 cgen_one(X86_MOV_AX_M16);
504 cgen_eight(imm);
505 return true;
506 }
507 if (arg1[0] == ARG_ADDRESS_0 && arg2[0] == R_AX) {
508 uint8_t code = size == OP_SIZE_1 ? X86_MOV_M16_AL : X86_MOV_M16_AX;
509 int64_t imm;
510 imm = get_imm(&arg1[1]);
511 if (size == OP_SIZE_2)
512 cgen_one(X86_OP_SIZE);
513 if (size == OP_SIZE_8)
514 cgen_rex(X86_REX | X86_REX_W);
515 cgen_one(code);
516 cgen_eight(imm);
517 return true;
518 }
519 if (R_IS_XMM(arg1[0]) && ARG_IS_ADDRESS(arg2[0])) {
520 if (size == OP_SIZE_2) {
521 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F, X86_0F_PINSRW_X128_RM16_IMM8, false, arg1[0], R_XMM7, arg2));
522 cgen_one(0x00);
523 return true;
524 }
525 if (size == OP_SIZE_16) {
526 g(cgen_sse_insn(ctx, SSE_PREFIX_NONE, PREFIX_0F, X86_0F_MOVAPS_X128_M128, false, arg1[0], 0, arg2));
527 return true;
528 }
529 g(cgen_sse_insn(ctx, size == OP_SIZE_4 ? SSE_PREFIX_F3 : SSE_PREFIX_F2, PREFIX_0F, X86_0F_MOVSS_X128_M32, false, arg1[0], 0, arg2));
530 return true;
531 }
532 if (ARG_IS_ADDRESS(arg1[0]) && R_IS_XMM(arg2[0])) {
533 if (size == OP_SIZE_2) {
534 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F_3A, X86_0F_3A_PEXTRW_RM16_X128_IMM8, false, arg2[0], 0, arg1));
535 cgen_one(0x00);
536 return true;
537 }
538 if (size == OP_SIZE_16) {
539 g(cgen_sse_insn(ctx, SSE_PREFIX_NONE, PREFIX_0F, X86_0F_MOVAPS_M128_X128, false, arg2[0], 0, arg1));
540 return true;
541 }
542 g(cgen_sse_insn(ctx, size == OP_SIZE_4 ? SSE_PREFIX_F3 : SSE_PREFIX_F2, PREFIX_0F, X86_0F_MOVSS_M32_X128, false, arg2[0], 0, arg1));
543 return true;
544 }
545 if (R_IS_XMM(arg1[0]) && R_IS_XMM(arg2[0])) {
546 g(cgen_sse_insn(ctx, SSE_PREFIX_NONE, PREFIX_0F, X86_0F_MOVAPS_X128_M128, false, arg1[0], 0, arg2));
547 return true;
548 }
549 if (R_IS_XMM(arg1[0]) && R_IS_GPR(arg2[0])) {
550 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F, X86_0F_MOVD_X128_RM32, size == OP_SIZE_8, arg1[0], 0, arg2));
551 return true;
552 }
553 if (R_IS_GPR(arg1[0]) && R_IS_XMM(arg2[0])) {
554 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F, X86_0F_MOVD_RM32_X128, size == OP_SIZE_8, arg2[0], 0, arg1));
555 return true;
556 }
557 if (!R_IS_GPR(arg1[0]) && unlikely(!R_IS_GPR(arg2[0]))) {
558 /*debug("%s", da(ctx->fn,function)->function_name);*/
559 internal(file_line, "cgen_mov: two addresses not supported");
560 }
561 if (!R_IS_GPR(arg1[0])) {
562 uint8_t code = size == OP_SIZE_1 ? X86_MOV_RM8_R8 : X86_MOV_RM16_R16;
563 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, code, size, true, arg2[0], arg1));
564 return true;
565 } else if (size >= OP_SIZE_4) {
566 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_MOV_R16_RM16, size, true, arg1[0], arg2));
567 return true;
568 } else {
569 uint8_t code = size == OP_SIZE_1 ? X86_0F_MOVZX_R16_RM8 : X86_0F_MOVZX_R16_RM16;
570 g(cgen_rm_insn(ctx, -1, PREFIX_0F, code, OP_SIZE_4, false, arg1[0], arg2));
571 return true;
572 }
573 }
575 static bool attr_w cgen_movsx(struct codegen_context *ctx, unsigned size)
576 {
577 uint8_t *arg1, *arg2;
578 if (unlikely(size == OP_SIZE_NATIVE)) {
579 g(cgen_mov(ctx, size));
580 return true;
581 }
582 arg1 = ctx->code_position;
583 arg2 = arg1 + arg_size(*arg1);
584 ctx->code_position = arg2 + arg_size(*arg2);
585 if (size <= OP_SIZE_2) {
586 g(cgen_rm_insn(ctx, -1, PREFIX_0F, size == OP_SIZE_1 ? X86_0F_MOVSX_R16_RM8 : X86_0F_MOVSX_R16_RM16, OP_SIZE_NATIVE, true, arg1[0], arg2));
587 } else {
588 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_MOVSXD, OP_SIZE_NATIVE, true, arg1[0], arg2));
589 }
590 return true;
591 }
593 static bool attr_w cgen_lea(struct codegen_context *ctx, unsigned size)
594 {
595 uint8_t addr[11];
596 uint8_t *arg1, *arg2, *arg3;
598 arg1 = ctx->code_position;
599 arg2 = arg1 + arg_size(*arg1);
600 arg3 = arg2 + arg_size(*arg2);
601 ctx->code_position = arg3 + arg_size(*arg3);
603 if (arg3[0] == ARG_IMM) {
604 int64_t imm;
605 if (arg2[0] == ARG_SHIFTED_REGISTER) {
606 if (unlikely((arg2[1] & ARG_SHIFT_MODE) != ARG_SHIFT_LSL) ||
607 unlikely((arg2[1] & ARG_SHIFT_AMOUNT) > 3))
608 goto invalid;
609 addr[0] = ARG_ADDRESS_1 + (arg2[1] & ARG_SHIFT_AMOUNT);
610 addr[1] = arg2[2];
611 } else {
612 addr[0] = ARG_ADDRESS_1;
613 addr[1] = arg2[0];
614 }
615 imm = get_imm(&arg3[1]);
616 memcpy(&addr[2], &imm, 8);
617 } else if (R_IS_GPR(arg3[0])) {
618 addr[0] = ARG_ADDRESS_2;
619 addr[1] = arg2[0];
620 addr[2] = arg3[0];
621 memset(&addr[3], 0, 8);
622 } else if (arg3[0] == ARG_SHIFTED_REGISTER) {
623 if (unlikely((arg3[1] & ARG_SHIFT_MODE) != ARG_SHIFT_LSL) ||
624 unlikely((arg3[1] & ARG_SHIFT_AMOUNT) > 3))
625 goto invalid;
626 addr[0] = ARG_ADDRESS_2 + (arg3[1] & ARG_SHIFT_AMOUNT);
627 addr[1] = arg2[0];
628 addr[2] = arg3[2];
629 memset(&addr[3], 0, 8);
630 } else {
631 invalid:
632 internal(file_line, "cgen_lea: invalid argument %u, %02x, %02x, %02x", size, arg1[0], arg2[0], arg3[0]);
633 }
634 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_LEA_R16_RM16, size, true, arg1[0], addr));
635 return true;
636 }
638 static bool attr_w cgen_alu(struct codegen_context *ctx, unsigned size, unsigned alu, unsigned writes_flags)
639 {
640 uint8_t *arg1, *arg2, *arg3;
641 if (alu != 7) {
642 arg1 = ctx->code_position;
643 arg2 = arg1 + arg_size(*arg1);
644 arg3 = arg2 + arg_size(*arg2);
645 ctx->code_position = arg3 + arg_size(*arg3);
646 if (unlikely(arg_size(*arg1) != arg_size(*arg2)))
647 internal(file_line, "cgen_alu: three-operand mode not supported");
648 if (unlikely(memcmp(arg1, arg2, arg_size(*arg1))))
649 internal(file_line, "cgen_alu: three-operand mode not supported");
650 } else {
651 arg1 = ctx->code_position;
652 arg2 = arg1;
653 arg3 = arg2 + arg_size(*arg2);
654 ctx->code_position = arg3 + arg_size(*arg3);
655 }
657 if (unlikely(alu == ALU_MUL)) {
658 if (unlikely(arg3[0] == ARG_IMM)) {
659 uint8_t code;
660 int64_t imm;
661 imm = get_imm(&arg3[1]);
662 if (unlikely(!imm_is_32bit(imm)))
663 internal(file_line, "cgen_alu: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
664 code = imm_is_8bit(imm) ? X86_IMUL_R16_RM16_IMM8 : X86_IMUL_R16_RM16_IMM16;
665 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, code, size, true, arg1[0], arg2));
666 if (code == X86_IMUL_R16_RM16_IMM8) {
667 cgen_one(imm);
668 } else if (size == OP_SIZE_2) {
669 cgen_two(imm);
670 } else {
671 cgen_four(imm);
672 }
673 return true;
674 }
675 if (unlikely(size == OP_SIZE_1)) {
676 if (unlikely(arg1[0] != R_AX))
677 internal(file_line, "cgen_alu: imul with unsupported register");
678 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_F6, size, false, X86_F6_IMUL_RM8, arg3));
679 return true;
680 } else {
681 if (unlikely(!R_IS_GPR(arg1[0])))
682 internal(file_line, "cgen_alu: invalid multiply args");
683 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_IMUL_R16_RM16, size, true, arg1[0], arg3));
684 return true;
685 }
686 }
688 if (arg3[0] == ARG_IMM) {
689 uint8_t code;
690 bool bit8;
691 int64_t imm;
692 imm = get_imm(&arg3[1]);
693 if (unlikely(!imm_is_32bit(imm)))
694 internal(file_line, "cgen_alu: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
696 if (!(writes_flags & 2)) {
697 if ((alu == ALU_ADD && imm == 1) || (alu == ALU_SUB && imm == -1)) {
698 #ifdef ARCH_X86_32
699 if (R_IS_GPR(arg1[0]) && size >= OP_SIZE_2) {
700 if (size == OP_SIZE_2)
701 cgen_one(X86_OP_SIZE);
702 cgen_one(X86_INC_R16 + arg1[0]);
703 return true;
704 }
705 #endif
706 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_FE : X86_FF, size, false, X86_FE_INC_RM8, arg1));
707 return true;
708 }
709 if ((alu == ALU_ADD && imm == -1) || (alu == ALU_SUB && imm == 1)) {
710 #ifdef ARCH_X86_32
711 if (R_IS_GPR(arg1[0]) && size >= OP_SIZE_2) {
712 if (size == OP_SIZE_2)
713 cgen_one(X86_OP_SIZE);
714 cgen_one(X86_DEC_R16 + arg1[0]);
715 return true;
716 }
717 #endif
718 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_FE : X86_FF, size, false, X86_FE_DEC_RM8, arg1));
719 return true;
720 }
721 }
723 if (arg1[0] == R_AX) {
724 if (imm_is_8bit(imm) && size >= OP_SIZE_4)
725 goto use_shorter;
726 bit8 = false;
727 code = size == OP_SIZE_1 ? X86_ALU_AL_IMM8 : X86_ALU_AX_IMM16;
728 if (size == OP_SIZE_2)
729 cgen_one(X86_OP_SIZE);
730 if (size == OP_SIZE_8)
731 cgen_rex(X86_REX | X86_REX_W);
732 code += alu * 8;
733 cgen_one(code);
734 } else {
735 use_shorter:
736 bit8 = imm_is_8bit(imm);
737 code = size == OP_SIZE_1 ? X86_ALU_RM8_IMM8 : bit8 ? X86_ALU_RM16_IMM8 : X86_ALU_RM16_IMM16;
738 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, code, size, false, alu, arg1));
739 }
740 if (bit8 || size == OP_SIZE_1) {
741 cgen_one(imm);
742 } else if (size == OP_SIZE_2) {
743 cgen_two(imm);
744 } else {
745 cgen_four(imm);
746 }
747 return true;
748 }
750 if (R_IS_XMM(arg1[0]) && size == OP_SIZE_16) {
751 uint8_t code;
752 switch (alu) {
753 case ALU_AND: code = X86_0F_ANDPS_X128_M128; break;
754 case ALU_ANDN: code = X86_0F_ANDNPS_X128_M128; break;
755 case ALU_OR: code = X86_0F_ORPS_X128_M128; break;
756 case ALU_XOR: code = X86_0F_XORPS_X128_M128; break;
757 default: internal(file_line, "invalid sse alu: %u", alu);
758 }
759 g(cgen_sse_insn(ctx, SSE_PREFIX_NONE, PREFIX_0F, code, false, arg1[0], arg2[0], arg3));
760 return true;
761 }
763 if (!R_IS_GPR(arg1[0]) && unlikely(!R_IS_GPR(arg3[0])))
764 internal(file_line, "cgen_alu: two addresses not supported");
766 if (!R_IS_GPR(arg1[0])) {
767 uint8_t code = size == OP_SIZE_1 ? X86_ALU_RM8_R8 : X86_ALU_RM16_R16;
768 code += alu * 8;
769 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, code, size, true, arg3[0], arg1));
770 return true;
771 } else {
772 uint8_t code = size == OP_SIZE_1 ? X86_ALU_R8_RM8 : X86_ALU_R16_RM16;
773 code += alu * 8;
774 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, code, size, true, arg1[0], arg3));
775 return true;
776 }
777 }
779 static bool attr_w cgen_alu1(struct codegen_context *ctx, unsigned size, unsigned alu)
780 {
781 uint8_t rex;
782 uint8_t *arg1 = ctx->code_position;
783 uint8_t *arg2 = arg1 + arg_size(*arg1);
784 ctx->code_position = arg2 + arg_size(*arg2);
785 if (alu == ALU1_NOT || alu == ALU1_NEG || alu == ALU1_BSWAP) {
786 if (unlikely(arg1[0] != arg2[0]))
787 internal(file_line, "cgen_alu1: arguments mismatch: %x, %x", arg1[0], arg2[0]);
788 }
789 switch (alu) {
790 case ALU1_NOT:
791 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_F6 : X86_F7, size, false, X86_F6_NOT_RM8, arg1));
792 return true;
793 case ALU1_NEG:
794 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_F6 : X86_F7, size, false, X86_F6_NEG_RM8, arg1));
795 return true;
796 case ALU1_BSWAP:
797 if (unlikely(size <= OP_SIZE_2))
798 internal(file_line, "cgen_alu1: bytes or words not supported with this operation");
799 rex = X86_REX;
800 if (!R_IS_GPR(arg1[0]))
801 internal(file_line, "cgen_alu1: bswap needs a register");
802 if (arg1[0] & 8)
803 rex |= X86_REX_B;
804 if (size == OP_SIZE_8)
805 rex |= X86_REX_W;
806 if (rex != X86_REX)
807 cgen_rex(rex);
808 cgen_one(X86_0F);
809 cgen_one(X86_0F_BSWAP + (arg1[0] & 7));
810 return true;
811 case ALU1_BSF:
812 case ALU1_BSR:
813 case ALU1_LZCNT:
814 case ALU1_POPCNT:
815 if (unlikely(size == OP_SIZE_1))
816 internal(file_line, "cgen_alu1: bytes not supported with this operation");
817 if (alu == ALU1_POPCNT || alu == ALU1_LZCNT)
818 cgen_one(X86_REPE);
819 g(cgen_rm_insn(ctx, -1, PREFIX_0F, alu == ALU1_BSF ? X86_0F_BSF_R16_RM16 : alu == ALU1_BSR || alu == ALU1_LZCNT ? X86_0F_BSR_R16_RM16 : X86_0F_POPCNT_R16_RM16, size, true, arg1[0], arg2));
820 return true;
821 default:
822 internal(file_line, "cgen_alu1: invalid operation %u", alu);
823 return false;
824 }
825 }
827 static bool attr_w cgen_test(struct codegen_context *ctx, unsigned size)
828 {
829 uint8_t *arg1, *arg2;
830 arg1 = ctx->code_position;
831 arg2 = arg1 + arg_size(*arg1);
832 ctx->code_position = arg2 + arg_size(*arg2);
834 if (arg2[0] == ARG_IMM) {
835 int64_t imm;
836 imm = get_imm(&arg2[1]);
837 if (arg1[0] == R_AX) {
838 if (size == OP_SIZE_1) {
839 cgen_one(X86_TEST_AL_IMM8);
840 } else if (size == OP_SIZE_2) {
841 cgen_one(X86_OP_SIZE);
842 cgen_one(X86_TEST_AX_IMM16);
843 } else if (size == OP_SIZE_4) {
844 cgen_one(X86_TEST_AX_IMM16);
845 } else {
846 if (unlikely(!imm_is_32bit(imm)))
847 internal(file_line, "cgen_Test: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
848 cgen_rex(X86_REX | X86_REX_W);
849 cgen_one(X86_TEST_AX_IMM16);
850 }
851 } else {
852 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_F6 : X86_F7, size, false, X86_F6_TEST_RM8_IMM8, arg1));
853 }
854 if (size == OP_SIZE_1) {
855 cgen_one(imm);
856 } else if (size == OP_SIZE_2) {
857 cgen_two(imm);
858 } else if (size == OP_SIZE_4) {
859 cgen_four(imm);
860 } else {
861 if (unlikely(!imm_is_32bit(imm)))
862 internal(file_line, "cgen_Test: immediate out of range: %"PRIxMAX"", (uintmax_t)imm);
863 cgen_four(imm);
864 }
865 return true;
866 }
868 if (!R_IS_GPR(arg1[0]) && unlikely(!R_IS_GPR(arg2[0])))
869 internal(file_line, "cgen_test: two addresses not supported");
871 if (!R_IS_GPR(arg1[0])) {
872 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_TEST_RM8_R8 : X86_TEST_RM16_R16, size, true, arg2[0], arg1));
873 } else {
874 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_TEST_RM8_R8 : X86_TEST_RM16_R16, size, true, arg1[0], arg2));
875 }
876 return true;
877 }
879 static bool attr_w cgen_lea3(struct codegen_context *ctx, unsigned size, unsigned shift)
880 {
881 uint8_t addr[11];
882 uint8_t *arg1, *arg2, *arg3, *arg4;
884 arg1 = ctx->code_position;
885 arg2 = arg1 + arg_size(*arg1);
886 arg3 = arg2 + arg_size(*arg2);
887 arg4 = arg3 + arg_size(*arg3);
888 ctx->code_position = arg4 + arg_size(*arg4);
890 if (unlikely(!R_IS_GPR(arg1[0])) || unlikely(!R_IS_GPR(arg2[0])) || unlikely(!R_IS_GPR(arg3[0])) || unlikely(arg4[0] != ARG_IMM))
891 internal(file_line, "cgen_lea3: invalid arguments");
893 addr[0] = ARG_ADDRESS_2 + shift;
894 addr[1] = arg2[0];
895 addr[2] = arg3[0];
896 memcpy(&addr[3], &arg4[1], 8);
898 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_LEA_R16_RM16, size, true, arg1[0], addr));
900 return true;
901 }
903 static bool attr_w cgen_rot(struct codegen_context *ctx, unsigned size, uint8_t rot, unsigned writes_flags)
904 {
905 uint8_t *arg1 = ctx->code_position;
906 uint8_t *arg2 = arg1 + arg_size(*arg1);
907 uint8_t *arg3 = arg2 + arg_size(*arg2);
908 ctx->code_position = arg3 + arg_size(*arg3);
910 if (cpu_test_feature(CPU_FEATURE_bmi2) && size >= OP_SIZE_4 && arg3[0] != ARG_IMM && !writes_flags && (rot == ROT_SHL || rot == ROT_SHR || rot == ROT_SAR)) {
911 int32_t sse_prefix;
912 switch (rot) {
913 case ROT_SHL: sse_prefix = SSE_PREFIX_66; break;
914 case ROT_SAR: sse_prefix = SSE_PREFIX_F3; break;
915 case ROT_SHR: sse_prefix = SSE_PREFIX_F2; break;
916 default: internal(file_line, "cgen_rot: invalid rotation %x", rot);
917 }
918 g(cgen_sse_insn(ctx, sse_prefix + force_vex, PREFIX_0F_38, X86_0F_38_ROTX, size == OP_SIZE_8, arg1[0], arg3[0], arg2));
919 return true;
920 }
922 if (arg1[0] != arg2[0])
923 internal(file_line, "cgen_rot: invalid arguments: %x, %02x, %02x, %02x", rot, arg1[0], arg2[0], arg3[0]);
925 if (arg3[0] == R_CX) {
926 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_ROT_RM8_CL : X86_ROT_RM16_CL, size, false, rot, arg1));
927 } else if (likely(arg3[0] == ARG_IMM)) {
928 int64_t imm;
929 imm = get_imm(&arg3[1]);
930 if (imm == 1) {
931 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_ROT_RM8_1 : X86_ROT_RM16_1, size, false, rot, arg1));
932 } else {
933 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_ROT_RM8_IMM8 : X86_ROT_RM16_IMM8, size, false, rot, arg1));
934 cgen_one(imm);
935 }
936 } else {
937 internal(file_line, "cgen_rot: invalid argument %02x", arg3[0]);
938 }
939 return true;
940 }
942 static bool attr_w cgen_btxt(struct codegen_context *ctx, unsigned size, uint8_t bt, uint8_t *arg1, uint8_t *arg2)
943 {
944 if (arg2[0] == ARG_IMM) {
945 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_BTX_RM16_IMM8, size, false, X86_0F_BTX_BT_RM16_IMM8 + bt, arg1));
946 cgen_one(arg2[1]);
947 } else {
948 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_BT_RM16_R16 + bt * 8, size, true, arg2[0], arg1));
949 }
950 return true;
951 }
953 static bool attr_w cgen_bt(struct codegen_context *ctx, unsigned size)
954 {
955 uint8_t *arg1 = ctx->code_position;
956 uint8_t *arg2 = arg1 + arg_size(*arg1);
957 ctx->code_position = arg2 + arg_size(*arg2);
959 return cgen_btxt(ctx, size, BTX_BT, arg1, arg2);
960 }
962 static bool attr_w cgen_btx(struct codegen_context *ctx, unsigned size, uint8_t bt)
963 {
964 uint8_t *arg1 = ctx->code_position;
965 uint8_t *arg2 = arg1 + arg_size(*arg1);
966 uint8_t *arg3 = arg2 + arg_size(*arg2);
967 ctx->code_position = arg3 + arg_size(*arg3);
969 if (arg1[0] != arg2[0])
970 internal(file_line, "cgen_btx: invalid arguments");
972 return cgen_btxt(ctx, size, bt, arg1, arg3);
973 }
975 static bool attr_w cgen_mul_l(struct codegen_context *ctx, unsigned size, bool sgn)
976 {
977 uint8_t *arg1, *arg2, *arg3, *arg4;
978 uint32_t reg_up;
979 arg1 = ctx->code_position;
980 arg2 = arg1 + arg_size(*arg1);
981 arg3 = arg2 + arg_size(*arg2);
982 arg4 = arg3 + arg_size(*arg3);
983 ctx->code_position = arg4 + arg_size(*arg4);
984 reg_up = size == OP_SIZE_1 ? R_AX : R_DX;
985 if (unlikely(arg1[0] != R_AX) || unlikely(arg2[0] != reg_up) || unlikely(arg3[0] != R_AX) || unlikely(arg4[0] == ARG_IMM))
986 internal(file_line, "cgen_mul_l: invalid mul arguments");
988 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_F6 : X86_F7, size, false, !sgn ? X86_F6_MUL_RM8 : X86_F6_IMUL_RM8, arg4));
989 return true;
990 }
992 static bool attr_w cgen_div_l(struct codegen_context *ctx, unsigned size, bool sgn)
993 {
994 uint8_t *arg1, *arg2, *arg3, *arg4, *arg5;
995 uint32_t reg_up;
996 arg1 = ctx->code_position;
997 arg2 = arg1 + arg_size(*arg1);
998 arg3 = arg2 + arg_size(*arg2);
999 arg4 = arg3 + arg_size(*arg3);
1000 arg5 = arg4 + arg_size(*arg4);
1001 ctx->code_position = arg5 + arg_size(*arg5);
1002 reg_up = size == OP_SIZE_1 ? R_AX : R_DX;
1003 if (unlikely(arg1[0] != R_AX) || unlikely(arg2[0] != reg_up) || unlikely(arg3[0] != R_AX) || unlikely(arg4[0] != reg_up) || unlikely(arg5[0] == ARG_IMM))
1004 internal(file_line, "cgen_div_l: invalid div arguments");
1006 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, size == OP_SIZE_1 ? X86_F6 : X86_F7, size, false, !sgn ? X86_F6_DIV_RM8 : X86_F6_IDIV_RM8, arg5));
1007 return true;
1008 }
1010 static bool attr_w cgen_cmov(struct codegen_context *ctx, unsigned size, unsigned cond)
1011 {
1012 uint8_t *arg1 = ctx->code_position;
1013 uint8_t *arg2 = arg1 + arg_size(*arg1);
1014 uint8_t *arg3 = arg2 + arg_size(*arg2);
1015 ctx->code_position = arg3 + arg_size(*arg3);
1016 if (unlikely(arg1[0] != arg2[0]))
1017 internal(file_line, "cgen_cmov: invalid arguments");
1018 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_CMOVCC_R16_RM16 + cond, size, true, arg1[0], arg3));
1019 return true;
1020 }
1022 static bool attr_w cgen_memcpy(struct codegen_context *ctx)
1023 {
1024 int64_t disp_dest, disp_src;
1025 uint8_t *arg1, *arg2, *arg3;
1026 arg1 = ctx->code_position;
1027 arg2 = arg1 + arg_size(*arg1);
1028 arg3 = arg2 + arg_size(*arg2);
1029 ctx->code_position = arg3 + arg_size(*arg3);
1030 if (unlikely(arg1[0] != ARG_ADDRESS_1_POST_I) || unlikely(arg2[0] != ARG_ADDRESS_1_POST_I) || unlikely(arg3[0] != R_CX))
1031 goto invl;
1032 if (unlikely(arg1[1] != R_DI) || unlikely(arg2[1] != R_SI))
1033 goto invl;
1034 disp_dest = get_imm(&arg1[2]);
1035 disp_src = get_imm(&arg2[2]);
1036 if (unlikely(disp_dest != 0) || unlikely(disp_src != 0))
1037 goto invl;
1039 cgen_one(X86_REPE);
1040 cgen_one(X86_MOVSB);
1041 return true;
1043 invl:
1044 internal(file_line, "cgen_memcpy: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1045 return false;
1046 }
1048 static bool attr_w cgen_memset(struct codegen_context *ctx)
1049 {
1050 int64_t disp_dest;
1051 uint8_t *arg1, *arg2, *arg3;
1052 arg1 = ctx->code_position;
1053 arg2 = arg1 + arg_size(*arg1);
1054 arg3 = arg2 + arg_size(*arg2);
1055 ctx->code_position = arg3 + arg_size(*arg3);
1056 if (unlikely(arg1[0] != ARG_ADDRESS_1_POST_I) || unlikely(arg2[0] != R_CX) || unlikely(arg3[0] != R_AX))
1057 goto invl;
1058 if (unlikely(arg1[1] != R_DI))
1059 goto invl;
1060 disp_dest = get_imm(&arg1[2]);
1061 if (unlikely(disp_dest != 0))
1062 goto invl;
1064 cgen_one(X86_REPE);
1065 cgen_one(X86_STOSB);
1066 return true;
1068 invl:
1069 internal(file_line, "cgen_memset: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1070 return false;
1071 }
1073 static bool attr_w cgen_sse_cmp(struct codegen_context *ctx, unsigned size)
1074 {
1075 uint8_t *arg1 = ctx->code_position;
1076 uint8_t *arg2 = arg1 + arg_size(*arg1);
1077 ctx->code_position = arg2 + arg_size(*arg2);
1078 g(cgen_sse_insn(ctx, size == OP_SIZE_4 ? SSE_PREFIX_NONE: SSE_PREFIX_66, PREFIX_0F, X86_0F_UCOMISS_X128_RM32, false, arg1[0], 0, arg2));
1079 return true;
1080 }
1082 static bool attr_w cgen_sse_alu(struct codegen_context *ctx, unsigned size, unsigned alu)
1083 {
1084 uint8_t opcode;
1085 uint8_t *arg1 = ctx->code_position;
1086 uint8_t *arg2 = arg1 + arg_size(*arg1);
1087 uint8_t *arg3 = arg2 + arg_size(*arg2);
1088 ctx->code_position = arg3 + arg_size(*arg3);
1089 switch (alu) {
1090 case FP_ALU_ADD: opcode = X86_0F_ADDPS_X128_M32; break;
1091 case FP_ALU_SUB: opcode = X86_0F_SUBPS_X128_M32; break;
1092 case FP_ALU_MUL: opcode = X86_0F_MULPS_X128_M32; break;
1093 case FP_ALU_DIV: opcode = X86_0F_DIVPS_X128_M32; break;
1094 default: internal(file_line, "cgen_sse_alu: invalid alu %u", alu);
1095 }
1096 g(cgen_sse_insn(ctx, size == OP_SIZE_4 ? SSE_PREFIX_F3 : SSE_PREFIX_F2, PREFIX_0F, opcode, false, arg1[0], arg2[0], arg3));
1097 return true;
1098 }
1100 static bool attr_w cgen_sse_alu1(struct codegen_context *ctx, unsigned size, unsigned alu)
1101 {
1102 uint8_t opcode;
1103 unsigned sse_pfx, sse_op_map;
1104 uint8_t *arg1 = ctx->code_position;
1105 uint8_t *arg2 = arg1 + arg_size(*arg1);
1106 ctx->code_position = arg2 + arg_size(*arg2);
1107 switch (alu) {
1108 case FP_ALU1_SQRT: if (size == OP_SIZE_4) {
1109 sse_pfx = SSE_PREFIX_F3;
1110 } else if (size == OP_SIZE_8) {
1111 sse_pfx = SSE_PREFIX_F2;
1112 } else {
1113 goto fail;
1114 }
1115 sse_op_map = PREFIX_0F;
1116 opcode = X86_0F_SQRTPS_X128_M32;
1117 break;
1118 case FP_ALU1_ROUND:
1119 case FP_ALU1_FLOOR:
1120 case FP_ALU1_CEIL:
1121 case FP_ALU1_TRUNC: sse_pfx = SSE_PREFIX_66;
1122 sse_op_map = PREFIX_0F_3A;
1123 if (size == OP_SIZE_4) {
1124 opcode = X86_0F_3A_ROUNDSS_X128_M32;
1125 } else if (size == OP_SIZE_8) {
1126 opcode = X86_0F_3A_ROUNDSD_X128_M64;
1127 } else {
1128 goto fail;
1129 }
1130 break;
1131 fail:
1132 default: internal(file_line, "cgen_sse_alu1: invalid alu %u, %u", alu, size);
1133 }
1134 g(cgen_sse_insn(ctx, sse_pfx, sse_op_map, opcode, false, arg1[0], arg1[0], arg2));
1135 if (OP_IS_ROUND(alu))
1136 cgen_one(alu - FP_ALU1_ROUND);
1137 return true;
1138 }
1140 static bool attr_w cgen_sse_from_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1141 {
1142 uint8_t *arg1 = ctx->code_position;
1143 uint8_t *arg2 = arg1 + arg_size(*arg1);
1144 ctx->code_position = arg2 + arg_size(*arg2);
1145 g(cgen_sse_insn(ctx, fp_op_size == OP_SIZE_4 ? SSE_PREFIX_F3 : SSE_PREFIX_F2, PREFIX_0F, X86_0F_CVTSI2SS_X128_RM32, int_op_size == OP_SIZE_8, arg1[0], R_XMM7, arg2));
1146 return true;
1147 }
1149 static bool attr_w cgen_sse_to_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1150 {
1151 uint8_t *arg1 = ctx->code_position;
1152 uint8_t *arg2 = arg1 + arg_size(*arg1);
1153 ctx->code_position = arg2 + arg_size(*arg2);
1154 g(cgen_sse_insn(ctx, fp_op_size == OP_SIZE_4 ? SSE_PREFIX_F3 : SSE_PREFIX_F2, PREFIX_0F, X86_0F_CVTTSS2SI_X128_RM32, int_op_size == OP_SIZE_8, arg1[0], 0, arg2));
1155 return true;
1156 }
1158 static bool attr_w cgen_sse_cvt(struct codegen_context *ctx, unsigned from_op_size, unsigned to_op_size)
1159 {
1160 uint8_t *arg1 = ctx->code_position;
1161 uint8_t *arg2 = arg1 + arg_size(*arg1);
1162 ctx->code_position = arg2 + arg_size(*arg2);
1163 if (from_op_size == OP_SIZE_2 && to_op_size == OP_SIZE_4) {
1164 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F_38, X86_0F_38_CVTPH2PS_X128_RM64, false, arg1[0], 0, arg2));
1165 return true;
1166 } else if (from_op_size == OP_SIZE_4 && to_op_size == OP_SIZE_2) {
1167 g(cgen_sse_insn(ctx, SSE_PREFIX_66, PREFIX_0F_3A, X86_0F_3A_CVTPS2PH_RM64_X128, false, arg2[0], 0, arg1));
1168 cgen_one(0x04);
1169 return true;
1170 }
1171 internal(file_line, "cgen_sse_cvt: unsupported arguments %u, %u", from_op_size, to_op_size);
1172 return false;
1173 }
1175 static bool attr_w cgen_x87_fld(struct codegen_context *ctx, unsigned size)
1176 {
1177 unsigned c1, c2;
1178 uint8_t *arg1 = ctx->code_position;
1179 ctx->code_position = arg1 + arg_size(*arg1);
1180 if (arg1[0] >= R_ST0 && arg1[0] <= R_ST7)
1181 size = OP_SIZE_4;
1182 switch (size) {
1183 case OP_SIZE_4:
1184 c1 = X87_FLD_RM32; c2 = X87_FLD_RM32_X; break;
1185 case OP_SIZE_8:
1186 c1 = X87_FLD_M64; c2 = X87_FLD_M64_X; break;
1187 case OP_SIZE_10:
1188 c1 = X87_FLD_M80; c2 = X87_FLD_M80_X; break;
1189 default:
1190 internal(file_line, "cgen_x87_fld: invalid size %u", size);
1191 }
1192 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1193 return true;
1194 }
1196 static bool attr_w cgen_x87_fild(struct codegen_context *ctx, unsigned size)
1197 {
1198 unsigned c1, c2;
1199 uint8_t *arg1 = ctx->code_position;
1200 ctx->code_position = arg1 + arg_size(*arg1);
1201 switch (size) {
1202 case OP_SIZE_2:
1203 c1 = X87_FILD_M16; c2 = X87_FILD_M16_X; break;
1204 case OP_SIZE_4:
1205 c1 = X87_FILD_M32; c2 = X87_FILD_M32_X; break;
1206 case OP_SIZE_8:
1207 c1 = X87_FILD_M64; c2 = X87_FILD_M64_X; break;
1208 default:
1209 internal(file_line, "cgen_x87_fild: invalid size %u", size);
1210 }
1211 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1212 return true;
1213 }
1215 static bool attr_w cgen_x87_fstp(struct codegen_context *ctx, unsigned size)
1216 {
1217 unsigned c1, c2;
1218 uint8_t *arg1 = ctx->code_position;
1219 ctx->code_position = arg1 + arg_size(*arg1);
1220 if (arg1[0] >= R_ST0 && arg1[0] <= R_ST7)
1221 size = OP_SIZE_8;
1222 switch (size) {
1223 case OP_SIZE_4:
1224 c1 = X87_FSTP_M32; c2 = X87_FSTP_M32_X; break;
1225 case OP_SIZE_8:
1226 c1 = X87_FSTP_RM64; c2 = X87_FSTP_RM64_X; break;
1227 case OP_SIZE_10:
1228 c1 = X87_FSTP_M80; c2 = X87_FSTP_M80_X; break;
1229 default:
1230 internal(file_line, "cgen_x87_fstp: invalid size %u", size);
1231 }
1232 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1233 return true;
1234 }
1236 static bool attr_w cgen_x87_fistp(struct codegen_context *ctx, unsigned size)
1237 {
1238 unsigned c1, c2;
1239 uint8_t *arg1 = ctx->code_position;
1240 ctx->code_position = arg1 + arg_size(*arg1);
1241 switch (size) {
1242 case OP_SIZE_2:
1243 c1 = X87_FISTP_M16; c2 = X87_FISTP_M16_X; break;
1244 case OP_SIZE_4:
1245 c1 = X87_FISTP_M32; c2 = X87_FISTP_M32_X; break;
1246 case OP_SIZE_8:
1247 c1 = X87_FISTP_M64; c2 = X87_FISTP_M64_X; break;
1248 default:
1249 internal(file_line, "cgen_x87_fistp: invalid size %u", size);
1250 }
1251 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1252 return true;
1253 }
1255 static bool attr_w cgen_x87_fisttp(struct codegen_context *ctx, unsigned size)
1256 {
1257 unsigned c1, c2;
1258 uint8_t *arg1 = ctx->code_position;
1259 ctx->code_position = arg1 + arg_size(*arg1);
1260 switch (size) {
1261 case OP_SIZE_2:
1262 c1 = X87_FISTTP_M16; c2 = X87_FISTTP_M16_X; break;
1263 case OP_SIZE_4:
1264 c1 = X87_FISTTP_M32; c2 = X87_FISTTP_M32_X; break;
1265 case OP_SIZE_8:
1266 c1 = X87_FISTTP_M64; c2 = X87_FISTTP_M64_X; break;
1267 default:
1268 internal(file_line, "cgen_x87_fisttp: invalid size %u", size);
1269 }
1270 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1271 return true;
1272 }
1274 static bool attr_w cgen_x87_fcomp(struct codegen_context *ctx, unsigned size)
1275 {
1276 unsigned c1, c2;
1277 uint8_t *arg1 = ctx->code_position;
1278 ctx->code_position = arg1 + arg_size(*arg1);
1279 if (arg1[0] < ARG_REGS_MAX) {
1280 c1 = X87_FALU_ST_RM32;
1281 } else switch (size) {
1282 case OP_SIZE_4:
1283 c1 = X87_FALU_ST_RM32; break;
1284 case OP_SIZE_8:
1285 c1 = X87_FALU_ST_M64; break;
1286 default:
1287 internal(file_line, "cgen_x87_fcomp: invalid size %u", size);
1288 }
1289 c2 = X87_ALU_FCOMP;
1290 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1291 return true;
1292 }
1294 static bool attr_w cgen_x87_alu(struct codegen_context *ctx, unsigned size, unsigned aux)
1295 {
1296 unsigned c1, c2;
1297 uint8_t *arg1 = ctx->code_position;
1298 ctx->code_position = arg1 + arg_size(*arg1);
1299 if (arg1[0] < ARG_REGS_MAX) {
1300 c1 = X87_FALU_ST_RM32;
1301 } else switch (size) {
1302 case OP_SIZE_4:
1303 c1 = X87_FALU_ST_RM32; break;
1304 case OP_SIZE_8:
1305 c1 = X87_FALU_ST_M64; break;
1306 default:
1307 internal(file_line, "cgen_x87_alu: invalid size %u", size);
1308 }
1309 switch (aux) {
1310 case FP_ALU_ADD:
1311 c2 = X87_ALU_ADD; break;
1312 case FP_ALU_SUB:
1313 c2 = X87_ALU_SUB; break;
1314 case FP_ALU_MUL:
1315 c2 = X87_ALU_MUL; break;
1316 case FP_ALU_DIV:
1317 c2 = X87_ALU_DIV; break;
1318 default:
1319 internal(file_line, "cgen_x87_fst: invalid operation %u", aux);
1320 }
1321 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, c1, OP_SIZE_4, false, c2, arg1));
1322 return true;
1323 }
1325 static bool attr_w cgen_x87_alup(struct codegen_context *ctx, unsigned aux)
1326 {
1327 unsigned c2;
1328 uint8_t *arg1 = ctx->code_position;
1329 ctx->code_position = arg1 + arg_size(*arg1);
1330 switch (aux) {
1331 case FP_ALU_ADD:
1332 c2 = X87_ALU_ADD; break;
1333 case FP_ALU_SUB:
1334 c2 = X87_ALU_SUB; break;
1335 case FP_ALU_MUL:
1336 c2 = X87_ALU_MUL; break;
1337 case FP_ALU_DIV:
1338 c2 = X87_ALU_DIV; break;
1339 default:
1340 internal(file_line, "cgen_x87_fstp: invalid operation %u", aux);
1341 }
1342 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X87_FALUP_STi_ST0, OP_SIZE_4, false, c2, arg1));
1343 return true;
1344 }
1346 static bool attr_w resolve_relocation(struct codegen_context *ctx, struct relocation *reloc)
1347 {
1348 int64_t offs = (int64_t)ctx->label_to_pos[reloc->label_id] - (int64_t)(reloc->position + (reloc->length == JMP_SHORT ? 1 : 4));
1349 switch (reloc->length) {
1350 case JMP_SHORT: {
1351 int8_t i8;
1352 if (!imm_is_8bit(offs))
1353 return false;
1354 i8 = offs;
1355 memcpy(ctx->mcode + reloc->position, &i8, 1);
1356 return true;
1357 }
1358 case JMP_LONG: {
1359 int32_t i32;
1360 if (!imm_is_32bit(offs))
1361 return false;
1362 i32 = offs;
1363 memcpy(ctx->mcode + reloc->position, &i32, 4);
1364 return true;
1365 }
1366 default: {
1367 internal(file_line, "resolve_relocation: invalid relocation length %u", reloc->length);
1368 return false;
1369 }
1370 }
1371 }
1373 static bool attr_w cgen_insn(struct codegen_context *ctx, uint32_t insn)
1374 {
1375 uint8_t imm8;
1376 uint16_t imm16;
1377 /*debug("insn: %08x", insn);*/
1378 switch (insn_opcode(insn)) {
1379 case INSN_ENTRY:
1380 g(cgen_entry(ctx));
1381 return true;
1382 case INSN_LABEL:
1383 g(cgen_label(ctx));
1384 return true;
1385 case INSN_RET:
1386 cgen_one(X86_RET);
1387 return true;
1388 case INSN_RET_IMM:
1389 imm16 = cget_two(ctx);
1390 cgen_one(X86_RET_IMM16);
1391 cgen_two(imm16);
1392 return true;
1393 case INSN_PUSH:
1394 g(cgen_push(ctx));
1395 return true;
1396 case INSN_POP:
1397 g(cgen_pop(ctx));
1398 return true;
1399 case INSN_CALL_INDIRECT:
1400 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_FF, OP_SIZE_4, false, X86_FF_CALL_INDIRECT, ctx->code_position));
1401 ctx->code_position += arg_size(*ctx->code_position);
1402 return true;
1403 case INSN_MOV:
1404 g(cgen_mov(ctx, insn_op_size(insn)));
1405 return true;
1406 case INSN_MOVSX:
1407 g(cgen_movsx(ctx, insn_op_size(insn)));
1408 return true;
1409 case INSN_CMP:
1410 g(cgen_alu(ctx, insn_op_size(insn), 7, insn_writes_flags(insn)));
1411 return true;
1412 case INSN_TEST:
1413 g(cgen_test(ctx, insn_op_size(insn)));
1414 return true;
1415 case INSN_ALU:
1416 case INSN_ALU_FLAGS:
1417 if (unlikely(insn_op_size(insn) < OP_SIZE_4))
1418 goto invalid_insn;
1419 if (!insn_writes_flags(insn) && insn_op_size(insn) <= OP_SIZE_8) {
1420 if (unlikely(insn_aux(insn) != ALU_ADD))
1421 goto invalid_insn;
1422 g(cgen_lea(ctx, insn_op_size(insn)));
1423 return true;
1424 }
1425 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1426 return true;
1427 case INSN_ALU_PARTIAL:
1428 case INSN_ALU_FLAGS_PARTIAL:
1429 if (unlikely(insn_op_size(insn) >= OP_SIZE_4))
1430 goto invalid_insn;
1431 if (!insn_writes_flags(insn)) {
1432 if (unlikely(insn_aux(insn) != ALU_ADD) || insn_op_size(insn) != OP_SIZE_2)
1433 goto invalid_insn;
1434 g(cgen_lea(ctx, insn_op_size(insn)));
1435 return true;
1436 }
1437 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1438 return true;
1439 case INSN_ALU1:
1440 case INSN_ALU1_FLAGS:
1441 if (unlikely(insn_op_size(insn) < OP_SIZE_4))
1442 goto invalid_insn;
1443 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn)));
1444 return true;
1445 case INSN_ALU1_PARTIAL:
1446 case INSN_ALU1_FLAGS_PARTIAL:
1447 if (unlikely(insn_op_size(insn) >= OP_SIZE_4))
1448 goto invalid_insn;
1449 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn)));
1450 return true;
1451 case INSN_LEA3:
1452 if (unlikely(insn_op_size(insn) < OP_SIZE_4))
1453 goto invalid_insn;
1454 g(cgen_lea3(ctx, insn_op_size(insn), insn_aux(insn)));
1455 return true;
1456 case INSN_ROT:
1457 if (unlikely(insn_op_size(insn) < OP_SIZE_4))
1458 goto invalid_insn;
1459 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1460 return true;
1461 case INSN_ROT_PARTIAL:
1462 if (unlikely(insn_op_size(insn) >= OP_SIZE_4))
1463 goto invalid_insn;
1464 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1465 return true;
1466 case INSN_BT:
1467 if (unlikely(insn_op_size(insn) == OP_SIZE_1) || unlikely(!insn_writes_flags(insn)))
1468 goto invalid_insn;
1469 g(cgen_bt(ctx, insn_op_size(insn)));
1470 return true;
1471 case INSN_BTX:
1472 if (unlikely(insn_op_size(insn) == OP_SIZE_1) || unlikely(!insn_writes_flags(insn)))
1473 goto invalid_insn;
1474 g(cgen_btx(ctx, insn_op_size(insn), insn_aux(insn)));
1475 return true;
1476 case INSN_MUL_L:
1477 g(cgen_mul_l(ctx, insn_op_size(insn), insn_aux(insn)));
1478 return true;
1479 case INSN_DIV_L:
1480 g(cgen_div_l(ctx, insn_op_size(insn), insn_aux(insn)));
1481 return true;
1482 case INSN_CBW:
1483 if (unlikely(insn_op_size(insn) <= OP_SIZE_2))
1484 goto invalid_insn;
1485 if (insn_op_size(insn) == OP_SIZE_8)
1486 cgen_rex(X86_REX | X86_REX_W);
1487 if (unlikely(cget_one(ctx) != R_AX))
1488 goto invalid_insn;
1489 if (unlikely(cget_one(ctx) != R_AX))
1490 goto invalid_insn;
1491 cgen_one(X86_CBW);
1492 return true;
1493 case INSN_CBW_PARTIAL:
1494 if (unlikely(insn_op_size(insn) != OP_SIZE_2))
1495 goto invalid_insn;
1496 if (unlikely(cget_one(ctx) != R_AX))
1497 goto invalid_insn;
1498 if (unlikely(cget_one(ctx) != R_AX))
1499 goto invalid_insn;
1500 cgen_one(X86_OP_SIZE);
1501 cgen_one(X86_CBW);
1502 return true;
1503 case INSN_CWD:
1504 if (unlikely(insn_op_size(insn) <= OP_SIZE_2))
1505 goto invalid_insn;
1506 if (unlikely(cget_one(ctx) != R_DX))
1507 goto invalid_insn;
1508 if (unlikely(cget_one(ctx) != R_AX))
1509 goto invalid_insn;
1510 if (insn_op_size(insn) == OP_SIZE_8)
1511 cgen_rex(X86_REX | X86_REX_W);
1512 cgen_one(X86_CWD);
1513 return true;
1514 case INSN_CWD_PARTIAL:
1515 if (unlikely(insn_op_size(insn) != OP_SIZE_2))
1516 goto invalid_insn;
1517 if (unlikely(cget_one(ctx) != R_DX))
1518 goto invalid_insn;
1519 if (unlikely(cget_one(ctx) != R_AX))
1520 goto invalid_insn;
1521 if (unlikely(cget_one(ctx) != R_DX))
1522 goto invalid_insn;
1523 cgen_one(X86_OP_SIZE);
1524 cgen_one(X86_CWD);
1525 return true;
1526 case INSN_SET_COND:
1527 if (unlikely(insn_op_size(insn) != OP_SIZE_1))
1528 goto invalid_insn;
1529 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_SETCC_RM8 + (insn_aux(insn) & 0xf), OP_SIZE_1, false, 0, ctx->code_position));
1530 ctx->code_position += arg_size(*ctx->code_position);
1531 return true;
1532 case INSN_SET_COND_PARTIAL:
1533 if (unlikely(insn_op_size(insn) != OP_SIZE_1))
1534 goto invalid_insn;
1535 g(cgen_rm_insn(ctx, -1, PREFIX_0F, X86_0F_SETCC_RM8 + (insn_aux(insn) & 0xf), OP_SIZE_1, false, 0, ctx->code_position));
1536 ctx->code_position += arg_size(*ctx->code_position);
1537 ctx->code_position += arg_size(*ctx->code_position);
1538 return true;
1539 case INSN_CMOV:
1540 case INSN_CMOV_XCC:
1541 if (unlikely(insn_op_size(insn) == OP_SIZE_1))
1542 goto invalid_insn;
1543 g(cgen_cmov(ctx, insn_op_size(insn), insn_aux(insn)));
1544 return true;
1545 case INSN_MEMCPY:
1546 g(cgen_memcpy(ctx));
1547 return true;
1548 case INSN_MEMSET:
1549 g(cgen_memset(ctx));
1550 return true;
1551 case INSN_FP_CMP:
1552 g(cgen_sse_cmp(ctx, insn_op_size(insn)));
1553 return true;
1554 case INSN_FP_ALU:
1555 g(cgen_sse_alu(ctx, insn_op_size(insn), insn_aux(insn)));
1556 return true;
1557 case INSN_FP_ALU1:
1558 g(cgen_sse_alu1(ctx, insn_op_size(insn), insn_aux(insn)));
1559 return true;
1560 case INSN_FP_FROM_INT32:
1561 case INSN_FP_FROM_INT64:
1562 g(cgen_sse_from_int(ctx, insn_opcode(insn) == INSN_FP_FROM_INT32 ? OP_SIZE_4 : OP_SIZE_8, insn_op_size(insn)));
1563 return true;
1564 case INSN_FP_TO_INT32:
1565 case INSN_FP_TO_INT64:
1566 g(cgen_sse_to_int(ctx, insn_opcode(insn) == INSN_FP_TO_INT32 ? OP_SIZE_4 : OP_SIZE_8, insn_op_size(insn)));
1567 return true;
1568 case INSN_FP_CVT:
1569 g(cgen_sse_cvt(ctx, insn_op_size(insn), insn_aux(insn)));
1570 return true;
1571 case INSN_X87_FLD:
1572 g(cgen_x87_fld(ctx, insn_op_size(insn)));
1573 return true;
1574 case INSN_X87_FILD:
1575 g(cgen_x87_fild(ctx, insn_op_size(insn)));
1576 return true;
1577 case INSN_X87_FSTP:
1578 g(cgen_x87_fstp(ctx, insn_op_size(insn)));
1579 return true;
1580 case INSN_X87_FISTP:
1581 g(cgen_x87_fistp(ctx, insn_op_size(insn)));
1582 return true;
1583 case INSN_X87_FISTTP:
1584 g(cgen_x87_fisttp(ctx, insn_op_size(insn)));
1585 return true;
1586 case INSN_X87_FCOMP:
1587 g(cgen_x87_fcomp(ctx, insn_op_size(insn)));
1588 return true;
1589 case INSN_X87_FCOMPP:
1590 cgen_one(X87_FCOMPP);
1591 cgen_one(X87_FCOMPP_2);
1592 return true;
1593 case INSN_X87_FCOMIP:
1594 imm8 = cget_one(ctx);
1595 cgen_one(X87_FCOMIP);
1596 cgen_one(X87_FCOMIP_2 + (imm8 & 7));
1597 return true;
1598 case INSN_X87_ALU:
1599 g(cgen_x87_alu(ctx, insn_op_size(insn), insn_aux(insn)));
1600 return true;
1601 case INSN_X87_ALUP:
1602 g(cgen_x87_alup(ctx, insn_aux(insn)));
1603 return true;
1604 case INSN_X87_FCHS:
1605 cgen_one(X87_FCHS);
1606 cgen_one(X87_FCHS_2);
1607 return true;
1608 case INSN_X87_FSQRT:
1609 cgen_one(X87_FSQRT);
1610 cgen_one(X87_FSQRT_2);
1611 return true;
1612 case INSN_X87_FRNDINT:
1613 cgen_one(X87_FRNDINT);
1614 cgen_one(X87_FRNDINT_2);
1615 return true;
1616 case INSN_X87_FNSTSW:
1617 if (unlikely(cget_one(ctx) != R_AX))
1618 goto invalid_insn;
1619 if (unlikely(cget_one(ctx) != R_AX))
1620 goto invalid_insn;
1621 cgen_one(X87_FNSTSW);
1622 cgen_one(X87_FNSTSW_2);
1623 return true;
1624 case INSN_X87_FLDCW:
1625 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X87_FLDCW, OP_SIZE_4, false, X87_FLDCW_X, ctx->code_position));
1626 ctx->code_position += arg_size(*ctx->code_position);
1627 return true;
1628 case INSN_JMP:
1629 if (insn_jump_size(insn) == JMP_SHORT || insn_jump_size(insn) == JMP_SHORTEST) {
1630 cgen_one(X86_JMP_8);
1631 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1632 cgen_one(0);
1633 } else if (likely(insn_jump_size(insn) == JMP_LONG)) {
1634 cgen_one(X86_JMP_16);
1635 g(add_relocation(ctx, JMP_LONG, 0, NULL));
1636 cgen_four(0);
1637 } else {
1638 goto invalid_insn;
1639 }
1640 return true;
1641 case INSN_JMP_COND:
1642 if (insn_jump_size(insn) == JMP_SHORT || insn_jump_size(insn) == JMP_SHORTEST) {
1643 cgen_one(X86_JCC_8 + (insn_aux(insn) & 0xf));
1644 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1645 cgen_one(0);
1646 } else if (likely(insn_jump_size(insn) == JMP_LONG)) {
1647 cgen_one(X86_0F);
1648 cgen_one(X86_0F_JCC_16 + (insn_aux(insn) & 0xf));
1649 g(add_relocation(ctx, JMP_LONG, 0, NULL));
1650 cgen_four(0);
1651 } else {
1652 goto invalid_insn;
1653 }
1654 return true;
1655 case INSN_JMP_INDIRECT:
1656 g(cgen_rm_insn(ctx, -1, PREFIX_NONE, X86_FF, OP_SIZE_4, false, X86_FF_JMP_INDIRECT, ctx->code_position));
1657 ctx->code_position += arg_size(*ctx->code_position);
1658 return true;
1659 default:
1660 invalid_insn:
1661 internal(file_line, "cgen_insn: invalid insn %08lx", (unsigned long)insn);
1662 return false;
1663 }
1664 }