c1-alpha.inc

   1 /*
   2  * Copyright (C) 2024 Mikulas Patocka
   3  *
   4  * This file is part of Ajla.
   5  *
   6  * Ajla is free software: you can redistribute it and/or modify it under the
   7  * terms of the GNU General Public License as published by the Free Software
   8  * Foundation, either version 3 of the License, or (at your option) any later
   9  * version.
  10  *
  11  * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
  12  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * Ajla. If not, see <https://www.gnu.org/licenses/>.
  17  */
  18
  19 #define OP_SIZE_NATIVE                  OP_SIZE_8
  20 #define OP_SIZE_ADDRESS                 OP_SIZE_NATIVE
  21
  22 #define JMP_LIMIT                       JMP_SHORTEST
  23
  24 #define UNALIGNED_TRAP                  1
  25
  26 #define ALU_WRITES_FLAGS(alu, im)       0
  27 #define ALU1_WRITES_FLAGS(alu)          0
  28 #define ROT_WRITES_FLAGS(alu, size, im) 0
  29 #define COND_IS_LOGICAL(cond)           0
  30
  31 #define ARCH_PARTIAL_ALU(size)          0
  32 #define ARCH_IS_3ADDRESS(alu, f)        1
  33 #define ARCH_IS_3ADDRESS_IMM(alu, f)    1
  34 #define ARCH_IS_3ADDRESS_ROT(alu, size) 1
  35 #define ARCH_IS_3ADDRESS_ROT_IMM(alu)   1
  36 #define ARCH_IS_2ADDRESS(alu)           1
  37 #define ARCH_IS_3ADDRESS_FP             1
  38 #define ARCH_HAS_FLAGS                  0
  39 #define ARCH_SUPPORTS_TRAPS             OS_SUPPORTS_TRAPS
  40 #define ARCH_TRAP_BEFORE                0
  41 #define ARCH_PREFERS_SX(size)           ((size) == OP_SIZE_4)
  42 #define ARCH_HAS_BWX                    cpu_test_feature(CPU_FEATURE_bwx)
  43 #define ARCH_HAS_MUL                    1
  44 #define ARCH_HAS_DIV                    0
  45 #define ARCH_HAS_ANDN                   1
  46 #define ARCH_HAS_SHIFTED_ADD(bits)      ((bits) == 0 || (bits) == 2 || (bits) == 3)
  47 #define ARCH_HAS_BTX(btx, size, cnst)   0
  48 #define ARCH_SHIFT_SIZE                 OP_SIZE_8
  49 #define ARCH_NEEDS_BARRIER              thread_needs_barriers
  50
  51 #define i_size(size)                    OP_SIZE_NATIVE
  52 #define i_size_rot(size)                OP_SIZE_NATIVE
  53 #define i_size_cmp(size)                OP_SIZE_NATIVE
  54
  55 /*#define TIMESTAMP_IN_REGISTER*/
  56
  57 #define R_V0            0x00
  58 #define R_T0            0x01
  59 #define R_T1            0x02
  60 #define R_T2            0x03
  61 #define R_T3            0x04
  62 #define R_T4            0x05
  63 #define R_T5            0x06
  64 #define R_T6            0x07
  65 #define R_T7            0x08
  66 #define R_S0            0x09
  67 #define R_S1            0x0a
  68 #define R_S2            0x0b
  69 #define R_S3            0x0c
  70 #define R_S4            0x0d
  71 #define R_S5            0x0e
  72 #define R_FP            0x0f
  73 #define R_A0            0x10
  74 #define R_A1            0x11
  75 #define R_A2            0x12
  76 #define R_A3            0x13
  77 #define R_A4            0x14
  78 #define R_A5            0x15
  79 #define R_T8            0x16
  80 #define R_T9            0x17
  81 #define R_T10           0x18
  82 #define R_T11           0x19
  83 #define R_RA            0x1a
  84 #define R_T12           0x1b
  85 #define R_AT            0x1c
  86 #define R_GP            0x1d
  87 #define R_SP            0x1e
  88 #define R_ZERO          0x1f
  89
  90 #define R_F0            0x20
  91 #define R_F1            0x21
  92 #define R_F2            0x22
  93 #define R_F3            0x23
  94 #define R_F4            0x24
  95 #define R_F5            0x25
  96 #define R_F6            0x26
  97 #define R_F7            0x27
  98 #define R_F8            0x28
  99 #define R_F9            0x29
 100 #define R_F10           0x2a
 101 #define R_F11           0x2b
 102 #define R_F12           0x2c
 103 #define R_F13           0x2d
 104 #define R_F14           0x2e
 105 #define R_F15           0x2f
 106 #define R_F16           0x30
 107 #define R_F17           0x31
 108 #define R_F18           0x32
 109 #define R_F19           0x33
 110 #define R_F20           0x34
 111 #define R_F21           0x35
 112 #define R_F22           0x36
 113 #define R_F23           0x37
 114 #define R_F24           0x38
 115 #define R_F25           0x39
 116 #define R_F26           0x3a
 117 #define R_F27           0x3b
 118 #define R_F28           0x3c
 119 #define R_F29           0x3d
 120 #define R_F30           0x3e
 121 #define R_FZERO         0x3f
 122
 123 #define R_FRAME         R_S0
 124 #define R_UPCALL        R_S1
 125 #ifdef TIMESTAMP_IN_REGISTER
 126 #define R_TIMESTAMP     R_S2
 127 #endif
 128
 129 #define R_SCRATCH_1     R_A0
 130 #define R_SCRATCH_2     R_A1
 131 #define R_SCRATCH_3     R_A2
 132 #define R_SCRATCH_4     R_A3
 133 #define R_SCRATCH_NA_1  R_T0
 134 #define R_SCRATCH_NA_2  R_T1
 135 #define R_SCRATCH_NA_3  R_T2
 136
 137 #define R_SAVED_1       R_S3
 138 #define R_SAVED_2       R_S4
 139
 140 #define R_ARG0          R_A0
 141 #define R_ARG1          R_A1
 142 #define R_ARG2          R_A2
 143 #define R_ARG3          R_A3
 144 #define R_ARG4          R_A4
 145 #define R_RET0          R_V0
 146
 147 #define R_OFFSET_IMM    R_T3
 148 #define R_CONST_IMM     R_T4
 149 #define R_CMP_RESULT    R_T5
 150
 151 #define FR_SCRATCH_1    R_F0
 152 #define FR_SCRATCH_2    R_F1
 153 #define FR_SCRATCH_3    R_F10
 154
 155 #define SUPPORTED_FP    0x6
 156
 157 #define FRAME_SIZE      0x50
 158
 159 static bool reg_is_fp(unsigned reg)
 160 {
 161         return reg >= 0x20 && reg < 0x40;
 162 }
 163
 164 static const uint8_t regs_saved[] = {
 165 #ifndef TIMESTAMP_IN_REGISTER
 166         R_S2,
 167 #endif
 168         R_S5, R_FP };
 169 static const uint8_t regs_volatile[] = { R_T6, R_T7, R_A4, R_A5, R_T8, R_T9, R_T10, R_T11, R_RA, R_T12, R_AT, R_GP };
 170 static const uint8_t fp_saved[] = { 0 };
 171 #define n_fp_saved 0U
 172 static const uint8_t fp_volatile[] = { R_F11, R_F12, R_F13, R_F14, R_F15, R_F16, R_F17, R_F18, R_F19, R_F20, R_F21, R_F22, R_F23, R_F24, R_F25, R_F26, R_F27, R_F28, R_F29, R_F30 };
 173 #define reg_is_saved(r) (((r) >= R_S0 && (r) <= R_FP) || ((r) >= R_F2 && (r) <= R_F9))
 174
 175 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
 176 {
 177         unsigned r = R_ZERO;
 178         int16_t c1, c2, c3, c4;
 179         c1 = (int16_t)c;
 180         c &= ~0xffffUL;
 181         if (c1 < 0)
 182                 c += 0x10000UL;
 183         c2 = (int16_t)(c >> 16);
 184         c &= ~0xffffffffUL;
 185         if (c2 < 0)
 186                 c += 0x100000000UL;
 187         c3 = (int16_t)(c >> 32);
 188         c &= ~0xffffffffffffUL;
 189         if (c3 < 0)
 190                 c += 0x1000000000000UL;
 191         c4 = (int16_t)(c >> 48);
 192         if (c4) {
 193                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 194                 gen_one(reg);
 195                 gen_one(R_ZERO);
 196                 gen_one(ARG_IMM);
 197                 gen_eight((uint64_t)c4 << 16);
 198                 r = reg;
 199         }
 200         if (c3) {
 201                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 202                 gen_one(reg);
 203                 gen_one(r);
 204                 gen_one(ARG_IMM);
 205                 gen_eight(c3);
 206                 r = reg;
 207         }
 208         if (r != R_ZERO) {
 209                 gen_insn(INSN_ROT, OP_SIZE_NATIVE, ROT_SHL, 0);
 210                 gen_one(reg);
 211                 gen_one(reg);
 212                 gen_one(ARG_IMM);
 213                 gen_eight(32);
 214         }
 215         if (c2) {
 216                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 217                 gen_one(reg);
 218                 gen_one(r);
 219                 gen_one(ARG_IMM);
 220                 gen_eight((uint64_t)c2 << 16);
 221                 r = reg;
 222         }
 223         if (c1 || r == R_ZERO) {
 224                 gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 225                 gen_one(reg);
 226                 gen_one(r);
 227                 gen_one(ARG_IMM);
 228                 gen_eight(c1);
 229         }
 230         return true;
 231 }
 232
 233 static bool attr_w gen_address(struct codegen_context *ctx, unsigned base, int64_t imm, unsigned purpose, unsigned size)
 234 {
 235         ctx->base_reg = base;
 236         ctx->offset_imm = imm;
 237         ctx->offset_reg = false;
 238         switch (purpose) {
 239                 case IMM_PURPOSE_LDR_OFFSET:
 240                 case IMM_PURPOSE_LDR_SX_OFFSET:
 241                 case IMM_PURPOSE_STR_OFFSET:
 242                 case IMM_PURPOSE_VLDR_VSTR_OFFSET:
 243                 case IMM_PURPOSE_MVI_CLI_OFFSET:
 244                         if (likely(imm >= -0x8000) && likely(imm < 0x8000))
 245                                 return true;
 246                         break;
 247                 default:
 248                         internal(file_line, "gen_address: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 249         }
 250         g(gen_load_constant(ctx, R_OFFSET_IMM, imm));
 251         gen_insn(INSN_ALU, OP_SIZE_ADDRESS, ALU_ADD, 0);
 252         gen_one(R_OFFSET_IMM);
 253         gen_one(R_OFFSET_IMM);
 254         gen_one(base);
 255         ctx->base_reg = R_OFFSET_IMM;
 256         ctx->offset_imm = 0;
 257         return true;
 258 }
 259
 260 static bool is_direct_const(int64_t imm, unsigned purpose, unsigned size)
 261 {
 262         int64_t imm_copy = imm;
 263         switch (purpose) {
 264                 case IMM_PURPOSE_STORE_VALUE:
 265                         if (!imm)
 266                                 return true;
 267                         break;
 268                 case IMM_PURPOSE_SUB:
 269                         imm_copy = -(uint64_t)imm_copy;
 270                         /*-fallthrough*/
 271                 case IMM_PURPOSE_ADD:
 272                         if (likely(imm_copy >= -0x8000) && likely(imm_copy < 0x8000))
 273                                 return true;
 274                         if (imm_copy & 0xffff)
 275                                 break;
 276                         if (likely(imm_copy >= -0x80000000L) && likely(imm_copy < 0x80000000L))
 277                                 return true;
 278                         break;
 279                 case IMM_PURPOSE_CMP:
 280                 case IMM_PURPOSE_CMP_LOGICAL:
 281                 case IMM_PURPOSE_AND:
 282                 case IMM_PURPOSE_OR:
 283                 case IMM_PURPOSE_XOR:
 284                 case IMM_PURPOSE_ANDN:
 285                 case IMM_PURPOSE_TEST:
 286                 case IMM_PURPOSE_MUL:
 287                 case IMM_PURPOSE_MOVR:
 288                         if (imm >= 0 && imm < 256)
 289                                 return true;
 290                         break;
 291                 default:
 292                         internal(file_line, "is_direct_const: invalid purpose %u (imm %"PRIxMAX", size %u)", purpose, (uintmax_t)imm, size);
 293         }
 294         return false;
 295 }
 296
 297 static bool attr_w gen_imm(struct codegen_context *ctx, int64_t imm, unsigned purpose, unsigned size)
 298 {
 299         if (is_direct_const(imm, purpose, size)) {
 300                 ctx->const_imm = imm;
 301                 ctx->const_reg = false;
 302         } else {
 303                 g(gen_load_constant(ctx, R_CONST_IMM, imm));
 304                 ctx->const_reg = true;
 305         }
 306         return true;
 307 }
 308
 309 static bool attr_w gen_entry(struct codegen_context *ctx)
 310 {
 311         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_SUB, OP_SIZE_NATIVE));
 312         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_SUB, 0);
 313         gen_one(R_SP);
 314         gen_one(R_SP);
 315         gen_imm_offset();
 316
 317         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 318         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 319         gen_address_offset();
 320         gen_one(R_RA);
 321
 322 #ifndef TIMESTAMP_IN_REGISTER
 323         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_STR_OFFSET, OP_SIZE_4));
 324         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 325         gen_address_offset();
 326         gen_one(R_ARG3);
 327 #endif
 328
 329         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 330         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 331         gen_address_offset();
 332         gen_one(R_S0);
 333
 334         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 335         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 336         gen_address_offset();
 337         gen_one(R_S1);
 338
 339         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 340         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 341         gen_address_offset();
 342         gen_one(R_S2);
 343
 344         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 345         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 346         gen_address_offset();
 347         gen_one(R_S3);
 348
 349         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 350         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 351         gen_address_offset();
 352         gen_one(R_S4);
 353
 354         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 355         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 356         gen_address_offset();
 357         gen_one(R_S5);
 358
 359         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 360         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 361         gen_address_offset();
 362         gen_one(R_FP);
 363
 364         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_STR_OFFSET, OP_SIZE_NATIVE));
 365         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 366         gen_address_offset();
 367         gen_one(R_ARG0);
 368
 369         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 370         gen_one(R_FRAME);
 371         gen_one(R_ARG1);
 372
 373         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 374         gen_one(R_UPCALL);
 375         gen_one(R_ARG2);
 376
 377 #ifdef TIMESTAMP_IN_REGISTER
 378         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 379         gen_one(R_TIMESTAMP);
 380         gen_one(R_ARG3);
 381 #endif
 382
 383         gen_insn(INSN_JMP_INDIRECT, 0, 0, 0);
 384         gen_one(R_ARG4);
 385
 386         return true;
 387 }
 388
 389 static bool attr_w gen_escape_arg(struct codegen_context *ctx, ip_t ip, uint32_t escape_label)
 390 {
 391         g(gen_load_constant(ctx, R_SCRATCH_1, (int32_t)ip));
 392
 393         gen_insn(INSN_JMP, 0, 0, 0);
 394         gen_four(escape_label);
 395
 396         return true;
 397 }
 398
 399 static bool attr_w gen_escape(struct codegen_context *ctx)
 400 {
 401         g(gen_address(ctx, R_SP, 72, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 402         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 403         gen_one(R_RET0);
 404         gen_address_offset();
 405
 406         g(gen_address(ctx, R_RET0, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 407         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 408         gen_address_offset();
 409         gen_one(R_FRAME);
 410
 411         g(gen_address(ctx, R_RET0, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 412         gen_insn(INSN_MOV, OP_SIZE_4, 0, 0);
 413         gen_address_offset();
 414         gen_one(R_SCRATCH_1);
 415
 416         g(gen_address(ctx, R_SP, 0, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 417         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 418         gen_one(R_RA);
 419         gen_address_offset();
 420
 421         g(gen_address(ctx, R_SP, 16, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 422         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 423         gen_one(R_S0);
 424         gen_address_offset();
 425
 426         g(gen_address(ctx, R_SP, 24, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 427         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 428         gen_one(R_S1);
 429         gen_address_offset();
 430
 431         g(gen_address(ctx, R_SP, 32, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 432         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 433         gen_one(R_S2);
 434         gen_address_offset();
 435
 436         g(gen_address(ctx, R_SP, 40, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 437         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 438         gen_one(R_S3);
 439         gen_address_offset();
 440
 441         g(gen_address(ctx, R_SP, 48, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 442         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 443         gen_one(R_S4);
 444         gen_address_offset();
 445
 446         g(gen_address(ctx, R_SP, 56, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 447         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 448         gen_one(R_S5);
 449         gen_address_offset();
 450
 451         g(gen_address(ctx, R_SP, 64, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 452         gen_insn(INSN_MOV, OP_SIZE_NATIVE, 0, 0);
 453         gen_one(R_FP);
 454         gen_address_offset();
 455
 456         g(gen_imm(ctx, FRAME_SIZE, IMM_PURPOSE_ADD, OP_SIZE_NATIVE));
 457         gen_insn(INSN_ALU, OP_SIZE_NATIVE, ALU_ADD, 0);
 458         gen_one(R_SP);
 459         gen_one(R_SP);
 460         gen_imm_offset();
 461
 462         gen_insn(INSN_RET, 0, 0, 0);
 463
 464         return true;
 465 }
 466
 467 static bool attr_w gen_upcall_argument(struct codegen_context attr_unused *ctx, unsigned attr_unused arg)
 468 {
 469         return true;
 470 }
 471
 472 static bool attr_w gen_upcall(struct codegen_context *ctx, unsigned offset, unsigned n_args)
 473 {
 474         g(gen_address(ctx, R_UPCALL, offset, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_NATIVE));
 475         gen_insn(INSN_MOV, OP_SIZE_ADDRESS, 0, 0);
 476         gen_one(R_T12);
 477         gen_address_offset();
 478
 479         gen_insn(INSN_CALL_INDIRECT, OP_SIZE_ADDRESS, 0, 0);
 480         gen_one(R_T12);
 481
 482         g(gen_upcall_end(ctx, n_args));
 483
 484         return true;
 485 }
 486
 487 static bool attr_w gen_cmp_test_jmp(struct codegen_context *ctx, unsigned insn, unsigned op_size, unsigned reg1, unsigned reg2, unsigned cond, uint32_t label);
 488
 489 static bool attr_w gen_timestamp_test(struct codegen_context *ctx, uint32_t escape_label)
 490 {
 491         g(gen_address(ctx, R_UPCALL, offsetof(struct cg_upcall_vector_s, ts), IMM_PURPOSE_LDR_SX_OFFSET, OP_SIZE_4));
 492         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 493         gen_one(R_SCRATCH_1);
 494         gen_address_offset();
 495
 496 #ifdef TIMESTAMP_IN_REGISTER
 497         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_TIMESTAMP, COND_NE, escape_label));
 498 #else
 499         g(gen_address(ctx, R_SP, 8, IMM_PURPOSE_LDR_OFFSET, OP_SIZE_4));
 500         gen_insn(INSN_MOVSX, OP_SIZE_4, 0, 0);
 501         gen_one(R_SCRATCH_2);
 502         gen_address_offset();
 503
 504         g(gen_cmp_test_jmp(ctx, INSN_CMP, OP_SIZE_NATIVE, R_SCRATCH_1, R_SCRATCH_2, COND_NE, escape_label));
 505 #endif
 506         return true;
 507 }