| blob | 26cc043ace9e76a589affae2fb8e41e6454eeb09 |
1 /*
2 * Copyright (C) 2024 Mikulas Patocka
3 *
4 * This file is part of Ajla.
5 *
6 * Ajla is free software: you can redistribute it and/or modify it under the
7 * terms of the GNU General Public License as published by the Free Software
8 * Foundation, either version 3 of the License, or (at your option) any later
9 * version.
10 *
11 * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * Ajla. If not, see <https://www.gnu.org/licenses/>.
17 */
19 typedef uint64_t it;
21 #define USE_BRCL Z
23 #define S390_BCR 0x070000000000ULL
24 #define S390_BASR 0x0d0000000000ULL
26 #define S390_LTR 0x120000000000ULL
27 #define S390_LTGR 0xb90200000000ULL
29 #define S390_LCR 0x130000000000ULL
30 #define S390_LCGR 0xb90300000000ULL
32 #define S390_NR 0x140000000000ULL
33 #define S390_NRK 0xb9f400000000ULL
34 #define S390_N 0x540000000000ULL
35 #define S390_NY 0xe30000000054ULL
36 #define S390_NGR 0xb98000000000ULL
37 #define S390_NGRK 0xb9e400000000ULL
38 #define S390_NG 0xe30000000080ULL
39 #define S390_NILL 0xa50700000000ULL
40 #define S390_NILH 0xa50600000000ULL
41 #define S390_NIHL 0xa50500000000ULL
42 #define S390_NIHH 0xa50400000000ULL
43 #define S390_NILF 0xc00b00000000ULL
44 #define S390_NIHF 0xc00a00000000ULL
46 #define S390_CLR 0x150000000000ULL
47 #define S390_CL 0x550000000000ULL
48 #define S390_CLY 0xe30000000055ULL
49 #define S390_CLGR 0xb92100000000ULL
50 #define S390_CLG 0xe30000000021ULL
51 #define S390_CGFI 0xc20c00000000ULL
52 #define S390_CFI 0xc20d00000000ULL
53 #define S390_CLGFI 0xc20e00000000ULL
54 #define S390_CLFI 0xc20f00000000ULL
56 #define S390_OR 0x160000000000ULL
57 #define S390_ORK 0xb9f600000000ULL
58 #define S390_O 0x560000000000ULL
59 #define S390_OY 0xe30000000056ULL
60 #define S390_OGR 0xb98100000000ULL
61 #define S390_OGRK 0xb9e600000000ULL
62 #define S390_OG 0xe30000000081ULL
63 #define S390_OILL 0xa50b00000000ULL
64 #define S390_OILH 0xa50a00000000ULL
65 #define S390_OIHL 0xa50900000000ULL
66 #define S390_OIHH 0xa50800000000ULL
67 #define S390_OILF 0xc00d00000000ULL
68 #define S390_OIHF 0xc00c00000000ULL
70 #define S390_XR 0x170000000000ULL
71 #define S390_XRK 0xb9f700000000ULL
72 #define S390_X 0x570000000000ULL
73 #define S390_XY 0xe30000000057ULL
74 #define S390_XGR 0xb98200000000ULL
75 #define S390_XGRK 0xb9e700000000ULL
76 #define S390_XG 0xe30000000082ULL
77 #define S390_XILF 0xc00700000000ULL
78 #define S390_XIHF 0xc00600000000ULL
80 #define S390_LR 0x180000000000ULL
81 #define S390_L 0x580000000000ULL
82 #define S390_LY 0xe30000000058ULL
83 #define S390_LGR 0xb90400000000ULL
84 #define S390_LG 0xe30000000004ULL
85 #define S390_LHI 0xa70800000000ULL
86 #define S390_LGHI 0xa70900000000ULL
87 #define S390_LGFI 0xc00100000000ULL
88 #define S390_LGFR 0xb91400000000ULL
89 #define S390_LLGCR 0xb98400000000ULL
90 #define S390_LLGC 0xe30000000090ULL
91 #define S390_LLGHR 0xb98500000000ULL
92 #define S390_LLGH 0xe30000000091ULL
93 #define S390_LLGFR 0xb91600000000ULL
94 #define S390_LBR 0xb92600000000ULL
95 #define S390_LB 0xe30000000076ULL
96 #define S390_LGBR 0xb90600000000ULL
97 #define S390_LGB 0xe30000000077ULL
99 #define S390_CR 0x190000000000ULL
100 #define S390_C 0x590000000000ULL
101 #define S390_CY 0xe30000000059ULL
102 #define S390_CGR 0xb92000000000ULL
103 #define S390_CG 0xe30000000020ULL
104 #define S390_CHI 0xa70e00000000ULL
105 #define S390_CGHI 0xa70f00000000ULL
107 #define S390_AR 0x1a0000000000ULL
108 #define S390_ARK 0xb9f800000000ULL
109 #define S390_A 0x5a0000000000ULL
110 #define S390_AY 0xe3000000005aULL
111 #define S390_AGR 0xb90800000000ULL
112 #define S390_AGRK 0xb9e800000000ULL
113 #define S390_AG 0xe30000000008ULL
114 #define S390_AHI 0xa70a00000000ULL
115 #define S390_AGHI 0xa70b00000000ULL
116 #define S390_AGF 0xe30000000018ULL
118 #define S390_SR 0x1b0000000000ULL
119 #define S390_SRK 0xb9f900000000ULL
120 #define S390_S 0x5b0000000000ULL
121 #define S390_SY 0xe3000000005bULL
122 #define S390_SGR 0xb90900000000ULL
123 #define S390_SGRK 0xb9e900000000ULL
124 #define S390_SG 0xe30000000009ULL
126 #define S390_MR 0x1c0000000000ULL
127 #define S390_M 0x5c0000000000ULL
128 #define S390_MFY 0xe3000000005cULL
129 #define S390_MGRK 0xb9ec00000000ULL
130 #define S390_MG 0xe30000000084ULL
131 #define S390_MSR 0xb25200000000ULL
132 #define S390_MS 0x710000000000ULL
133 #define S390_MSY 0xe30000000051ULL
134 #define S390_MSRKC 0xb9fd00000000ULL
135 #define S390_MSC 0xe30000000053ULL
136 #define S390_MSGR 0xb90c00000000ULL
137 #define S390_MSGRKC 0xb9ed00000000ULL
138 #define S390_MSG 0xe3000000000cULL
139 #define S390_MSGC 0xe30000000083ULL
141 #define S390_DR 0x1d0000000000ULL
142 #define S390_DLR 0xb99700000000ULL
143 #define S390_DLGR 0xb98700000000ULL
144 #define S390_DSGR 0xb90d00000000ULL
146 #define S390_ALR 0x1e0000000000ULL
147 #define S390_ALRK 0xb9fa00000000ULL
148 #define S390_AL 0x5e0000000000ULL
149 #define S390_ALY 0xe3000000005eULL
150 #define S390_ALGR 0xb90a00000000ULL
151 #define S390_ALGRK 0xb9ea00000000ULL
152 #define S390_ALG 0xe3000000000aULL
154 #define S390_SLR 0x1f0000000000ULL
155 #define S390_SLRK 0xb9fb00000000ULL
156 #define S390_SL 0x5f0000000000ULL
157 #define S390_SLY 0xe3000000005fULL
158 #define S390_SLGR 0xb90b00000000ULL
159 #define S390_SLGRK 0xb9eb00000000ULL
160 #define S390_SLG 0xe3000000000bULL
162 #define S390_LER 0x380000000000ULL
163 #define S390_LDR 0x280000000000ULL
164 #define S390_LXR 0xb36500000000ULL
165 #define S390_LE 0x780000000000ULL
166 #define S390_LEY 0xed0000000064ULL
167 #define S390_LD 0x680000000000ULL
168 #define S390_LDY 0xed0000000065ULL
170 #define S390_STE 0x700000000000ULL
171 #define S390_STEY 0xed0000000066ULL
172 #define S390_STD 0x600000000000ULL
173 #define S390_STDY 0xed0000000067ULL
175 #define S390_LA 0x410000000000ULL
176 #define S390_LAY 0xe30000000071ULL
178 #define S390_STC 0x420000000000ULL
179 #define S390_STCY 0xe30000000072ULL
180 #define S390_STH 0x400000000000ULL
181 #define S390_STHY 0xe30000000070ULL
182 #define S390_ST 0x500000000000ULL
183 #define S390_STY 0xe30000000050ULL
184 #define S390_STG 0xe30000000024ULL
186 #define S390_IC 0x430000000000ULL
187 #define S390_ICY 0xe30000000073ULL
189 #define S390_LCEBR 0xb30300000000ULL
190 #define S390_LCDBR 0xb31300000000ULL
191 #define S390_LCXBR 0xb34300000000ULL
193 #define S390_CEBR 0xb30900000000ULL
194 #define S390_CDBR 0xb31900000000ULL
195 #define S390_CXBR 0xb34900000000ULL
196 #define S390_CEB 0xed0000000009ULL
197 #define S390_CDB 0xed0000000019ULL
199 #define S390_AEBR 0xb30a00000000ULL
200 #define S390_ADBR 0xb31a00000000ULL
201 #define S390_AXBR 0xb34a00000000ULL
202 #define S390_AEB 0xed000000000aULL
203 #define S390_ADB 0xed000000001aULL
205 #define S390_SEBR 0xb30b00000000ULL
206 #define S390_SDBR 0xb31b00000000ULL
207 #define S390_SXBR 0xb34b00000000ULL
208 #define S390_SEB 0xed000000000bULL
209 #define S390_SDB 0xed000000001bULL
211 #define S390_DEBR 0xb30d00000000ULL
212 #define S390_DDBR 0xb31d00000000ULL
213 #define S390_DXBR 0xb34d00000000ULL
214 #define S390_DEB 0xed000000000dULL
215 #define S390_DDB 0xed000000001dULL
217 #define S390_SQEBR 0xb31400000000ULL
218 #define S390_SQDBR 0xb31500000000ULL
219 #define S390_SQXBR 0xb31600000000ULL
220 #define S390_SQEB 0xed0000000014ULL
221 #define S390_SQDB 0xed0000000015ULL
223 #define S390_MEEBR 0xb31700000000ULL
224 #define S390_MDBR 0xb31c00000000ULL
225 #define S390_MXBR 0xb34c00000000ULL
226 #define S390_MEEB 0xed0000000017ULL
227 #define S390_MDB 0xed000000001cULL
229 #define S390_FIEBR 0xb35700000000ULL
230 #define S390_FIDBR 0xb35f00000000ULL
231 #define S390_FIXBR 0xb34700000000ULL
232 #define S390_FI_ROUND 0x000040000000ULL
233 #define S390_FI_TRUNC 0x000050000000ULL
234 #define S390_FI_CEIL 0x000060000000ULL
235 #define S390_FI_FLOOR 0x000070000000ULL
237 #define S390_CEFBR 0xb39400000000ULL
238 #define S390_CDFBR 0xb39500000000ULL
239 #define S390_CXFBR 0xb39600000000ULL
240 #define S390_CEGBR 0xb3a400000000ULL
241 #define S390_CDGBR 0xb3a500000000ULL
242 #define S390_CXGBR 0xb3a600000000ULL
244 #define S390_CFEBR 0xb39800000000ULL
245 #define S390_CFDBR 0xb39900000000ULL
246 #define S390_CFXBR 0xb39a00000000ULL
247 #define S390_CGEBR 0xb3a800000000ULL
248 #define S390_CGDBR 0xb3a900000000ULL
249 #define S390_CGXBR 0xb3aa00000000ULL
251 #define S390_LHR 0xb92700000000ULL
252 #define S390_LH 0x480000000000ULL
253 #define S390_LHY 0xe30000000078ULL
254 #define S390_LGHR 0xb90700000000ULL
255 #define S390_LGH 0xe30000000015ULL
256 #define S390_LGF 0xe30000000014ULL
257 #define S390_LLGF 0xe30000000016ULL
259 #define S390_RLL 0xeb000000001dULL
260 #define S390_RLLG 0xeb000000001cULL
261 #define S390_SRL 0x880000000000ULL
262 #define S390_SRLK 0xeb00000000deULL
263 #define S390_SRLG 0xeb000000000cULL
264 #define S390_SLL 0x890000000000ULL
265 #define S390_SLLK 0xeb00000000dfULL
266 #define S390_SLLG 0xeb000000000dULL
267 #define S390_SRA 0x8a0000000000ULL
268 #define S390_SRAK 0xeb00000000dcULL
269 #define S390_SRAG 0xeb000000000aULL
270 #define S390_SLA 0x8b0000000000ULL
271 #define S390_SLAK 0xeb00000000ddULL
272 #define S390_SLAG 0xeb000000000bULL
274 #define S390_STM 0x900000000000ULL
275 #define S390_STMY 0xeb0000000090ULL
276 #define S390_STMG 0xeb0000000024ULL
277 #define S390_LM 0x980000000000ULL
278 #define S390_LMY 0xeb0000000098ULL
279 #define S390_LMG 0xeb0000000004ULL
281 #define S390_MVI 0x920000000000ULL
282 #define S390_MVIY 0xeb0000000052ULL
283 #define S390_CLI 0x950000000000ULL
284 #define S390_CLIY 0xeb0000000055ULL
286 #define S390_TMLL 0xa70100000000ULL
287 #define S390_TMLH 0xa70000000000ULL
288 #define S390_TMHL 0xa70300000000ULL
289 #define S390_TMHH 0xa70200000000ULL
291 #define S390_BRC 0xa70400000000ULL
292 #define S390_BRAS 0xa70500000000ULL
293 #define S390_LRVR 0xb91f00000000ULL
294 #define S390_LRVRG 0xb90f00000000ULL
295 #define S390_POPCNT 0xb9e180000000ULL
296 #define S390_LOCR 0xb9f200000000ULL
297 #define S390_LOCGR 0xb9e200000000ULL
298 #define S390_NCRK 0xb9f500000000ULL
299 #define S390_NCGRK 0xb9e500000000ULL
300 #define S390_LOC 0xeb00000000f2ULL
301 #define S390_LOCG 0xeb00000000e2ULL
302 #define S390_BRCL 0xc00400000000ULL
303 #define S390_BRC_OVF 0x1ULL
304 #define S390_BRC_GREATER 0x2ULL
305 #define S390_BRC_LESS 0x4ULL
306 #define S390_BRC_EQ 0x8ULL
308 #define S390_IIHF 0xc00800000000ULL
309 #define S390_IILF 0xc00900000000ULL
311 #define S390_MVC 0xd20000000000ULL
313 struct codes {
314 it rr;
315 it rrk;
316 it rx;
317 it rxy;
318 it rrg;
319 it rrgk;
320 it rxg;
321 it ri;
322 it rig;
323 it rig32;
324 it rill;
325 it rilh;
326 it rihl;
327 it rihh;
328 it rilf;
329 it rihf;
330 int neg_imm;
331 };
333 static const struct codes codes_cmp = { S390_CR, -1, S390_C, S390_CY, S390_CGR, -1, S390_CG, S390_CHI, S390_CGHI, -1, -1, -1, -1, -1, -1, -1, 0 };
334 static const struct codes codes_cmp_log = { S390_CLR, -1, S390_CL, S390_CLY, S390_CLGR, -1, S390_CLG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
335 static const struct codes codes_ic = { -1, -1, S390_IC, S390_ICY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
336 static const struct codes codes_load_8 = { S390_LBR, -1, -1, S390_LB, S390_LGBR, -1, S390_LGB, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
337 static const struct codes codes_load_16 = { -1, -1, S390_LH, S390_LHY, S390_LGHR, -1, S390_LGH, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
338 static const struct codes codes_load_32 = { -1, -1, -1, -1, S390_LGFR, -1, S390_LGF, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
339 static const struct codes codes_load_8_unsigned = { -1, -1, -1, -1, S390_LLGCR, -1, S390_LLGC, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
340 static const struct codes codes_load_16_unsigned = { -1, -1, -1, -1, S390_LLGHR, -1, S390_LLGH, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
341 static const struct codes codes_load_32_unsigned = { -1, -1, -1, -1, S390_LLGFR, -1, S390_LLGF, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
342 static const struct codes codes_load = { S390_LR, -1, S390_L, S390_LY, S390_LGR, -1, S390_LG, S390_LHI, S390_LGHI, S390_LGFI, -1, -1, -1, -1, -1, -1, 0 };
343 static const struct codes codes_store_8 = { -1, -1, S390_STC, S390_STCY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
344 static const struct codes codes_store_16 = { -1, -1, S390_STH, S390_STHY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
345 static const struct codes codes_store = { -1, -1, S390_ST, S390_STY, -1, -1, S390_STG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
347 static const struct codes codes_alu_no_flags[] = {
348 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
349 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
350 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
351 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
352 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
353 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
354 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
355 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
356 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
357 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
358 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
359 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
360 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
361 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
362 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
363 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
364 { S390_MSR, -1, S390_MS, S390_MSY, S390_MSGR, -1, S390_MSG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
365 };
367 static const struct codes codes_alu[] = {
368 { S390_AR, S390_ARK, S390_A, S390_AY, S390_AGR, S390_AGRK, S390_AG, S390_AHI, S390_AGHI, -1, -1, -1, -1, -1, -1, -1, 0 },
369 { S390_OR, S390_ORK, S390_O, S390_OY, S390_OGR, S390_OGRK, S390_OG, -1, -1, -1, S390_OILL, S390_OILH, S390_OIHL, S390_OIHH, S390_OILF, S390_OIHF, 0 },
370 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
371 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
372 { S390_NR, S390_NRK, S390_N, S390_NY, S390_NGR, S390_NGRK, S390_NG, -1, -1, -1, S390_NILL, S390_NILH, S390_NIHL, S390_NIHH, S390_NILF, S390_NIHF, 2 },
373 { S390_SR, S390_SRK, S390_S, S390_SY, S390_SGR, S390_SGRK, S390_SG, S390_AHI, S390_AGHI, -1, -1, -1, -1, -1, -1, -1, 1 },
374 { S390_XR, S390_XRK, S390_X, S390_XY, S390_XGR, S390_XGRK, S390_XG, -1, -1, -1, -1, -1, -1, -1, S390_XILF, S390_XIHF, 0 },
375 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
376 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
377 { -1, S390_NCRK, -1, -1, -1, S390_NCGRK, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
378 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
379 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
380 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
381 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
382 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
383 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
384 { -1, S390_MSRKC, -1, S390_MSC, -1, S390_MSGRKC, S390_MSGC, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
385 };
387 static const struct codes codes_alu_log[] = {
388 { S390_ALR, S390_ALRK, S390_AL, S390_ALY, S390_ALGR, S390_ALGRK, S390_ALG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
389 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
390 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
391 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
392 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
393 { S390_SLR, S390_SLRK, S390_SL, S390_SLY, S390_SLGR, S390_SLGRK, S390_SLG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
394 };
396 static const it rot32[9] = {
397 S390_RLL, -1, -1, -1,
398 S390_SLL, S390_SRL, -1, S390_SRA,
399 S390_SLA,
400 };
402 static const it rot32k[9] = {
403 S390_RLL, -1, -1, -1,
404 S390_SLLK, S390_SRLK, -1, S390_SRAK,
405 S390_SLAK,
406 };
408 static const it rot64[9] = {
409 S390_RLLG, -1, -1, -1,
410 S390_SLLG, S390_SRLG, -1, S390_SRAG,
411 S390_SLAG,
412 };
414 static const int8_t jmp_cond[0x30] = {
415 S390_BRC_OVF, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ,
416 -1, -1,
417 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_OVF,
418 -1, -1,
419 -1, -1,
420 -1, -1,
421 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
422 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
424 -1, -1,
425 S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ, -1,
426 -1, -1,
427 -1, -1,
428 -1, -1,
429 -1, -1,
430 -1, -1,
431 -1, -1,
433 -1, -1,
434 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
435 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_OVF,
436 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
437 -1, -1,
438 S390_BRC_OVF, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ,
439 -1, -1,
440 -1, -1,
441 };
443 static const int8_t jmp_cond_logical[0x8] = {
444 -1, -1,
445 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
446 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS,
447 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
448 };
450 struct fp_alu {
451 it err;
452 it drr;
453 it xrr;
454 it erx;
455 it drx;
456 };
458 static const struct fp_alu fp_alus[4] = {
459 { S390_AEBR, S390_ADBR, S390_AXBR, S390_AEB, S390_ADB },
460 { S390_SEBR, S390_SDBR, S390_SXBR, S390_SEB, S390_SDB },
461 { S390_MEEBR, S390_MDBR, S390_MXBR, S390_MEEB, S390_MDB },
462 { S390_DEBR, S390_DDBR, S390_DXBR, S390_DEB, S390_DDB },
463 };
465 static const struct fp_alu fp_alu1s[6] = {
466 { S390_LCEBR, S390_LCDBR, S390_LCXBR, -1, -1 },
467 { S390_SQEBR, S390_SQDBR, S390_SQXBR, S390_SQEB, S390_SQDB },
468 { S390_FIEBR | S390_FI_ROUND, S390_FIDBR | S390_FI_ROUND, S390_FIXBR | S390_FI_ROUND, -1, -1 },
469 { S390_FIEBR | S390_FI_FLOOR, S390_FIDBR | S390_FI_FLOOR, S390_FIXBR | S390_FI_FLOOR, -1, -1 },
470 { S390_FIEBR | S390_FI_CEIL, S390_FIDBR | S390_FI_CEIL, S390_FIXBR | S390_FI_CEIL, -1, -1 },
471 { S390_FIEBR | S390_FI_TRUNC, S390_FIDBR | S390_FI_TRUNC, S390_FIXBR | S390_FI_TRUNC, -1, -1 },
472 };
474 static const struct fp_alu fp_mov = {
475 S390_LER, S390_LDR, S390_LXR, -1, -1
476 };
478 static const struct fp_alu fp_cmp = {
479 S390_CEBR, S390_CDBR, S390_CXBR, S390_CEB, S390_CDB
480 };
482 static uint8_t get_jmp_cond(unsigned cond, bool logical)
483 {
484 int8_t c;
485 if (!logical) {
486 if (unlikely(cond >= n_array_elements(jmp_cond)))
487 goto invl;
488 c = jmp_cond[cond];
489 } else {
490 if (unlikely(cond >= n_array_elements(jmp_cond_logical)))
491 goto invl;
492 c = jmp_cond_logical[cond];
493 }
494 if (unlikely(c == -1))
495 goto invl;
496 return (uint8_t)c;
497 invl:
498 internal(file_line, "get_jmp_cond: invalid %scondition %x", logical ? "logical " : "", cond);
499 }
501 static bool attr_w cgen_s390(struct codegen_context *ctx, it code)
502 {
503 unsigned sz = code >> 46;
504 if (sz == 0) {
505 if (unlikely((uint32_t)code))
506 goto invl;
507 cgen_two(code >> 32);
508 } else if (sz == 1 || sz == 2) {
509 if (unlikely((uint16_t)code))
510 goto invl;
511 cgen_four(code >> 16);
512 } else if (sz == 3) {
513 cgen_two(code >> 32);
514 cgen_four(code);
515 } else {
516 invl:
517 internal(file_line, "cgen_s390: invalid insn %"PRIxMAX"", (uintmax_t)code);
518 }
519 return true;
520 }
522 static bool attr_w cgen_rr_rx(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, uint8_t *arg3, const struct codes *codes)
523 {
524 it code;
525 uint8_t b, x;
526 uint8_t *disp;
527 int64_t imm;
528 if (size > OP_SIZE_NATIVE)
529 goto invl;
530 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
531 goto invl;
532 if (arg3[0] < 0x10) {
533 unsigned sz;
534 bool k = false;
535 if (size != OP_SIZE_8) {
536 code = codes->rr;
537 if (code == (it)-1 || arg1[0] != arg2[0]) {
538 code = codes->rrk;
539 k = true;
540 }
541 } else {
542 code = codes->rrg;
543 if (code == (it)-1 || arg1[0] != arg2[0]) {
544 code = codes->rrgk;
545 k = true;
546 }
547 }
548 sz = code >> 46;
549 if (k) {
550 code |= (it)arg1[0] << 20;
551 code |= (it)arg2[0] << 16;
552 code |= (it)arg3[0] << 28;
553 } else if (!sz) {
554 code |= (it)arg1[0] << 36;
555 code |= (it)arg3[0] << 32;
556 } else if (sz == 1 || sz == 2) {
557 code |= (it)arg1[0] << 20;
558 code |= (it)arg3[0] << 16;
559 } else {
560 goto invl;
561 }
562 g(cgen_s390(ctx, code));
563 return true;
564 }
565 if (unlikely(arg1[0] != arg2[0]))
566 goto invl;
567 if (arg3[0] == ARG_IMM) {
568 imm = get_imm(&arg3[1]);
569 if (codes->neg_imm == 1)
570 imm = -(uint64_t)imm;
571 if (imm >= -0x8000 && imm < 0x8000) {
572 code = size != OP_SIZE_8 ? codes->ri : codes->rig;
573 if (unlikely(code == (it)-1))
574 goto log_op;
575 code |= (it)arg1[0] << 36;
576 code |= (it)(imm & 0xffff) << 16;
577 } else if (imm >= -0x80000000LL && imm < 0x80000000LL) {
578 code = codes->rig32;
579 if (unlikely(code == (it)-1))
580 goto log_op;
581 code |= (it)arg1[0] << 36;
582 code |= (it)(imm & 0xffffffffLL);
583 } else {
584 goto log_op;
585 }
586 g(cgen_s390(ctx, code));
587 return true;
588 log_op:
589 if (codes->neg_imm == 2)
590 imm = ~imm;
591 if (!(imm & ~0xffffULL) && codes->rill != (it)-1) {
592 code = codes->rill;
593 if (codes->neg_imm == 2)
594 imm = ~imm;
595 code |= (it)(imm & 0xffffULL) << 16;
596 } else if (!(imm & ~0xffff0000ULL) && codes->rilh != (it)-1) {
597 code = codes->rilh;
598 if (codes->neg_imm == 2)
599 imm = ~imm;
600 code |= (it)(imm & 0xffff0000ULL);
601 } else if (!(imm & ~0xffff00000000ULL) && codes->rihl != (it)-1) {
602 code = codes->rihl;
603 if (codes->neg_imm == 2)
604 imm = ~imm;
605 code |= (it)((uint64_t)imm & 0xffff00000000ULL) >> 16;
606 } else if (!(imm & ~0xffff000000000000ULL) && codes->rihh != (it)-1) {
607 code = codes->rihh;
608 if (codes->neg_imm == 2)
609 imm = ~imm;
610 code |= (it)((uint64_t)imm & 0xffff000000000000ULL) >> 32;
611 } else if (!(imm & ~0xffffffffULL) && codes->rilf != (it)-1) {
612 code = codes->rilf;
613 if (codes->neg_imm == 2)
614 imm = ~imm;
615 code |= (it)(imm & 0xffffffffLL);
616 } else if (!(imm & ~0xffffffff00000000ULL) && codes->rihf != (it)-1) {
617 code = codes->rihf;
618 if (codes->neg_imm == 2)
619 imm = ~imm;
620 code |= (it)(((uint64_t)imm & 0xffffffff00000000LL) >> 32);
621 } else {
622 goto invl;
623 }
624 code |= (it)arg1[0] << 36;
625 g(cgen_s390(ctx, code));
626 return true;
627 } else if (arg3[0] == ARG_ADDRESS_0) {
628 b = 0;
629 x = 0;
630 disp = &arg3[1];
631 } else if (arg3[0] == ARG_ADDRESS_1) {
632 b = arg3[1];
633 x = 0;
634 disp = &arg3[2];
635 } else if (arg3[0] == ARG_ADDRESS_2) {
636 b = arg3[1];
637 x = arg3[2];
638 disp = &arg3[3];
639 } else {
640 goto invl;
641 }
643 imm = get_imm(disp);
644 if (size != OP_SIZE_8) {
645 if (imm >= 0 && imm < 0x1000 && codes->rx != (it)-1) {
646 code = codes->rx;
647 code |= (it)arg1[0] << 36;
648 code |= (it)x << 32;
649 code |= (it)b << 28;
650 code |= (it)(imm & 0xfff) << 16;
651 } else if (imm >= -0x80000 && imm < 0x80000) {
652 code = codes->rxy;
653 goto rxya;
654 } else {
655 goto invl;
656 }
657 } else {
658 code = codes->rxg;
659 if (imm >= -0x80000 && imm < 0x80000) {
660 rxya:
661 code |= (it)arg1[0] << 36;
662 code |= (it)x << 32;
663 code |= (it)b << 28;
664 code |= (it)(imm & 0xfff) << 16;
665 code |= (it)(imm & 0xff000) >> 4;
666 } else {
667 goto invl;
668 }
670 }
671 g(cgen_s390(ctx, code));
672 return true;
673 invl:
674 internal(file_line, "cgen_rr_rx: invalid arguments %u, %02x, %02x, %02x", size, *arg1, *arg2, *arg3);
675 return false;
676 }
678 static bool attr_w cgen_fp_mem(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, it e, it ey, it d, it dy)
679 {
680 it code;
681 uint8_t b, x;
682 uint8_t *disp;
683 int64_t imm;
684 if (size != OP_SIZE_4 && size != OP_SIZE_8)
685 goto invl;
686 if (unlikely(!reg_is_fp(arg1[0])))
687 goto invl;
688 if (arg2[0] == ARG_ADDRESS_0) {
689 b = 0;
690 x = 0;
691 disp = &arg2[1];
692 } else if (arg2[0] == ARG_ADDRESS_1) {
693 b = arg2[1];
694 x = 0;
695 disp = &arg2[2];
696 } else if (arg2[0] == ARG_ADDRESS_2) {
697 b = arg2[1];
698 x = arg2[2];
699 disp = &arg2[3];
700 } else {
701 goto invl;
702 }
703 imm = get_imm(disp);
704 if (imm >= 0 && imm < 4096) {
705 code = size == OP_SIZE_4 ? e : d;
706 } else if (imm >= -0x80000 && imm < 0x80000) {
707 code = size == OP_SIZE_4 ? ey : dy;
708 code |= (it)(imm & 0xff000) >> 4;
709 } else {
710 goto invl;
711 }
712 code |= (it)(arg1[0] & 0xf) << 36;
713 code |= (it)x << 32;
714 code |= (it)b << 28;
715 code |= (it)(imm & 0xfff) << 16;
716 g(cgen_s390(ctx, code));
717 return true;
718 invl:
719 internal(file_line, "cgen_fp_mem: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
720 return false;
721 }
723 static bool attr_w cgen_fp_op(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, const struct fp_alu *fp_alu)
724 {
725 it code;
726 uint8_t b, x;
727 uint8_t *disp;
728 int64_t imm;
729 if (size != OP_SIZE_4 && size != OP_SIZE_8 && size != OP_SIZE_16)
730 goto invl;
731 if (reg_is_fp(arg2[0])) {
732 unsigned sz;
733 code = size == OP_SIZE_4 ? fp_alu->err : size == OP_SIZE_8 ? fp_alu->drr : fp_alu->xrr;
734 sz = code >> 46;
735 if (!sz) {
736 code |= (it)(arg1[0] & 0xf) << 36;
737 code |= (it)(arg2[0] & 0xf) << 32;
738 } else {
739 code |= (it)(arg1[0] & 0xf) << 20;
740 code |= (it)(arg2[0] & 0xf) << 16;
741 }
742 g(cgen_s390(ctx, code));
743 return true;
744 } else if (arg2[0] == ARG_ADDRESS_0) {
745 b = 0;
746 x = 0;
747 disp = &arg2[1];
748 } else if (arg2[0] == ARG_ADDRESS_1) {
749 b = arg2[1];
750 x = 0;
751 disp = &arg2[2];
752 } else if (arg2[0] == ARG_ADDRESS_2) {
753 b = arg2[1];
754 x = arg2[2];
755 disp = &arg2[3];
756 } else {
757 goto invl;
758 }
759 imm = get_imm(disp);
760 if (unlikely(imm < 0) || unlikely(imm >= 4096))
761 goto invl;
762 if (unlikely(size == OP_SIZE_16))
763 goto invl;
764 code = size == OP_SIZE_4 ? fp_alu->erx : fp_alu->drx;
765 code |= (it)(arg1[0] & 0xf) << 36;
766 code |= (it)x << 32;
767 code |= (it)b << 28;
768 code |= (it)(imm & 0xfff) << 16;
769 g(cgen_s390(ctx, code));
770 return true;
771 invl:
772 internal(file_line, "cgen_fp_op: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
773 return false;
774 }
776 static bool attr_w cgen_xi(struct codegen_context *ctx, uint8_t *arg1, uint8_t *arg2, it xi, it xiy)
777 {
778 it code;
779 uint8_t b;
780 uint8_t *disp;
781 int64_t val, imm;
782 if (unlikely(arg1[0] == ARG_ADDRESS_0)) {
783 b = 0;
784 disp = &arg1[1];
785 } else if (likely(arg1[0] == ARG_ADDRESS_1) && likely(arg2[0] == ARG_IMM)) {
786 b = arg1[1];
787 disp = &arg1[2];
788 } else {
789 goto invl;
790 }
792 imm = get_imm(disp);
793 if (likely(arg2[0] == ARG_IMM)) {
794 val = get_imm(&arg2[1]);
795 } else {
796 goto invl;
797 }
799 if (imm >= 0 && imm < 0x1000) {
800 code = xi;
801 code |= (it)(imm & 0xfff) << 16;
802 } else if (imm >= -0x80000 && imm < 0x80000) {
803 code = xiy;
804 code |= (it)(imm & 0xfff) << 16;
805 code |= (it)(imm & 0xff000) >> 4;
806 } else {
807 goto invl;
808 }
810 code |= (it)(val & 0xff) << 32;
811 code |= (it)b << 28;
813 g(cgen_s390(ctx, code));
814 return true;
815 invl:
816 internal(file_line, "cgen_xi: invalid arguments %02x, %02x", *arg1, *arg2);
817 return false;
818 }
820 static bool attr_w cgen_lm_stm(struct codegen_context *ctx, unsigned size, uint8_t r_start, uint8_t r_end, uint8_t *arg1, it m, it my, it mg)
821 {
822 it code;
823 int64_t imm;
824 if (unlikely(r_start >= 0x10) || unlikely(r_end >= 0x10) || unlikely(arg1[0] != ARG_ADDRESS_1) || unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
825 goto invl;
826 imm = get_imm(&arg1[2]);
827 if (size == OP_SIZE_4 && imm >= 0 && imm < 0x1000) {
828 code = m;
829 code |= (it)(imm & 0xfff) << 16;
830 } else {
831 if (size == OP_SIZE_4)
832 code = my;
833 else
834 code = mg;
835 code |= (it)(imm & 0xfff) << 16;
836 code |= (it)(imm & 0xff000) >> 4;
837 }
838 code |= (it)r_start << 36;
839 code |= (it)r_end << 32;
840 code |= (it)arg1[1] << 28;
841 g(cgen_s390(ctx, code));
842 return true;
843 invl:
844 internal(file_line, "cgen_lm_stm: invalid arguments %02x", *arg1);
845 return false;
846 }
848 static bool attr_w cgen_s390_push_pop(struct codegen_context *ctx, unsigned size, bool push)
849 {
850 uint8_t *arg1;
851 arg1 = ctx->code_position;
852 ctx->code_position = arg1 + arg_size(*arg1);
853 if (!push)
854 g(cgen_lm_stm(ctx, size, R_6, R_15, arg1, S390_LM, S390_LMY, S390_LMG));
855 else
856 g(cgen_lm_stm(ctx, size, R_6, R_15, arg1, S390_STM, S390_STMY, S390_STMG));
857 return true;
858 }
860 static bool attr_w cgen_call_indirect(struct codegen_context *ctx)
861 {
862 uint8_t reg = cget_one(ctx);
863 it code = S390_BASR;
864 code |= (it)R_14 << 36;
865 code |= (it)reg << 32;
866 g(cgen_s390(ctx, code));
867 return true;
868 }
870 static bool attr_w cgen_branch_imm(struct codegen_context *ctx, uint8_t reg, int64_t imm)
871 {
872 it code;
873 code = S390_BRAS;
874 code |= (it)reg << 36;
875 code |= (OP_SIZE_NATIVE == OP_SIZE_4 ? (it)4 : (it)6) << 16;
876 g(cgen_s390(ctx, code));
877 if (OP_SIZE_NATIVE == OP_SIZE_4) {
878 cgen_four(imm);
879 } else {
880 cgen_eight(imm);
881 }
882 code = OP_SIZE_NATIVE == OP_SIZE_4 ? S390_L : S390_LG;
883 code |= (it)reg << 36;
884 code |= (it)reg << 28;
885 g(cgen_s390(ctx, code));
886 return true;
887 }
889 static bool attr_w cgen_mov(struct codegen_context *ctx, unsigned size)
890 {
891 uint8_t *arg1 = ctx->code_position;
892 uint8_t *arg2 = arg1 + arg_size(*arg1);
893 ctx->code_position = arg2 + arg_size(*arg2);
894 if (arg1[0] < 0x10) {
895 if (unlikely(size != OP_SIZE_NATIVE)) {
896 switch (size) {
897 case OP_SIZE_1:
898 if (unlikely(!cpu_test_feature(CPU_FEATURE_extended_imm)))
899 goto invl;
900 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_8_unsigned));
901 return true;
902 case OP_SIZE_2:
903 if (unlikely(!cpu_test_feature(CPU_FEATURE_extended_imm)))
904 goto invl;
905 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_16_unsigned));
906 return true;
907 case OP_SIZE_4:
908 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_32_unsigned));
909 return true;
910 default:
911 goto invl;
912 }
913 }
914 if (!cpu_test_feature(CPU_FEATURE_extended_imm) && arg2[0] == ARG_IMM) {
915 int64_t imm = get_imm(&arg2[1]);
916 if (imm < -0x8000 || imm >= 0x8000) {
917 g(cgen_branch_imm(ctx, arg1[0], imm));
918 return true;
919 }
920 }
921 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_load));
922 return true;
923 }
924 if (reg_is_fp(arg1[0])) {
925 if (reg_is_fp(arg2[0])) {
926 g(cgen_fp_op(ctx, size, arg1, arg2, &fp_mov));
927 return true;
928 }
929 if (unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
930 goto invl;
931 g(cgen_fp_mem(ctx, size, arg1, arg2, S390_LE, S390_LEY, S390_LD, S390_LDY));
932 return true;
933 }
934 if (arg2[0] < 0x10) {
935 g(cgen_rr_rx(ctx, size, arg2, arg2, arg1, size == OP_SIZE_1 ? &codes_store_8 : size == OP_SIZE_2 ? &codes_store_16 : &codes_store));
936 return true;
937 }
938 if (reg_is_fp(arg2[0])) {
939 if (unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
940 goto invl;
941 g(cgen_fp_mem(ctx, size, arg2, arg1, S390_STE, S390_STEY, S390_STD, S390_STDY));
942 return true;
943 }
944 if (size == OP_SIZE_1 && arg1[0] == ARG_ADDRESS_1 && arg2[0] == ARG_IMM) {
945 g(cgen_xi(ctx, arg1, arg2, S390_MVI, S390_MVIY));
946 return true;
947 }
948 invl:
949 internal(file_line, "cgen_mov: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
950 return false;
951 }
953 static bool attr_w cgen_movsx(struct codegen_context *ctx, unsigned size)
954 {
955 uint8_t *arg1, *arg2;
956 if (unlikely(size == OP_SIZE_NATIVE)) {
957 g(cgen_mov(ctx, size));
958 return true;
959 }
960 arg1 = ctx->code_position;
961 arg2 = arg1 + arg_size(*arg1);
962 ctx->code_position = arg2 + arg_size(*arg2);
963 switch (size) {
964 case OP_SIZE_1:
965 if (arg2[0] >= 0x10 ? !cpu_test_feature(CPU_FEATURE_long_displacement) : !cpu_test_feature(CPU_FEATURE_extended_imm))
966 goto invl;
967 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_8));
968 return true;
969 case OP_SIZE_2:
970 if (arg2[0] < 0x10 && !cpu_test_feature(CPU_FEATURE_extended_imm))
971 goto invl;
972 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_16));
973 return true;
974 case OP_SIZE_4:
975 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_32));
976 return true;
977 default:
978 goto invl;
979 }
980 invl:
981 internal(file_line, "cgen_movsx: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
982 return false;
983 }
985 static bool attr_w cgen_cmp(struct codegen_context *ctx, unsigned size, unsigned writes_flags)
986 {
987 uint8_t *arg1, *arg2;
988 arg1 = ctx->code_position;
989 arg2 = arg1 + arg_size(*arg1);
990 ctx->code_position = arg2 + arg_size(*arg2);
991 if (writes_flags == 1) {
992 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_cmp));
993 return true;
994 } else if (writes_flags == 2) {
995 if (size == OP_SIZE_1 && arg1[0] == ARG_ADDRESS_1 && arg2[0] == ARG_IMM) {
996 g(cgen_xi(ctx, arg1, arg2, S390_CLI, S390_CLIY));
997 return true;
998 }
999 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_cmp_log));
1000 return true;
1001 }
1002 internal(file_line, "cgen_cmp: invalid arguments %u, %02x, %02x, %u", size, *arg1, *arg2, writes_flags);
1003 return false;
1004 }
1006 static bool attr_w cgen_test(struct codegen_context *ctx, unsigned size)
1007 {
1008 it code;
1009 uint8_t *arg1, *arg2;
1010 arg1 = ctx->code_position;
1011 arg2 = arg1 + arg_size(*arg1);
1012 ctx->code_position = arg2 + arg_size(*arg2);
1013 if (likely(arg1[0] < 0x10) && likely(arg2[0] == ARG_IMM)) {
1014 uint16_t m;
1015 int64_t imm = get_imm(&arg2[1]);
1016 if (!(imm & ~0xffffULL)) {
1017 code = S390_TMLL;
1018 m = (uint64_t)imm;
1019 } else if (!(imm & ~0xffff0000ULL)) {
1020 code = S390_TMLH;
1021 m = (uint64_t)imm >> 16;
1022 } else if (!(imm & ~0xffff00000000ULL)) {
1023 code = S390_TMHL;
1024 m = (uint64_t)imm >> 32;
1025 } else if (!(imm & ~0xffff000000000000ULL)) {
1026 code = S390_TMHH;
1027 m = (uint64_t)imm >> 48;
1028 } else {
1029 goto invl;
1030 }
1031 code |= (it)m << 16;
1032 code |= (it)arg1[0] << 36;
1033 g(cgen_s390(ctx, code));
1034 return true;
1035 }
1036 if (arg1[0] < 0x10 && arg2[0] == arg1[0]) {
1037 if (size == OP_SIZE_4) {
1038 code = S390_LTR;
1039 code |= (it)arg1[0] << 36;
1040 code |= (it)arg1[0] << 32;
1041 } else if (size == OP_SIZE_8) {
1042 code = S390_LTGR;
1043 code |= (it)arg1[0] << 20;
1044 code |= (it)arg1[0] << 16;
1045 } else {
1046 goto invl;
1047 }
1048 g(cgen_s390(ctx, code));
1049 return true;
1050 }
1051 invl:
1052 internal(file_line, "cgen_test: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
1053 return false;
1054 }
1056 static bool attr_w cgen_alu(struct codegen_context *ctx, unsigned size, unsigned alu, unsigned writes_flags)
1057 {
1058 uint8_t *arg1, *arg2, *arg3;
1059 arg1 = ctx->code_position;
1060 arg2 = arg1 + arg_size(*arg1);
1061 arg3 = arg2 + arg_size(*arg2);
1062 ctx->code_position = arg3 + arg_size(*arg3);
1063 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
1064 goto invl;
1065 if (writes_flags == 0) {
1066 if (unlikely(alu >= n_array_elements(codes_alu_no_flags)))
1067 goto invl;
1068 if (unlikely(codes_alu_no_flags[alu].rr == (it)-1) && unlikely(codes_alu_no_flags[alu].rrk == (it)-1))
1069 goto invl;
1070 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu_no_flags[alu]));
1071 } else if (writes_flags == 1) {
1072 if (unlikely(alu >= n_array_elements(codes_alu)))
1073 goto invl;
1074 if (unlikely(codes_alu[alu].rr == (it)-1) && unlikely(codes_alu[alu].rrk == (it)-1))
1075 goto invl;
1076 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu[alu]));
1077 } else if (writes_flags == 2) {
1078 if (unlikely(alu >= n_array_elements(codes_alu_log)))
1079 goto invl;
1080 if (unlikely(codes_alu_log[alu].rr == (it)-1) && unlikely(codes_alu_log[alu].rrk == (it)-1))
1081 goto invl;
1082 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu_log[alu]));
1083 } else {
1084 goto invl;
1085 }
1086 return true;
1087 invl:
1088 /*debug("%s", da(ctx->fn,function)->function_name);*/
1089 internal(file_line, "cgen_alu: invalid arguments %u, %u, %02x, %02x, %02x", size, alu, *arg1, *arg2, *arg3);
1090 return false;
1091 }
1093 static bool attr_w cgen_alu1(struct codegen_context *ctx, unsigned size, unsigned alu, unsigned writes_flags)
1094 {
1095 it code;
1096 uint8_t *arg1 = ctx->code_position;
1097 uint8_t *arg2 = arg1 + arg_size(*arg1);
1098 ctx->code_position = arg2 + arg_size(*arg2);
1099 switch (alu) {
1100 case ALU1_NEG:
1101 if (unlikely(writes_flags != 1))
1102 goto invl;
1103 if (size == OP_SIZE_4) {
1104 code = S390_LCR;
1105 code |= (it)arg1[0] << 36;
1106 code |= (it)arg2[0] << 32;
1107 } else if (size == OP_SIZE_8) {
1108 code = S390_LCGR;
1109 code |= (it)arg1[0] << 20;
1110 code |= (it)arg2[0] << 16;
1111 } else {
1112 goto invl;
1113 }
1114 break;
1115 case ALU1_BSWAP:
1116 if (size == OP_SIZE_4) {
1117 code = S390_LRVR;
1118 } else if (size == OP_SIZE_8) {
1119 code = S390_LRVRG;
1120 } else {
1121 goto invl;
1122 }
1123 code |= (it)arg1[0] << 20;
1124 code |= (it)arg2[0] << 16;
1125 break;
1126 case ALU1_POPCNT:
1127 if (size != OP_SIZE_8)
1128 goto invl;
1129 code = S390_POPCNT;
1130 code |= (it)arg1[0] << 20;
1131 code |= (it)arg2[0] << 16;
1132 break;
1133 default:
1134 goto invl;
1135 }
1136 g(cgen_s390(ctx, code));
1137 return true;
1138 invl:
1139 internal(file_line, "cgen_alu1: invalid arguments %u, %u, %02x, %02x", size, alu, *arg1, *arg2);
1140 return false;
1141 }
1143 static bool attr_w cgen_lea3(struct codegen_context *ctx)
1144 {
1145 it code;
1146 int64_t imm;
1147 uint8_t *arg1, *arg2, *arg3, *arg4;
1148 arg1 = ctx->code_position;
1149 arg2 = arg1 + arg_size(*arg1);
1150 arg3 = arg2 + arg_size(*arg2);
1151 arg4 = arg3 + arg_size(*arg3);
1152 ctx->code_position = arg4 + arg_size(*arg4);
1153 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || arg4[0] != ARG_IMM)
1154 goto invl;
1155 imm = get_imm(&arg4[1]);
1156 if (imm >= 0 && imm < 0x1000) {
1157 code = S390_LA;
1158 } else {
1159 code = S390_LAY;
1160 code |= (it)(imm & 0xff000) >> 4;
1161 }
1162 code |= (it)arg1[0] << 36;
1163 code |= (it)arg2[0] << 32;
1164 code |= (it)arg3[0] << 28;
1165 code |= (it)(imm & 0xfff) << 16;
1166 g(cgen_s390(ctx, code));
1167 return true;
1168 invl:
1169 internal(file_line, "cgen_lea3: invalid arguments %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4);
1170 return false;
1171 }
1173 static bool attr_w cgen_rot(struct codegen_context *ctx, unsigned size, unsigned alu)
1174 {
1175 it code;
1176 unsigned sz;
1177 uint8_t *arg1, *arg2, *arg3;
1178 arg1 = ctx->code_position;
1179 arg2 = arg1 + arg_size(*arg1);
1180 arg3 = arg2 + arg_size(*arg2);
1181 ctx->code_position = arg3 + arg_size(*arg3);
1182 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
1183 goto invl;
1184 if (arg3[0] >= 0x10 && unlikely(arg3[0] != ARG_IMM))
1185 goto invl;
1187 if (size == OP_SIZE_4 && arg1[0] == arg2[0]) {
1188 code = rot32[alu];
1189 } else if (size == OP_SIZE_4) {
1190 code = rot32k[alu];
1191 } else if (size == OP_SIZE_8) {
1192 code = rot64[alu];
1193 } else {
1194 goto invl;
1195 }
1196 sz = code >> 46;
1197 if (sz == 1 || sz == 2) {
1198 code |= (it)arg1[0] << 36;
1199 } else if (sz == 3) {
1200 code |= (it)arg1[0] << 36;
1201 code |= (it)arg2[0] << 32;
1202 } else {
1203 goto invl;
1204 }
1205 if (arg3[0] == ARG_IMM)
1206 code |= (it)(get_imm(&arg3[1]) & (size == OP_SIZE_4 ? 0x1f : 0x3f)) << 16;
1207 else
1208 code |= (it)arg3[0] << 28;
1209 g(cgen_s390(ctx, code));
1210 return true;
1211 invl:
1212 internal(file_line, "cgen_rot: invalid arguments %u, %u, %02x, %02x, %02x", size, alu, *arg1, *arg2, *arg3);
1213 return false;
1214 }
1216 static bool attr_w cgen_mul_l(struct codegen_context *ctx, unsigned size)
1217 {
1218 it code;
1219 uint8_t *arg1, *arg2, *arg3, *arg4;
1220 arg1 = ctx->code_position;
1221 arg2 = arg1 + arg_size(*arg1);
1222 arg3 = arg2 + arg_size(*arg2);
1223 arg4 = arg3 + arg_size(*arg3);
1224 ctx->code_position = arg4 + arg_size(*arg4);
1225 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || unlikely(arg4[0] >= 0x10))
1226 goto invl;
1227 if (unlikely(arg2[0] & 1) || unlikely(arg1[0] != arg2[0] + 1) || unlikely(arg3[0] != arg1[0]))
1228 goto invl;
1229 if (size == OP_SIZE_4) {
1230 code = S390_MR;
1231 code |= (it)arg2[0] << 36;
1232 code |= (it)arg4[0] << 32;
1233 } else {
1234 code = S390_MGRK;
1235 code |= (it)arg2[0] << 20;
1236 code |= (it)arg3[0] << 16;
1237 code |= (it)arg4[0] << 28;
1238 }
1239 g(cgen_s390(ctx, code));
1240 return true;
1241 invl:
1242 internal(file_line, "cgen_mul_l: invalid arguments %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4);
1243 return false;
1244 }
1246 static bool attr_w cgen_div_l(struct codegen_context *ctx, unsigned size, bool sgn)
1247 {
1248 it code;
1249 uint8_t *arg1, *arg2, *arg3, *arg4, *arg5;
1250 arg1 = ctx->code_position;
1251 arg2 = arg1 + arg_size(*arg1);
1252 arg3 = arg2 + arg_size(*arg2);
1253 arg4 = arg3 + arg_size(*arg3);
1254 arg5 = arg4 + arg_size(*arg4);
1255 ctx->code_position = arg5 + arg_size(*arg5);
1256 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || unlikely(arg4[0] >= 0x10) || unlikely(arg5[0] >= 0x10))
1257 goto invl;
1258 if (unlikely(arg1[0] & 1) || unlikely(arg2[0] != arg1[0] + 1))
1259 goto invl;
1260 if (unlikely(arg3[0] != arg1[0]) || unlikely(arg4[0] != arg3[0] + 1))
1261 goto invl;
1262 if (!sgn) {
1263 code = size == OP_SIZE_4 ? S390_DLR : S390_DLGR;
1264 } else {
1265 code = size == OP_SIZE_4 ? S390_DR : S390_DSGR;
1266 }
1267 if (code == S390_DR) {
1268 code |= (it)arg1[0] << 36;
1269 code |= (it)arg5[0] << 32;
1270 } else {
1271 code |= (it)arg1[0] << 20;
1272 code |= (it)arg5[0] << 16;
1273 }
1274 g(cgen_s390(ctx, code));
1275 return true;
1276 invl:
1277 internal(file_line, "cgen_div_l: invalid arguments %02x, %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4, *arg4);
1278 return false;
1279 }
1281 static bool attr_w cgen_cmov(struct codegen_context *ctx, unsigned size, unsigned cond, bool logical)
1282 {
1283 uint8_t *arg1 = ctx->code_position;
1284 uint8_t *arg2 = arg1 + arg_size(*arg1);
1285 uint8_t *arg3 = arg2 + arg_size(*arg2);
1286 ctx->code_position = arg3 + arg_size(*arg3);
1287 if (unlikely(arg1[0] != arg2[0]) || arg1[0] >= 0x10)
1288 goto invl;
1290 if (arg3[0] < 0x10) {
1291 it code;
1292 code = size == OP_SIZE_4 ? S390_LOCR : S390_LOCGR;
1293 code |= (it)get_jmp_cond(cond, logical) << 28;
1294 code |= (it)arg1[0] << 20;
1295 code |= (it)arg3[0] << 16;
1296 g(cgen_s390(ctx, code));
1297 return true;
1298 } else if (arg3[0] == ARG_ADDRESS_1) {
1299 it code;
1300 int64_t imm;
1301 code = size == OP_SIZE_4 ? S390_LOC : S390_LOCG;
1302 code |= (it)get_jmp_cond(cond, logical) << 32;
1303 code |= (it)arg1[0] << 36;
1304 code |= (it)arg3[1] << 28;
1305 imm = get_imm(&arg3[2]);
1306 if (imm < -0x80000 || imm >= 0x80000)
1307 goto invl;
1308 code |= (it)(imm & 0xfff) << 16;
1309 code |= (it)(imm & 0xff000) >> 4;
1310 g(cgen_s390(ctx, code));
1311 return true;
1312 }
1314 invl:
1315 internal(file_line, "cgen_cmov: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1316 }
1318 static bool attr_w cgen_ldp_stp(struct codegen_context *ctx, unsigned size, bool st)
1319 {
1320 uint8_t *arg1, *arg2, *arg3;
1321 if (!st) {
1322 arg2 = ctx->code_position;
1323 arg3 = arg2 + arg_size(*arg2);
1324 arg1 = arg3 + arg_size(*arg3);
1325 ctx->code_position = arg1 + arg_size(*arg1);
1326 } else {
1327 arg1 = ctx->code_position;
1328 arg2 = arg1 + arg_size(*arg1);
1329 arg3 = arg2 + arg_size(*arg2);
1330 ctx->code_position = arg3 + arg_size(*arg3);
1331 }
1332 if (unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10))
1333 goto invl;
1334 if (unlikely(arg2[0] != arg3[0] + 1))
1335 goto invl;
1336 if (!st)
1337 g(cgen_lm_stm(ctx, size, arg3[0], arg2[0], arg1, S390_LM, S390_LMY, S390_LMG));
1338 else
1339 g(cgen_lm_stm(ctx, size, arg3[0], arg2[0], arg1, S390_STM, S390_STMY, S390_STMG));
1340 return true;
1341 invl:
1342 internal(file_line, "cgen_ldp_stp: invalid arguments %u, %02x, %02x, %02x", size, *arg1, *arg2, *arg3);
1343 return false;
1344 }
1346 static bool attr_w cgen_ic(struct codegen_context *ctx)
1347 {
1348 uint8_t *arg1, *arg2, *arg3;
1349 arg1 = ctx->code_position;
1350 arg2 = arg1 + arg_size(*arg1);
1351 arg3 = arg2 + arg_size(*arg2);
1352 ctx->code_position = arg3 + arg_size(*arg3);
1353 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] != arg1[0]))
1354 goto invl;
1355 g(cgen_rr_rx(ctx, OP_SIZE_4, arg1, arg2, arg3, &codes_ic));
1356 return true;
1357 invl:
1358 internal(file_line, "cgen_ic: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1359 return false;
1360 }
1362 static bool attr_w cgen_mov_mask(struct codegen_context *ctx)
1363 {
1364 it code;
1365 int64_t imm;
1366 uint8_t *arg1, *arg2, *arg3;
1367 arg1 = ctx->code_position;
1368 arg2 = arg1 + arg_size(*arg1);
1369 arg3 = arg2 + arg_size(*arg2);
1370 ctx->code_position = arg3 + arg_size(*arg3);
1371 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] != arg1[0]) || unlikely(arg3[0] != ARG_IMM))
1372 goto invl;
1373 imm = get_imm(&arg3[1]);
1374 code = S390_IIHF;
1375 code |= (it)arg1[1] << 36;
1376 code |= (it)(imm & 0xffffffffLL);
1377 g(cgen_s390(ctx, code));
1378 return true;
1379 invl:
1380 internal(file_line, "cgen_mov_mask: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1381 return false;
1382 }
1384 static bool attr_w cgen_memcpy(struct codegen_context *ctx)
1385 {
1386 it code;
1387 int64_t disp_dest, disp_src, len;
1388 uint8_t *arg1, *arg2, *arg3;
1389 arg1 = ctx->code_position;
1390 arg2 = arg1 + arg_size(*arg1);
1391 arg3 = arg2 + arg_size(*arg2);
1392 ctx->code_position = arg3 + arg_size(*arg3);
1393 if (unlikely(arg1[0] != ARG_ADDRESS_1) || unlikely(arg2[0] != ARG_ADDRESS_1) || unlikely(arg3[0] != ARG_IMM))
1394 goto invl;
1395 disp_dest = get_imm(&arg1[2]);
1396 disp_src = get_imm(&arg2[2]);
1397 len = get_imm(&arg3[1]);
1398 code = S390_MVC;
1399 code |= (it)((len - 1) & 0xff) << 32;
1400 code |= (it)arg1[1] << 28;
1401 code |= (it)(disp_dest & 0xfff) << 16;
1402 code |= (it)arg2[1] << 12;
1403 code |= (it)(disp_src & 0xfff) << 0;
1404 g(cgen_s390(ctx, code));
1405 return true;
1406 invl:
1407 internal(file_line, "cgen_memcpy: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1408 return false;
1409 }
1411 static bool attr_w cgen_fp_cmp(struct codegen_context *ctx, unsigned size)
1412 {
1413 uint8_t *arg1 = ctx->code_position;
1414 uint8_t *arg2 = arg1 + arg_size(*arg1);
1415 ctx->code_position = arg2 + arg_size(*arg2);
1416 if (unlikely(!reg_is_fp(arg1[0])))
1417 goto invl;
1418 g(cgen_fp_op(ctx, size, arg1, arg2, &fp_cmp));
1419 return true;
1420 invl:
1421 internal(file_line, "cgen_fp_cmp: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
1422 return false;
1423 }
1425 static bool attr_w cgen_fp_alu(struct codegen_context *ctx, unsigned size, unsigned aux)
1426 {
1427 uint8_t *arg1 = ctx->code_position;
1428 uint8_t *arg2 = arg1 + arg_size(*arg1);
1429 uint8_t *arg3 = arg2 + arg_size(*arg2);
1430 ctx->code_position = arg3 + arg_size(*arg3);
1431 if (unlikely(!reg_is_fp(arg1[0])) || unlikely(arg1[0] != arg2[0]))
1432 goto invl;
1433 g(cgen_fp_op(ctx, size, arg1, arg3, &fp_alus[aux]));
1434 return true;
1435 invl:
1436 internal(file_line, "cgen_fp_alu: invalid arguments %u, %u, %02x, %02x, %02x", size, aux, *arg1, *arg2, *arg3);
1437 return false;
1438 }
1440 static bool attr_w cgen_fp_alu1(struct codegen_context *ctx, unsigned size, unsigned aux)
1441 {
1442 uint8_t *arg1 = ctx->code_position;
1443 uint8_t *arg2 = arg1 + arg_size(*arg1);
1444 ctx->code_position = arg2 + arg_size(*arg2);
1445 if (unlikely(!reg_is_fp(arg1[0])))
1446 goto invl;
1447 g(cgen_fp_op(ctx, size, arg1, arg2, &fp_alu1s[aux]));
1448 return true;
1449 invl:
1450 internal(file_line, "cgen_fp_alu1: invalid arguments %u, %u, %02x, %02x", size, aux, *arg1, *arg2);
1451 return false;
1452 }
1454 static bool attr_w cgen_fp_to_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1455 {
1456 it code;
1457 uint8_t *arg1 = ctx->code_position;
1458 uint8_t *arg2 = arg1 + arg_size(*arg1);
1459 ctx->code_position = arg2 + arg_size(*arg2);
1460 if (unlikely(arg1[0] >= 0x10) || unlikely(!reg_is_fp(arg2[0])))
1461 goto invl;
1462 switch (fp_op_size) {
1463 case OP_SIZE_4:
1464 code = int_op_size == OP_SIZE_4 ? S390_CFEBR : S390_CGEBR;
1465 break;
1466 case OP_SIZE_8:
1467 code = int_op_size == OP_SIZE_4 ? S390_CFDBR : S390_CGDBR;
1468 break;
1469 case OP_SIZE_16:
1470 code = int_op_size == OP_SIZE_4 ? S390_CFXBR : S390_CGXBR;
1471 break;
1472 default:
1473 goto invl;
1474 }
1475 code |= (it)5 << 28;
1476 code |= (it)arg1[0] << 20;
1477 code |= (it)(arg2[0] & 0xf) << 16;
1478 g(cgen_s390(ctx, code));
1479 return true;
1480 invl:
1481 internal(file_line, "cgen_fp_to_int: invalid arguments %u, %u, %02x, %02x", int_op_size, fp_op_size, *arg1, *arg2);
1482 return false;
1483 }
1485 static bool attr_w cgen_fp_from_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1486 {
1487 it code;
1488 uint8_t *arg1 = ctx->code_position;
1489 uint8_t *arg2 = arg1 + arg_size(*arg1);
1490 ctx->code_position = arg2 + arg_size(*arg2);
1491 if (unlikely(!reg_is_fp(arg1[0])) || unlikely(arg2[0] >= 0x10))
1492 goto invl;
1493 switch (fp_op_size) {
1494 case OP_SIZE_4:
1495 code = int_op_size == OP_SIZE_4 ? S390_CEFBR : S390_CEGBR;
1496 break;
1497 case OP_SIZE_8:
1498 code = int_op_size == OP_SIZE_4 ? S390_CDFBR : S390_CDGBR;
1499 break;
1500 case OP_SIZE_16:
1501 code = int_op_size == OP_SIZE_4 ? S390_CXFBR : S390_CXGBR;
1502 break;
1503 default:
1504 goto invl;
1505 }
1506 code |= (it)(arg1[0] & 0xf) << 20;
1507 code |= (it)arg2[0] << 16;
1508 g(cgen_s390(ctx, code));
1509 return true;
1510 invl:
1511 internal(file_line, "cgen_fp_from_int: invalid arguments %u, %u, %02x, %02x", int_op_size, fp_op_size, *arg1, *arg2);
1512 return false;
1513 }
1515 static bool attr_w cgen_jmp_cond(struct codegen_context *ctx, bool lng, unsigned aux, bool logical)
1516 {
1517 it code;
1518 if (!lng) {
1519 g(add_relocation(ctx, JMP_SHORTEST, 0, NULL));
1520 code = S390_BRC;
1521 } else if (USE_BRCL) {
1522 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1523 code = S390_BRCL;
1524 } else {
1525 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1526 code = S390_BRAS;
1527 code |= (it)R_OFFSET_IMM << 36;
1528 code |= (it)4 << 16;
1529 g(cgen_s390(ctx, code));
1530 cgen_four(0);
1531 #if defined(ARCH_S390_32)
1532 code = S390_L;
1533 #else
1534 code = S390_LGF;
1535 #endif
1536 code |= (it)R_CONST_IMM << 36;
1537 code |= (it)R_OFFSET_IMM << 28;
1538 g(cgen_s390(ctx, code));
1539 code = S390_LA;
1540 code |= (it)R_OFFSET_IMM << 36;
1541 code |= (it)R_OFFSET_IMM << 32;
1542 code |= (it)R_CONST_IMM << 28;
1543 g(cgen_s390(ctx, code));
1544 code = S390_BCR;
1545 code |= (it)R_OFFSET_IMM << 32;
1546 code |= (it)get_jmp_cond(aux, logical) << 36;
1547 g(cgen_s390(ctx, code));
1548 return true;
1549 }
1550 code |= (it)get_jmp_cond(aux, logical) << 36;
1551 g(cgen_s390(ctx, code));
1552 return true;
1553 }
1555 static bool attr_w cgen_jmp_indirect(struct codegen_context *ctx)
1556 {
1557 uint8_t reg = cget_one(ctx);
1558 it code = S390_BCR;
1559 code |= (it)(S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ) << 36;
1560 code |= (it)reg << 32;
1561 g(cgen_s390(ctx, code));
1562 return true;
1563 }
1565 static bool attr_w resolve_relocation(struct codegen_context *ctx, struct relocation *reloc)
1566 {
1567 int64_t offs = ((int64_t)ctx->label_to_pos[reloc->label_id] - (int64_t)(reloc->position)) / 2;
1568 switch (reloc->length) {
1569 case JMP_SHORTEST: {
1570 int16_t i16;
1571 if (unlikely(offs < -0x8000) || unlikely(offs >= 0x8000))
1572 return false;
1573 i16 = offs;
1574 memcpy(ctx->mcode + reloc->position + 2, &i16, 2);
1575 return true;
1576 }
1577 case JMP_SHORT: {
1578 int32_t i32;
1579 if (USE_BRCL) {
1580 if (unlikely(offs < -0x80000000LL) || unlikely(offs >= 0x80000000LL))
1581 return false;
1582 i32 = offs;
1583 memcpy(ctx->mcode + reloc->position + 2, &i32, 4);
1584 return true;
1585 } else {
1586 offs *= 2;
1587 offs -= 4;
1588 if (unlikely(offs < -0x80000000LL) || unlikely(offs >= 0x80000000LL))
1589 return false;
1590 i32 = offs;
1591 memcpy(ctx->mcode + reloc->position + 4, &i32, 4);
1592 return true;
1593 }
1594 }
1595 default: {
1596 internal(file_line, "resolve_relocation: invalid relocation length %u", reloc->length);
1597 return false;
1598 }
1599 }
1600 }
1602 static bool attr_w cgen_insn(struct codegen_context *ctx, uint32_t insn)
1603 {
1604 /*debug("insn: %08x", insn);*/
1605 switch (insn_opcode(insn)) {
1606 case INSN_ENTRY:
1607 g(cgen_entry(ctx));
1608 return true;
1609 case INSN_LABEL:
1610 g(cgen_label(ctx));
1611 return true;
1612 case INSN_RET:
1613 g(cgen_s390(ctx, S390_BCR | ((it)(S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ) << 36) | ((it)R_14 << 32)));
1614 return true;
1615 case INSN_S390_PUSH:
1616 g(cgen_s390_push_pop(ctx, insn_op_size(insn), true));
1617 return true;
1618 case INSN_S390_POP:
1619 g(cgen_s390_push_pop(ctx, insn_op_size(insn), false));
1620 return true;
1621 case INSN_CALL_INDIRECT:
1622 g(cgen_call_indirect(ctx));
1623 return true;
1624 case INSN_MOV:
1625 g(cgen_mov(ctx, insn_op_size(insn)));
1626 return true;
1627 case INSN_MOVSX:
1628 g(cgen_movsx(ctx, insn_op_size(insn)));
1629 return true;
1630 case INSN_CMP:
1631 g(cgen_cmp(ctx, insn_op_size(insn), insn_writes_flags(insn)));
1632 return true;
1633 case INSN_TEST:
1634 if (unlikely(!insn_writes_flags(insn)))
1635 goto invalid_insn;
1636 g(cgen_test(ctx, insn_op_size(insn)));
1637 return true;
1638 case INSN_ALU:
1639 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1640 goto invalid_insn;
1641 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1642 return true;
1643 case INSN_ALU_PARTIAL:
1644 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1645 goto invalid_insn;
1646 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1647 return true;
1648 case INSN_ALU1:
1649 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1650 goto invalid_insn;
1651 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1652 return true;
1653 case INSN_ALU1_PARTIAL:
1654 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1655 goto invalid_insn;
1656 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1657 return true;
1658 case INSN_LEA3:
1659 if (unlikely(insn_op_size(insn) != OP_SIZE_ADDRESS))
1660 goto invalid_insn;
1661 if (unlikely(insn_aux(insn) != 0))
1662 goto invalid_insn;
1663 g(cgen_lea3(ctx));
1664 return true;
1665 case INSN_ROT:
1666 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1667 goto invalid_insn;
1668 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn)));
1669 return true;
1670 case INSN_ROT_PARTIAL:
1671 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1672 goto invalid_insn;
1673 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn)));
1674 return true;
1675 case INSN_MUL_L:
1676 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1677 goto invalid_insn;
1678 g(cgen_mul_l(ctx, insn_op_size(insn)));
1679 return true;
1680 case INSN_DIV_L:
1681 g(cgen_div_l(ctx, insn_op_size(insn), insn_aux(insn)));
1682 return true;
1683 case INSN_CMOV:
1684 case INSN_CMOV_XCC:
1685 if (unlikely(!cpu_test_feature(CPU_FEATURE_misc_45)))
1686 goto invalid_insn;
1687 g(cgen_cmov(ctx, insn_op_size(insn), insn_aux(insn), insn_opcode(insn) == INSN_CMOV_XCC));
1688 return true;
1689 case INSN_STP:
1690 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1691 goto invalid_insn;
1692 g(cgen_ldp_stp(ctx, insn_op_size(insn), true));
1693 return true;
1694 case INSN_LDP:
1695 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1696 goto invalid_insn;
1697 g(cgen_ldp_stp(ctx, insn_op_size(insn), false));
1698 return true;
1699 case INSN_MOV_MASK:
1700 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1701 goto invalid_insn;
1702 if (insn_aux(insn) == MOV_MASK_0_8) {
1703 g(cgen_ic(ctx));
1704 } else if (insn_aux(insn) == MOV_MASK_32_64) {
1705 g(cgen_mov_mask(ctx));
1706 } else {
1707 goto invalid_insn;
1708 }
1709 return true;
1710 case INSN_MEMCPY:
1711 g(cgen_memcpy(ctx));
1712 return true;
1713 case INSN_FP_CMP:
1714 g(cgen_fp_cmp(ctx, insn_op_size(insn)));
1715 return true;
1716 case INSN_FP_ALU:
1717 g(cgen_fp_alu(ctx, insn_op_size(insn), insn_aux(insn)));
1718 return true;
1719 case INSN_FP_ALU1:
1720 g(cgen_fp_alu1(ctx, insn_op_size(insn), insn_aux(insn)));
1721 return true;
1722 case INSN_FP_TO_INT32:
1723 g(cgen_fp_to_int(ctx, OP_SIZE_4, insn_op_size(insn)));
1724 return true;
1725 case INSN_FP_TO_INT64:
1726 g(cgen_fp_to_int(ctx, OP_SIZE_8, insn_op_size(insn)));
1727 return true;
1728 case INSN_FP_FROM_INT32:
1729 g(cgen_fp_from_int(ctx, OP_SIZE_4, insn_op_size(insn)));
1730 return true;
1731 case INSN_FP_FROM_INT64:
1732 g(cgen_fp_from_int(ctx, OP_SIZE_8, insn_op_size(insn)));
1733 return true;
1734 case INSN_JMP:
1735 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, COND_ALWAYS, false));
1736 return true;
1737 case INSN_JMP_COND:
1738 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, insn_aux(insn), false));
1739 return true;
1740 case INSN_JMP_COND_LOGICAL:
1741 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, insn_aux(insn), true));
1742 return true;
1743 case INSN_JMP_INDIRECT:
1744 g(cgen_jmp_indirect(ctx));
1745 return true;
1746 default:
1747 invalid_insn:
1748 internal(file_line, "cgen_insn: invalid insn %08x", insn);
1749 return false;
1750 }
1751 }