| blob | a868237b01571283b754e0dfc692d70fe45e8f28 |
1 From 2c3bca2c3f13a0a9ef71d549a90fba23e6997d44 Mon Sep 17 00:00:00 2001
2 From: "Wang, Pengfei" <pengfei.wang@intel.com>
3 Date: Mon, 5 Jul 2021 21:08:49 +0800
4 Subject: [PATCH] Twist shuffle mask when fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y))
5 -> SHUFFLE(HOP(X,Y))
7 This patch fixes PR50823.
9 The shuffle mask should be twisted twice before gotten the correct one due to the difference between inner HOP and outer.
11 Reviewed By: RKSimon
13 Differential Revision: https://reviews.llvm.org/D104903
15 (cherry picked from commit 9ab99f773fec7da4183495a3fdc655a797d3bea2)
16 ---
17 llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++---
18 llvm/test/CodeGen/X86/haddsub-undef.ll | 4 +--
19 llvm/test/CodeGen/X86/packss.ll | 2 +-
20 llvm/test/CodeGen/X86/pr50823.ll | 35 +++++++++++++++++++++++++
21 4 files changed, 42 insertions(+), 6 deletions(-)
22 create mode 100644 llvm/test/CodeGen/X86/pr50823.ll
24 diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
25 index 1e2407c7e7f6..d8b2f765e953 100644
26 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp
27 +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
28 @@ -43194,9 +43194,10 @@ static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG,
29 ShuffleVectorSDNode::commuteMask(ShuffleMask1);
30 }
31 if ((Op00 == Op10) && (Op01 == Op11)) {
32 - SmallVector<int, 4> ShuffleMask;
33 - ShuffleMask.append(ShuffleMask0.begin(), ShuffleMask0.end());
34 - ShuffleMask.append(ShuffleMask1.begin(), ShuffleMask1.end());
35 + const int Map[4] = {0, 2, 1, 3};
36 + SmallVector<int, 4> ShuffleMask(
37 + {Map[ShuffleMask0[0]], Map[ShuffleMask1[0]], Map[ShuffleMask0[1]],
38 + Map[ShuffleMask1[1]]});
39 SDLoc DL(N);
40 MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
41 SDValue Res = DAG.getNode(Opcode, DL, VT, Op00, Op01);
42 diff --git a/llvm/test/CodeGen/X86/haddsub-undef.ll b/llvm/test/CodeGen/X86/haddsub-undef.ll
43 index 68d058433179..e7c8b84d3bc7 100644
44 --- a/llvm/test/CodeGen/X86/haddsub-undef.ll
45 +++ b/llvm/test/CodeGen/X86/haddsub-undef.ll
46 @@ -1166,7 +1166,7 @@ define <4 x double> @PR34724_add_v4f64_u123(<4 x double> %0, <4 x double> %1) {
47 ; AVX512-FAST: # %bb.0:
48 ; AVX512-FAST-NEXT: vextractf128 $1, %ymm0, %xmm0
49 ; AVX512-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
50 -; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,0,3]
51 +; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3]
52 ; AVX512-FAST-NEXT: retq
53 %3 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 2, i32 4>
54 %4 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 3, i32 5>
55 @@ -1267,7 +1267,7 @@ define <4 x double> @PR34724_add_v4f64_01u3(<4 x double> %0, <4 x double> %1) {
56 ; AVX512-FAST-LABEL: PR34724_add_v4f64_01u3:
57 ; AVX512-FAST: # %bb.0:
58 ; AVX512-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
59 -; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,1,3]
60 +; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3]
61 ; AVX512-FAST-NEXT: retq
62 %3 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 0, i32 2>
63 %4 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 1, i32 3>
64 diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
65 index 16349ae2c7f9..ac431b7556ea 100644
66 --- a/llvm/test/CodeGen/X86/packss.ll
67 +++ b/llvm/test/CodeGen/X86/packss.ll
68 @@ -370,7 +370,7 @@ define <32 x i8> @packsswb_icmp_zero_trunc_256(<16 x i16> %a0) {
69 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
70 ; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
71 ; AVX2-NEXT: vpacksswb %ymm0, %ymm1, %ymm0
72 -; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3]
73 +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,3]
74 ; AVX2-NEXT: ret{{[l|q]}}
75 %1 = icmp eq <16 x i16> %a0, zeroinitializer
76 %2 = sext <16 x i1> %1 to <16 x i16>
77 diff --git a/llvm/test/CodeGen/X86/pr50823.ll b/llvm/test/CodeGen/X86/pr50823.ll
78 new file mode 100644
79 index 000000000000..c5d5296e5c66
80 --- /dev/null
81 +++ b/llvm/test/CodeGen/X86/pr50823.ll
82 @@ -0,0 +1,35 @@
83 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
84 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
85 +
86 +%v8_uniform_FVector3 = type { float, float, float }
87 +
88 +declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
89 +
90 +define void @foo(%v8_uniform_FVector3* %Out, float* %In, <8 x i32> %__mask) {
91 +; CHECK-LABEL: foo:
92 +; CHECK: # %bb.0: # %allocas
93 +; CHECK-NEXT: vmovups (%rsi), %xmm0
94 +; CHECK-NEXT: vhaddps 32(%rsi), %xmm0, %xmm0
95 +; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,1]
96 +; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0
97 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
98 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0
99 +; CHECK-NEXT: vmovss %xmm0, (%rdi)
100 +; CHECK-NEXT: vzeroupper
101 +; CHECK-NEXT: retq
102 +allocas:
103 + %ptr_cast_for_load = bitcast float* %In to <8 x float>*
104 + %ptr_masked_load74 = load <8 x float>, <8 x float>* %ptr_cast_for_load, align 4
105 + %ptr8096 = getelementptr float, float* %In, i64 8
106 + %ptr_cast_for_load81 = bitcast float* %ptr8096 to <8 x float>*
107 + %ptr80_masked_load82 = load <8 x float>, <8 x float>* %ptr_cast_for_load81, align 4
108 + %ret_7.i.i = shufflevector <8 x float> %ptr_masked_load74, <8 x float> %ptr80_masked_load82, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
109 + %Out_load19 = getelementptr %v8_uniform_FVector3, %v8_uniform_FVector3* %Out, i64 0, i32 0
110 + %v1.i.i100 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %ret_7.i.i, <8 x float> %ret_7.i.i)
111 + %v2.i.i101 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %v1.i.i100, <8 x float> %v1.i.i100)
112 + %scalar1.i.i102 = extractelement <8 x float> %v2.i.i101, i32 0
113 + %scalar2.i.i103 = extractelement <8 x float> %v2.i.i101, i32 4
114 + %sum.i.i104 = fadd float %scalar1.i.i102, %scalar2.i.i103
115 + store float %sum.i.i104, float* %Out_load19, align 4
116 + ret void
117 +}