myhdl/conditional_expression.patch

   1 diff -urN myhdl/conversion/_analyze.py myhdl/conversion/_analyze.py
   2 --- myhdl/conversion/_analyze.py        2008-12-21 18:19:52.000000000 +0100
   3 +++ myhdl/conversion/_analyze.py        2008-12-26 02:03:04.000000000 +0100
   4 @@ -274,6 +274,11 @@
   5          if node.else_:
   6              self.visit(node.else_)
   7
   8 +    def visitIfExp(self, node, *args):
   9 +        self.visit(node.test)
  10 +        self.visit(node.then)
  11 +        self.visit(node.else_)
  12 +
  13      def visitPrintnl(self, node, *args):
  14          if node.dest is not None:
  15              self.raiseError(node, _error.NotSupported, "printing to a file with >> syntax")
  16 @@ -700,6 +705,15 @@
  17          if (len(choices) == item1._nritems) or (node.else_ is not None):
  18              node.isFullCase = True
  19
  20 +    def visitIfExp(self, node, *args):
  21 +            self.visit(node.test, *args)
  22 +            self.refStack.push()
  23 +            self.visit(node.then, *args)
  24 +            self.refStack.pop()
  25 +            self.refStack.push()
  26 +            self.visit(node.else_, *args)
  27 +            self.refStack.pop()
  28 +
  29      def visitListComp(self, node, *args):
  30          mem = node.obj = _Ram()
  31          self.visit(node.expr, _access.INPUT, _kind.DECLARATION)
  32 diff -urN myhdl/conversion/_toVHDL.py myhdl/conversion/_toVHDL.py
  33 --- myhdl/conversion/_toVHDL.py 2008-12-23 19:21:05.000000000 +0100
  34 +++ myhdl/conversion/_toVHDL.py 2008-12-26 01:52:23.000000000 +0100
  35 @@ -1105,6 +1105,15 @@
  36          self.write("end if;")
  37
  38
  39 +    def visitIfExp(self, node, *args):
  40 +        self.write("(")
  41 +        self.visit(node.then)
  42 +        self.write(") when (")
  43 +        self.visit(node.test)
  44 +        self.write(") else (")
  45 +        self.visit(node.else_)
  46 +        self.write(")")
  47 +
  48      def visitKeyword(self, node, *args):
  49          self.visit(node.expr)
  50
  51 diff -urN myhdl/conversion/_toVerilog.py myhdl/conversion/_toVerilog.py
  52 --- myhdl/conversion/_toVerilog.py      2008-12-21 18:19:52.000000000 +0100
  53 +++ myhdl/conversion/_toVerilog.py      2008-12-26 01:51:57.000000000 +0100
  54 @@ -833,6 +833,15 @@
  55              self.writeline()
  56              self.write("end")
  57
  58 +    def visitIfExp(self, node, *args):
  59 +        self.write("(")
  60 +        self.visit(node.test)
  61 +        self.write(") ? (")
  62 +        self.visit(node.then)
  63 +        self.write(") : (")
  64 +        self.visit(node.else_)
  65 +        self.write(")")
  66 +
  67      def visitKeyword(self, node, *args):
  68          self.visit(node.expr)
  69