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Add support up to 2.6.31
[bcu1driver.git] / eib-pei16.c
blob017b84f30c004224f39ba92fc36639113fb81019
1 /*
2 eib-pei16.c - Low level EIB driver for BCU 1
3
4 Copyright (C) 2000 Bernd Thallner <bernd@kangaroo.at>
5 Copyright (C) 2005-2008 Martin Koegler <mkoegler@auto.tuwien.ac.at>
6
7 Ported to Linux 2.6 by Robert Kurevija
8 Heavily modfied and restructed by Martin Kögler
9
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License
12 as published by the Free Software Foundation; either version 2
13 of the License, or (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/fs.h>
29 #include <linux/sched.h>
30
31 #include "eib-common.h"
32 #include "eib.h"
33
34 #define EIB_DEBUG 0
35
36 #undef EIB_PRINT
37 #define EIB_PRINT(fmt, args...) printk(KERN_NOTICE "eib: " fmt "\n", ## args)
38
39 #undef PDEBUG
40 #if EIB_DEBUG
41 # define PDEBUG(fmt, args...) printk(KERN_NOTICE "eib: " fmt "\n", ## args)
42 #else
43 # define PDEBUG(fmt, args...) do {} while (0)
44 #endif
45
46 #define EIB_LOG(MSG, args...) do { struct timespec tv; getnstimeofday (&tv); PDEBUG("at %010ld.%09ld " MSG,tv.tv_sec,tv.tv_nsec,##args);tv.tv_nsec--;} while(0)
47
48 static int eib_major = 0;
49
50 module_param (eib_major, int, 0);
51 MODULE_PARM_DESC (eib_major, "Major number for this device.");
52
53 MODULE_AUTHOR ("Martin Kögler, mkoegler@auto.tuwien.ac.at");
54 MODULE_AUTHOR ("Bernd Thallner, bernd@kangaroo.at");
55 MODULE_DESCRIPTION ("A low level EIB driver for BCU 1.");
56 MODULE_LICENSE ("GPL");
57
58 /* maximum time in usec to wait between rx interrupt raised and byte fully send */
59 #define MAX_TEMT_WAIT 1000
60
61 /* minimum time in usec to wait between byte fully send and clear rts signal */
62 #define WRITE_TEMT_CLRRTS_DELAY 100
63
64 /* minimum time in usec to wait between clear rts and set rts signal */
65 #define WRITE_CLRRTS_SETRTS_DELAY 80
66
67 /* timeout for data block transfer */
68 #define READ_WRITE_TIMEOUT 130000
69
70 /* maximum time between to interrupts if not in idle state */
71 #define MAX_TIME_BETWEEN_INT 80000
72
73 /* minimum time to wait after reset without any respond to signals */
74 #define MIN_RESET_WAIT_TIME 130000
75
76 /* maximum time between to wait for start sending */
77 #define MAX_INIT_SEND_TIMEOUT 100000
78
79 /* time to start transmission */
80 #define MAX_INIT_SEND_TIME 3000
81
82 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
83
84 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
85 #define HRTIMER_MODE_REL HRTIMER_REL
86 #endif
87
88 #include <linux/hrtimer.h>
89 #include <linux/ktime.h>
90
91 typedef struct eib_timer eib_timer;
92 typedef void (*eib_timer_func) (eib_timer * timer);
93
94 struct eib_timer
95 {
96 struct hrtimer tl;
97 eib_timer_func func;
98 };
99
100 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
101 static int
102 eib_timer_run (struct hrtimer *data)
103 #else
104 static enum hrtimer_restart
105 eib_timer_run (struct hrtimer *data)
106 #endif
107 {
108 eib_timer *t = container_of (data, eib_timer, tl);
109 t->func (t);
110 return HRTIMER_NORESTART;
111 }
112
113 static inline void
114 init_eib_timer (eib_timer * timer, eib_timer_func func)
115 {
116 hrtimer_init (&timer->tl, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
117 timer->func = func;
118 timer->tl.function = eib_timer_run;
119 }
120
121 static inline void
122 start_eib_timer (eib_timer * timer, unsigned long usec_offset)
123 {
124 if (!usec_offset)
125 usec_offset = 1;
126 hrtimer_start (&timer->tl, ktime_set (0, usec_offset * 1000),
127 HRTIMER_MODE_REL);
128 }
129
130 static inline void
131 stop_eib_timer (eib_timer * timer)
132 {
133 hrtimer_try_to_cancel (&timer->tl);
134 }
135
136 static inline void
137 destroy_eib_timer (eib_timer * timer)
138 {
139 hrtimer_cancel (&timer->tl);
140 }
141
142 #else
143
144 typedef struct eib_timer eib_timer;
145 typedef void (*eib_timer_func) (eib_timer * timer);
146
147 struct eib_timer
148 {
149 struct timer_list tl;
150 eib_timer_func func;
151 };
152
153 static void
154 eib_timer_run (unsigned long data)
155 {
156 eib_timer *t = (eib_timer *) data;
157 t->func (t);
158 }
159
160 static inline void
161 init_eib_timer (eib_timer * timer, eib_timer_func func)
162 {
163 init_timer (&timer->tl);
164 timer->func = func;
165 timer->tl.function = eib_timer_run;
166 timer->tl.data = (unsigned long int) (void *) timer;
167 }
168
169 static inline void
170 start_eib_timer (eib_timer * timer, unsigned long usec_offset)
171 {
172 mod_timer (&timer->tl,
173 usec_offset ? jiffies +
174 usecs_to_jiffies (usec_offset) : jiffies + 1);
175 }
176
177 static inline void
178 stop_eib_timer (eib_timer * timer)
179 {
180 del_timer (&timer->tl);
181 }
182
183 static inline void
184 destroy_eib_timer (eib_timer * timer)
185 {
186 del_timer_sync (&timer->tl);
187 }
188
189 #endif
190
191 struct eib_protocol_data
192 {
193 eib_chardev *cdev;
194 int minor;
195 spinlock_t lock;
196 int shutdown;
197 eib_port *iface;
198 eib_lowlevel *dev;
199
200 int read_pos;
201 int write_pos;
202
203 eib_timer initate_send_timer;
204 eib_timer detect_reset_timer;
205 eib_timer write_timer;
206
207 struct timespec last_int_tv;
208 struct timespec start_tv;
209 struct timespec send_tv;
210 struct timespec reset_tv;
211 volatile int state;
212 volatile int initate_send;
213 int reset_count;
214 };
215
216 static int
217 bitcount (unsigned char x)
218 {
219 int b;
220
221 for (b = 0; x != 0; x >>= 1)
222 if (x & 01)
223 b++;
224
225 return b;
226 }
227
228 static long
229 time_difference (struct timespec *tv1, struct timespec *tv2)
230 {
231 struct timespec foo;
232
233 if (tv2 == NULL)
234 {
235 getnstimeofday (&foo);
236 tv2 = &foo;
237 }
238
239 return (tv2->tv_nsec - tv1->tv_nsec) / 1000 + /* usecs */
240 1000000 * (tv2->tv_sec - tv1->tv_sec); /* seconds * 1000000 */
241 }
242
243 static void
244 add_initate_send_timer (eib_protocol_data * dev)
245 {
246 long t1, t2;
247 if (dev->shutdown)
248 {
249 return;
250 }
251 t1 = MAX_INIT_SEND_TIME - time_difference (&dev->last_int_tv, NULL);
252 t2 = MAX_INIT_SEND_TIMEOUT - time_difference (&dev->send_tv, NULL);
253 EIB_LOG ("add_initate_send: %ld %ld", t1, t2);
254 if (t1 < 0)
255 t1 = 0;
256 if (t2 < 0)
257 t2 = 0;
258
259 if (t2 < t1)
260 t1 = t2;
261 start_eib_timer (&dev->initate_send_timer, t1);
262 }
263
264 static void
265 add_detect_reset_timer (eib_protocol_data * dev)
266 {
267 long t1;
268 if (dev->shutdown)
269 {
270 return;
271 }
272 if (dev->state == 7)
273 {
274 t1 = MIN_RESET_WAIT_TIME - time_difference (&dev->reset_tv, NULL);
275 EIB_LOG ("add_detect_reset: %ld", t1);
276 if (t1 < 0)
277 t1 = 0;
278 }
279 else
280 {
281 long t2;
282 t1 = READ_WRITE_TIMEOUT - time_difference (&dev->start_tv, NULL);
283 t2 = MAX_TIME_BETWEEN_INT - time_difference (&dev->last_int_tv, NULL);
284 EIB_LOG ("add_detect_reset: %ld %ld", t1, t2);
285 if (t1 < 0)
286 t1 = 0;
287 if (t2 < 0)
288 t2 = 0;
289 if (t2 < t1)
290 t1 = t2;
291 }
292
293 start_eib_timer (&dev->detect_reset_timer, t1);
294 }
295
296 static void
297 add_write_timer (eib_protocol_data * dev, long timeout)
298 {
299 if (dev->shutdown)
300 {
301 return;
302 }
303 EIB_LOG ("add_write_timer: %ld", timeout);
304 start_eib_timer (&dev->write_timer, timeout);
305 }
306
307 static void
308 do_reset1 (eib_protocol_data * dev, unsigned long reason, const char *msg,
309 int line)
310 {
311
312 EIB_PRINT
313 ("do_reset: state=%d, reason=%lx, initate_send=%d, getCTS()=%d, %s at %d",
314 dev->state, reason, dev->initate_send, dev->iface->getCTS (dev->dev),
315 msg, line);
316
317 dev->state = 7;
318 dev->iface->getserialint (dev->dev);
319 dev->iface->recv (dev->dev);
320 dev->iface->getCTS (dev->dev); /* clear MSR Delta */
321 getnstimeofday (&dev->reset_tv);
322 dev->iface->clrRTS (dev->dev);
323 }
324
325 #define do_reset(dev, MSG) do_reset1(dev, MSG , __LINE__)
326
327 #define ERR_1 0x00000001 , "no interrupt pending"
328 #define ERR_2 0x00000002 , "unexpected receive data interrupt"
329 #define ERR_4 0x00000004 , "unexpected receive data interrupt"
330 #define ERR_8 0x00000008 , "unexpected cts change to high"
331 #define ERR_10 0x00000010 , "read buffer overflow"
332 #define ERR_20 0x00000020 , "unexpected cts change to high"
333 #define ERR_40 0x00000040 , "unknown state"
334 #define ERR_80 0x00000080 , "overrun"
335 #define ERR_100 0x00000100 , "read forced"
336 #define ERR_200 0x00000200 , "unexpected receive data interrupt"
337 #define ERR_400 0x00000400 , "parity error"
338 #define ERR_800 0x00000800 , "unexpected receive data interrupt"
339 #define ERR_1000 0x00001000 , "exceed MAX_TEMT_WAIT"
340 #define ERR_2000 0x00002000 , "unexpected byte received"
341 #define ERR_4000 0x00004000 , "read forced && read buffer full"
342 #define ERR_8000 0x00008000 , "unexpected cts change"
343 #define ERR_10000 0x00010000 , "initate send with empty write buffer"
344 #define ERR_20000 0x00020000 , "bcu reset (info)"
345 #define ERR_40000 0x00040000 , "unexpected receive data interrupt"
346 #define ERR_80000 0x00080000 , "unexpected cts change to high"
347 #define ERR_100000 0x00100000 , "READ_WRITE_TIMEOUT"
348 #define ERR_200000 0x00200000 , "exceed MAX_TIME_BETWEEN_INT"
349 #define ERR_400000 0x00400000 , "clear write buffer"
350 #define ERR_800000 0x00800000 , "BCU reset"
351 #define ERR_10000000 0x10000000 , "INITIATESEND"
352
353 static void
354 check_interrupt_pending (eib_protocol_data * dev)
355 {
356 switch (dev->iface->getserialint (dev->dev))
357 {
358 case EIB_INT_DATA:
359 do_reset (dev, ERR_40000); // unexpected receive data interrupt
360 break;
361 case EIB_INT_MSR:
362 if (dev->iface->getCTS (dev->dev))
363 do_reset (dev, ERR_80000); // unexpected cts change to high
364 break;
365 default:
366 break;
367 }
368 }
369
370 static void
371 eib_handler (eib_protocol_data * dev, enum eib_reason reason)
372 {
373 unsigned long flags;
374 int tmp;
375
376 EIB_LOG ("Handler %d %d %d", reason, dev->state,
377 dev->iface->getCTS (dev->dev));
378
379 switch (dev->state)
380 { /* State machine state */
381 case 0:
382 switch (reason)
383 {
384 case EIB_INT_DATA:
385 do_reset (dev, ERR_2); /* unexpected receive data interrupt */
386 break;
387 case EIB_INT_MSR:
388 if (dev->iface->getCTS (dev->dev))
389 {
390 if (dev->initate_send)
391 { /* write to bcu */
392 dev->iface->send (dev->dev, eib_writebuffer (dev->cdev)[0]);
393 dev->initate_send = 0;
394 dev->write_pos++;
395 dev->state = 5;
396
397 break;
398 }
399 else
400 { // read
401 add_detect_reset_timer (dev);
402 if (eib_readbuffer_full (dev->cdev))
403 {
404 do_reset (dev, ERR_10); /* read buffer overflow */
405 }
406 else
407 {
408 getnstimeofday (&dev->start_tv);
409 dev->iface->setRTS (dev->dev);
410 dev->iface->send (dev->dev, 0xFF);
411 dev->state = 2;
412 }
413 }
414 } // else !getCTS() -> state=0
415 break;
416 case EIB_TIME_RESET:
417 break;
418 case EIB_TIME_SEND:
419 break;
420 case EIB_TIME_WRITE:
421 do_reset (dev, ERR_40); /* unknown state */
422 break;
423 case EIB_OTHER:
424 case EIB_NONE:
425 break;
426 }
427 break;
428 case 1:
429 switch (reason)
430 {
431 case EIB_INT_DATA:
432 do_reset (dev, ERR_200); // unexpected receive data interrupt
433 break;
434 case EIB_INT_MSR:
435 if (dev->iface->getCTS (dev->dev))
436 {
437 dev->iface->setRTS (dev->dev);
438 dev->iface->send (dev->dev, 0x00);
439 dev->state = 2;
440 add_detect_reset_timer (dev);
441 } // else !getCTS() -> state=1
442 break;
443 case EIB_TIME_RESET:
444 break;
445 case EIB_TIME_SEND:
446 break;
447 case EIB_TIME_WRITE:
448 do_reset (dev, ERR_40); /* unknown state */
449 break;
450 case EIB_OTHER:
451 case EIB_NONE:
452 break;
453 }
454 break;
455 case 2:
456 switch (reason)
457 {
458 case EIB_INT_DATA:
459 tmp = dev->iface->recv (dev->dev);
460 eib_readbuffer (dev->cdev)[dev->read_pos++] = tmp;
461 if (dev->iface->overrun (dev->dev))
462 {
463 do_reset (dev, ERR_80); // overrun
464 break;
465 }
466 if (tmp == 0xA0 && dev->read_pos == 1)
467 {
468 eib_readbuffer (dev->cdev)[0] = 1;
469 eib_readbuffer (dev->cdev)[1] = tmp;
470 eib_read_notify (dev->cdev);
471 do_reset (dev, ERR_800000); // BCU reset
472 break;
473 }
474
475 if (tmp == 0xFF && dev->read_pos == 1)
476 {
477 EIB_PRINT ("No data");
478 dev->state = 0;
479 check_interrupt_pending (dev);
480 dev->iface->clrRTS (dev->dev);
481 dev->read_pos = 0;
482
483 getnstimeofday (&dev->last_int_tv);
484 break;
485 }
486
487 if (dev->read_pos == 1 && !(((tmp & 0x60) == 0x20) &&
488 ((tmp & 0x80) ==
489 (bitcount (tmp & 0x7f) % 2) * 0x80)))
490 {
491 do_reset (dev, ERR_400); // parity error
492 break;
493 }
494
495 dev->state = 3;
496 break;
497 case EIB_INT_MSR:
498 if (dev->iface->getCTS (dev->dev))
499 do_reset (dev, ERR_20); /* unexpected cts change to high */
500 break;
501 case EIB_TIME_RESET:
502 break;
503 case EIB_TIME_SEND:
504 break;
505 case EIB_TIME_WRITE:
506 do_reset (dev, ERR_40); /* unknown state */
507 break;
508 case EIB_OTHER:
509 case EIB_NONE:
510 break;
511 }
512 break;
513 case 3:
514 switch (reason)
515 {
516 case EIB_INT_DATA:
517 do_reset (dev, ERR_4); /* unexpected receive data interrupt */
518 break;
519 case EIB_INT_MSR:
520 if (dev->iface->getCTS (dev->dev))
521 {
522 do_reset (dev, ERR_8); /* unexpected cts change to high */
523 break;
524 }
525 if (dev->read_pos == (eib_readbuffer (dev->cdev)[0] & 0x1f) + 1)
526 { // read finished
527
528 if (eib_readbuffer (dev->cdev)[0] == 0xa0)
529 {
530 eib_readbuffer (dev->cdev)[0] = 1;
531 eib_readbuffer (dev->cdev)[0] = 0xa0;
532 eib_read_notify (dev->cdev);
533 EIB_PRINT ("BCU reset");
534 }
535 else
536 {
537 dev->reset_count = 0;
538 eib_readbuffer (dev->cdev)[0] &= 0x1f;
539 eib_read_notify (dev->cdev);
540 }
541
542 dev->read_pos = 0;
543
544 spin_lock_irqsave (&dev->lock, flags);
545
546 if (!eib_writebuffer_empty (dev->cdev))
547 {
548 getnstimeofday (&dev->send_tv);
549 add_initate_send_timer (dev);
550 }
551 dev->state = 0;
552 }
553 else
554 {
555 spin_lock_irqsave (&dev->lock, flags);
556 dev->state = 1;
557 }
558 check_interrupt_pending (dev);
559 dev->iface->clrRTS (dev->dev);
560
561 spin_unlock_irqrestore (&dev->lock, flags);
562
563 getnstimeofday (&dev->last_int_tv);
564 break;
565 case EIB_TIME_RESET:
566 break;
567 case EIB_TIME_SEND:
568 break;
569 case EIB_TIME_WRITE:
570 break;
571 case EIB_OTHER:
572 case EIB_NONE:
573 break;
574 }
575 break;
576 case 4:
577 switch (reason)
578 {
579 case EIB_INT_DATA:
580 do_reset (dev, ERR_800); /* unexpected receive data interrupt */
581 break;
582 case EIB_INT_MSR:
583 if (dev->iface->getCTS (dev->dev))
584 {
585 dev->iface->send (dev->dev,
586 eib_writebuffer (dev->cdev)[dev->
587 write_pos++]);
588 dev->state = 5;
589 add_detect_reset_timer (dev);
590 } // else !getCTS() -> state=4
591 break;
592 case EIB_TIME_RESET:
593 break;
594 case EIB_TIME_SEND:
595 break;
596 case EIB_TIME_WRITE:
597 do_reset (dev, ERR_40); /* unknown state */
598 break;
599 case EIB_OTHER:
600 case EIB_NONE:
601 break;
602 }
603 break;
604 case 5:
605 switch (reason)
606 {
607 case EIB_INT_DATA:
608 tmp = dev->iface->recv (dev->dev);
609
610 dev->state = 6;
611
612 if (dev->iface->overrun (dev->dev))
613 {
614 do_reset (dev, ERR_80); /* overun */
615 break;
616 }
617 if (dev->write_pos == 1 && tmp == 0xA0)
618 {
619 eib_readbuffer (dev->cdev)[1] = tmp;
620 eib_readbuffer (dev->cdev)[0] = 1;
621 eib_read_notify (dev->cdev);
622 do_reset (dev, ERR_800000); // BCU reset
623 break;
624 }
625
626 if (dev->write_pos == 1 && tmp != 0xff)
627 {
628 dev->write_pos = 0;
629 if (eib_readbuffer_full (dev->cdev))
630 {
631 do_reset (dev, ERR_4000); /* read forced && read buffer full */
632
633 break;
634 }
635
636 if (((tmp & 0x60) != 0x20) ||
637 ((tmp & 0x80) != (bitcount (tmp & 0x7f) % 2) * 0x80))
638 {
639 do_reset (dev, ERR_400); /* parity error */
640
641 break;
642 }
643 eib_readbuffer (dev->cdev)[dev->read_pos++] = tmp;
644
645 dev->state = 3;
646 break;
647 }
648 if (dev->write_pos > 1 && tmp != 0x00)
649 {
650 do_reset (dev, ERR_2000); /* unexpect byte received */
651 break;
652 }
653 add_write_timer (dev, MAX_TEMT_WAIT + WRITE_TEMT_CLRRTS_DELAY);
654 break;
655 case EIB_INT_MSR:
656 do_reset (dev, ERR_8000); /* unexpected cts change */
657 break;
658 case EIB_TIME_RESET:
659 break;
660 case EIB_TIME_SEND:
661 break;
662 case EIB_TIME_WRITE:
663 do_reset (dev, ERR_40); /* unknown state */
664 break;
665 case EIB_OTHER:
666 case EIB_NONE:
667 break;
668 }
669 break;
670 case 6:
671 switch (reason)
672 {
673 case EIB_INT_DATA:
674 do_reset (dev, ERR_4); /* unexpected receive data interrupt */
675 break;
676 case EIB_INT_MSR:
677 if (dev->iface->getCTS (dev->dev))
678 do_reset (dev, ERR_8); /* unexpected cts change to high */
679 break;
680 case EIB_TIME_RESET:
681 break;
682 case EIB_TIME_SEND:
683 break;
684 case EIB_TIME_WRITE:
685 if (!dev->iface->send_finished (dev->dev))
686 {
687 do_reset (dev, ERR_1000); // exceed MAX_TEMT_WAIT
688 return;
689 }
690
691 if (dev->write_pos == (eib_writebuffer (dev->cdev)[0] & 0x1f) + 1)
692 { // write finished
693 dev->reset_count = 0;
694 eib_write_finish (dev->cdev, 1);
695 dev->write_pos = 0;
696
697 if (!eib_writebuffer_empty (dev->cdev))
698 {
699 getnstimeofday (&dev->send_tv);
700 add_initate_send_timer (dev);
701 }
702
703 spin_lock_irqsave (&dev->lock, flags);
704
705
706 dev->state = 0;
707
708 check_interrupt_pending (dev);
709 dev->iface->clrRTS (dev->dev);
710 spin_unlock_irqrestore (&dev->lock, flags);
711 }
712 else
713 {
714 check_interrupt_pending (dev);
715
716 dev->iface->clrRTS (dev->dev);
717
718 spin_lock_irqsave (&dev->lock, flags);
719 dev->state = 8;
720 add_write_timer (dev, WRITE_CLRRTS_SETRTS_DELAY);
721 spin_unlock_irqrestore (&dev->lock, flags);
722 }
723
724 getnstimeofday (&dev->last_int_tv);
725 break;
726 case EIB_OTHER:
727 case EIB_NONE:
728 break;
729 }
730 break;
731 case 7:
732 switch (reason)
733 {
734 case EIB_INT_DATA:
735 dev->iface->recv (dev->dev);
736 break;
737 case EIB_INT_MSR:
738 dev->iface->getCTS (dev->dev);
739 break;
740 case EIB_TIME_RESET:
741 break;
742 case EIB_TIME_SEND:
743 break;
744 case EIB_TIME_WRITE:
745 break;
746 case EIB_OTHER:
747 case EIB_NONE:
748 break;
749 }
750 break;
751 case 8:
752 switch (reason)
753 {
754 case EIB_INT_DATA:
755 do_reset (dev, ERR_4); /* unexpected receive data interrupt */
756 break;
757 case EIB_INT_MSR:
758 if (dev->iface->getCTS (dev->dev))
759 do_reset (dev, ERR_8); /* unexpected cts change to high */
760 stop_eib_timer (&dev->write_timer);
761 goto rt2;
762 break;
763 case EIB_TIME_RESET:
764 break;
765 case EIB_TIME_SEND:
766 break;
767 case EIB_TIME_WRITE:
768 rt2:
769 spin_lock_irqsave (&dev->lock, flags);
770
771 dev->state = 4;
772
773 dev->iface->setRTS (dev->dev);
774 check_interrupt_pending (dev);
775 spin_unlock_irqrestore (&dev->lock, flags);
776
777 getnstimeofday (&dev->last_int_tv);
778 break;
779 case EIB_OTHER:
780 case EIB_NONE:
781 break;
782 }
783 break;
784 default:
785 do_reset (dev, ERR_40); // unknown state
786 }
787 }
788
789 static void
790 write_timer (eib_timer * timer)
791 {
792 eib_protocol_data *proto =
793 container_of (timer, eib_protocol_data, write_timer);
794
795 eib_handler (proto, EIB_TIME_WRITE);
796 }
797
798 static void
799 detect_reset_timer (eib_timer * timer)
800 {
801 eib_protocol_data *dev =
802 container_of (timer, eib_protocol_data, detect_reset_timer);
803 unsigned long flags;
804
805 spin_lock_irqsave (&dev->lock, flags);
806
807 EIB_LOG ("detect_reset %d %d", dev->state, dev->iface->getCTS (dev->dev));
808
809 if (dev->state == 0 && !dev->initate_send && !dev->iface->getCTS (dev->dev))
810 { // idle
811
812 spin_unlock_irqrestore (&dev->lock, flags);
813
814 return;
815 }
816 else if (dev->state == 7)
817 { // reset
818 if (time_difference (&dev->reset_tv, NULL) > MIN_RESET_WAIT_TIME)
819 {
820 getnstimeofday (&dev->last_int_tv);
821 if (!eib_writebuffer_empty (dev->cdev) && dev->reset_count > 10)
822 {
823 dev->reset_count = 0;
824 EIB_PRINT ("discard packet");
825 eib_write_finish (dev->cdev, -1);
826 }
827 if (!eib_writebuffer_empty (dev->cdev))
828 {
829 getnstimeofday (&dev->send_tv);
830 add_initate_send_timer (dev);
831 }
832 dev->read_pos = 0;
833 dev->write_pos = 0;
834 dev->state = 0;
835 dev->reset_count++;
836 spin_unlock_irqrestore (&dev->lock, flags);
837
838 return;
839 }
840 }
841 else
842 { // read || write
843 if (time_difference (&dev->start_tv, NULL) > READ_WRITE_TIMEOUT)
844 do_reset (dev, ERR_100000); // read write timeout
845 else if (time_difference (&dev->last_int_tv, NULL) >
846 MAX_TIME_BETWEEN_INT)
847 do_reset (dev, ERR_200000); // max time between int exceeded
848 }
849 add_detect_reset_timer (dev);
850
851 spin_unlock_irqrestore (&dev->lock, flags);
852 }
853
854 static void
855 initate_send_timer (eib_timer * timer)
856 {
857 eib_protocol_data *dev =
858 container_of (timer, eib_protocol_data, initate_send_timer);
859 unsigned long flags;
860
861 EIB_LOG ("Initiate_Send %d %d", dev->state, dev->iface->getCTS (dev->dev));
862
863 if (eib_writebuffer_empty (dev->cdev))
864 {
865 EIB_PRINT ("initate send with empty buffer");
866 return;
867 }
868
869 spin_lock_irqsave (&dev->lock, flags);
870
871 if (dev->state == 0 && !dev->iface->getCTS (dev->dev) &&
872 time_difference (&dev->last_int_tv, NULL) > MAX_INIT_SEND_TIME)
873 {
874
875 dev->initate_send = 1;
876 getnstimeofday (&dev->start_tv);
877 getnstimeofday (&dev->last_int_tv);
878
879 dev->iface->setRTS (dev->dev);
880 add_detect_reset_timer (dev);
881
882 spin_unlock_irqrestore (&dev->lock, flags);
883
884 return;
885 }
886 if (time_difference (&dev->send_tv, NULL) > MAX_INIT_SEND_TIMEOUT)
887 {
888 EIB_PRINT ("timeout initiate send");
889
890 do_reset (dev, ERR_10000000);
891 add_detect_reset_timer (dev);
892
893 spin_unlock_irqrestore (&dev->lock, flags);
894
895 return;
896 }
897
898 add_initate_send_timer (dev);
899
900 spin_unlock_irqrestore (&dev->lock, flags);
901 }
902
903 static void
904 bcu_interrupt_handler (void *data, enum eib_reason reason)
905 {
906 eib_protocol_data *dev = (eib_protocol_data *) data;
907
908 eib_handler (dev, reason);
909
910 if (dev->state != 0 && dev->state != 7 &&
911 time_difference (&dev->start_tv, NULL) > READ_WRITE_TIMEOUT)
912 do_reset (dev, ERR_100000); /* read write timeout */
913
914 getnstimeofday (&dev->last_int_tv);
915 }
916
917 static int
918 eib_write_prepare (eib_protocol_data * proto, eib_buffer buf, int len)
919 {
920 int temp;
921
922 if (len > 31)
923 {
924 return -EINVAL;
925 }
926
927 temp = (len & 0x1f) | 0x20;
928 buf[0] = temp | (bitcount (temp) % 2) * 0x80;
929 return 0;
930 }
931
932 static void
933 eib_write_start (eib_protocol_data * proto)
934 {
935 unsigned long flags;
936 spin_lock_irqsave (&proto->lock, flags);
937 getnstimeofday (&proto->send_tv);
938 add_initate_send_timer (proto);
939
940 spin_unlock_irqrestore (&proto->lock, flags);
941 }
942
943 #define EIB_BCU_VERSION 1 /* eib bcu version */
944
945 static int
946 eib_proto_ioctl (eib_protocol_data * dev, unsigned int cmd, unsigned long arg)
947 {
948 switch (cmd)
949 {
950
951 case EIB_GET_BCU_VERSION:
952 return EIB_BCU_VERSION;
953
954 case EIB_GET_DEVICE_INFORMATION:
955 break;
956
957 case EIB_RESET_DEVICE_STATISTIC:
958 break;
959
960 case EIB_CLEAR_WRITE_BUFFER:
961 eib_writebuffer_clear (dev->cdev);
962
963 stop_eib_timer (&dev->initate_send_timer);
964 add_detect_reset_timer (dev);
965 dev->initate_send = 0;
966 do_reset (dev, ERR_400000);
967
968 break;
969
970 case EIB_CLEAR_READ_BUFFER:
971 eib_readbuffer_clear (dev->cdev);
972
973 stop_eib_timer (&dev->initate_send_timer);
974 add_detect_reset_timer (dev);
975 do_reset (dev, ERR_400000);
976
977 break;
978
979 case EIB_SINGLE_OPEN:
980 break;
981
982 default:
983 return -ENOIOCTLCMD;
984 }
985
986 return 0;
987 }
988
989 static eib_protocol_data *
990 eib_proto_create (int minor, eib_chardev * cdev)
991 {
992 eib_protocol_data *dev;
993 unsigned long flags;
994 int retval;
995
996 EIB_PRINT ("open serial %d", minor);
997 dev = (void *) kmalloc (sizeof (eib_protocol_data), GFP_KERNEL);
998 if (!dev)
999 return ERR_PTR (-ENOMEM);
1000
1001 memset (dev, 0, sizeof (eib_protocol_data));
1002 dev->cdev = cdev;
1003 spin_lock_init (&dev->lock);
1004 dev->minor = minor;
1005
1006 dev->dev =
1007 eib_port_create (minor, "eib", bcu_interrupt_handler, dev, &dev->iface);
1008 if (IS_ERR (dev->dev))
1009 {
1010 retval = PTR_ERR (dev->dev);
1011 goto outmem;
1012 }
1013
1014 spin_lock_irqsave (&dev->lock, flags);
1015 init_eib_timer (&dev->initate_send_timer, initate_send_timer);
1016 init_eib_timer (&dev->detect_reset_timer, detect_reset_timer);
1017 init_eib_timer (&dev->write_timer, write_timer);
1018
1019 dev->read_pos = 0;
1020 dev->write_pos = 0;
1021 dev->minor = minor;
1022
1023 dev->state = 0;
1024 dev->initate_send = 0;
1025 dev->reset_count = 0;
1026 getnstimeofday (&dev->last_int_tv);
1027
1028 dev->iface->open_port (dev->dev);
1029 spin_unlock_irqrestore (&dev->lock, flags);
1030
1031 EIB_PRINT ("resouces allocated %d", dev->minor);
1032 return dev;
1033
1034 outmem:
1035 kfree (dev);
1036 return ERR_PTR (retval);
1037 }
1038
1039 static void
1040 eib_proto_shutdown (eib_protocol_data * dev)
1041 {
1042 PDEBUG ("close %d", dev->minor);
1043 dev->shutdown = 1;
1044 }
1045
1046 static void
1047 eib_proto_free (eib_protocol_data * dev)
1048 {
1049 unsigned long flags;
1050 spin_lock_irqsave (&dev->lock, flags);
1051 dev->iface->close_port (dev->dev);
1052 dev->iface->free_serial (dev->dev);
1053
1054 destroy_eib_timer (&dev->initate_send_timer);
1055 destroy_eib_timer (&dev->write_timer);
1056 destroy_eib_timer (&dev->detect_reset_timer);
1057
1058 spin_unlock_irqrestore (&dev->lock, flags);
1059 kfree (dev);
1060 PDEBUG ("closed %d", dev->minor);
1061 }
1062
1063 static eib_protocol_ops eib_proto_ops = {
1064 .write_prepare = eib_write_prepare,
1065 .write_start = eib_write_start,
1066 .ioctl = eib_proto_ioctl,
1067 .shutdown = eib_proto_shutdown,
1068 .free = eib_proto_free,
1069 .create = eib_proto_create,
1070 .owner = THIS_MODULE,
1071 };
1072
1073 static int __init
1074 eib_pei16_init (void)
1075 {
1076 int retval;
1077
1078 retval = eib_driver_register ("eib", eib_major, &eib_proto_ops);
1079 if (retval < 0)
1080 return retval;
1081
1082 EIB_PRINT ("pei16 driver loaded (%d)", eib_major);
1083
1084 return 0;
1085 }
1086
1087 static void __exit
1088 eib_pei16_cleanup (void)
1089 {
1090 eib_driver_unregister ("eib");
1091 EIB_PRINT ("pei16 driver successfully unloaded!\n");
1092 }
1093
1094 module_init (eib_pei16_init);
1095 module_exit (eib_pei16_cleanup);
Linux kernel driver for EIB BCU1 compatible interfaces (PEI16)