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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal.h
blob98a534ee7d6bf72901fb451fd4e236700ba9e6f3
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal.h
4 * @author MCD Application Team
5 * @brief This file contains all the functions prototypes for the HAL
6 * module driver.
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef __STM32F3xx_HAL_H
39 #define __STM32F3xx_HAL_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f3xx_hal_conf.h"
47
48 /** @addtogroup STM32F3xx_HAL_Driver
49 * @{
50 */
51
52 /** @addtogroup HAL
53 * @{
54 */
55
56 /* Private macros ------------------------------------------------------------*/
57 /** @addtogroup HAL_Private_Macros
58 * @{
59 */
60 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
61 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
62 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
63 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
64 /**
65 * @}
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup HAL_Exported_Constants HAL Exported Constants
71 * @{
72 */
73 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
74 * @brief SYSCFG registers bit address in the alias region
75 * @{
76 */
77 /* ------------ SYSCFG registers bit address in the alias region -------------*/
78 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
79 /* --- CFGR2 Register ---*/
80 /* Alias word address of BYP_ADDR_PAR bit */
81 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
82 #define BYPADDRPAR_BitNumber 0x04U
83 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
84 /**
85 * @}
86 */
87
88 #if defined(SYSCFG_CFGR1_DMA_RMP)
89 /** @defgroup HAL_DMA_Remapping HAL DMA Remapping
90 * Elements values convention: 0xXXYYYYYY
91 * - YYYYYY : Position in the register
92 * - XX : Register index
93 * - 00: CFGR1 register in SYSCFG
94 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
95 * @{
96 */
97 #define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
98 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
99 #define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
100 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
101 #define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
102 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
103 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
104 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
105 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
106 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
107 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
108 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
109 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
110 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
111 #if defined(SYSCFG_CFGR3_DMA_RMP)
112 #if !defined(HAL_REMAP_CFGR3_MASK)
113 #define HAL_REMAP_CFGR3_MASK (0x01000000U)
114 #endif
115
116 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
117 11: Map on DMA1 channel 2 */
118 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
119 01: Map on DMA1 channel 4 */
120 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
121 10: Map on DMA1 channel 6 */
122 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
123 11: Map on DMA1 channel 3 */
124 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
125 01: Map on DMA1 channel 5 */
126 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
127 10: Map on DMA1 channel 7 */
128 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
129 11: Map on DMA1 channel 7 */
130 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
131 01: Map on DMA1 channel 3 */
132 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
133 10: Map on DMA1 channel 5 */
134 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
135 11: Map on DMA1 channel 6 */
136 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
137 01: Map on DMA1 channel 2 */
138 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
139 10: Map on DMA1 channel 4 */
140 #define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
141 x0: No remap (ADC2 on DMA2)
142 10: Map on DMA1 channel 2 */
143 #define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
144 11: Map on DMA1 channel 4 */
145 #endif /* SYSCFG_CFGR3_DMA_RMP */
146
147 #if defined(SYSCFG_CFGR3_DMA_RMP)
148 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
149 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
150 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
151 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
152 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
153 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
154 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
155 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
156 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
157 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
158 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
159 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
160 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
161 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
162 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
163 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
164 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
165 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
166 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
167 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
168 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
169 #else
170 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
171 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
172 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
173 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
174 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
175 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
176 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
177 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
178 /**
179 * @}
180 */
181 #endif /* SYSCFG_CFGR1_DMA_RMP */
182
183 /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
184 * Elements values convention: 0xXXYYYYYY
185 * - YYYYYY : Position in the register
186 * - XX : Register index
187 * - 00: CFGR1 register in SYSCFG
188 * - 01: CFGR3 register in SYSCFG
189 * @{
190 */
191 #define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
192 0: No remap (DAC trigger is TIM8_TRGO)
193 1: Remap (DAC trigger is TIM3_TRGO) */
194 #define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
195 0: No remap
196 1: Remap (TIM1_TRG3 = TIM17_OC) */
197 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
198 #if !defined(HAL_REMAP_CFGR3_MASK)
199 #define HAL_REMAP_CFGR3_MASK (0x01000000U)
200 #endif
201 #define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
202 0: Remap (DAC trigger is TIM15_TRGO)
203 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
204 #define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
205 0: No remap
206 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
207 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
208 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
209 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
210 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
211 #else
212 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
213 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
214 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
215 /**
216 * @}
217 */
218
219 #if defined (STM32F302xE)
220 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
221 * @{
222 */
223 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
224 0: No remap (TIM1_CC3)
225 1: Remap (TIM20_TRGO) */
226 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
227 0: No remap (TIM2_CC2)
228 1: Remap (TIM20_TRGO2) */
229 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
230 0: No remap (TIM4_CC4)
231 1: Remap (TIM20_CC1) */
232 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
233 0: No remap (TIM6_TRGO)
234 1: Remap (TIM20_CC2) */
235 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
236 0: No remap (TIM3_CC4)
237 1: Remap (TIM20_CC3) */
238 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
239 0: No remap (TIM2_CC1)
240 1: Remap (TIM20_TRGO) */
241 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
242 0: No remap (EXTI line 15)
243 1: Remap (TIM20_TRGO2) */
244 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
245 0: No remap (TIM3_CC1)
246 1: Remap (TIM20_CC4) */
247
248 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
249 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
250 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
251 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
252 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
253 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
254 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
255 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
256 /**
257 * @}
258 */
259 #endif /* STM32F302xE */
260
261 #if defined (STM32F303xE) || defined (STM32F398xx)
262 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
263 * @{
264 */
265 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
266 0: No remap (TIM1_CC3)
267 1: Remap (TIM20_TRGO) */
268 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
269 0: No remap (TIM2_CC2)
270 1: Remap (TIM20_TRGO2) */
271 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
272 0: No remap (TIM4_CC4)
273 1: Remap (TIM20_CC1) */
274 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
275 0: No remap (TIM6_TRGO)
276 1: Remap (TIM20_CC2) */
277 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
278 0: No remap (TIM3_CC4)
279 1: Remap (TIM20_CC3) */
280 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
281 0: No remap (TIM2_CC1)
282 1: Remap (TIM20_TRGO) */
283 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
284 0: No remap (EXTI line 15)
285 1: Remap (TIM20_TRGO2) */
286 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
287 0: No remap (TIM3_CC1)
288 1: Remap (TIM20_CC4) */
289 #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
290 0: No remap (EXTI line 2)
291 1: Remap (TIM20_TRGO) */
292 #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
293 0: No remap (TIM4_CC1)
294 1: Remap (TIM20_TRGO2) */
295 #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
296 0: No remap (TIM2_CC1)
297 1: Remap (TIM20_CC1) */
298 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
299 0: No remap (TIM4_CC3)
300 1: Remap (TIM20_TRGO) */
301 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
302 0: No remap (TIM1_CC3)
303 1: Remap (TIM20_TRGO2) */
304 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
305 0: No remap (TIM7_TRGO)
306 1: Remap (TIM20_CC2) */
307
308 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
309 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
310 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
311 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
312 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
313 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
314 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
315 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
316 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
317 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
318 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
319 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
320 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
321 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
322 /**
323 * @}
324 */
325 #endif /* STM32F303xE || STM32F398xx */
326
327 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
328 * @{
329 */
330
331 /** @brief Fast-mode Plus driving capability on a specific GPIO
332 */
333 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
334 #define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
335 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
336
337 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
338 #define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
339 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
340
341 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
342 #define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
343 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
344
345 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
346 #define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
347 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
348 /**
349 * @}
350 */
351
352 #if defined(SYSCFG_RCR_PAGE0)
353 /* CCM-SRAM defined */
354 /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
355 * @{
356 */
357 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
358 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
359 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
360 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
361 #if defined(SYSCFG_RCR_PAGE4)
362 /* More than 4KB CCM-SRAM defined */
363 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
364 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
365 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
366 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
367 #endif /* SYSCFG_RCR_PAGE4 */
368 #if defined(SYSCFG_RCR_PAGE8)
369 #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
370 #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
371 #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
372 #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
373 #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
374 #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
375 #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
376 #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
377 #endif /* SYSCFG_RCR_PAGE8 */
378
379 #if defined(SYSCFG_RCR_PAGE8)
380 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
381 #elif defined(SYSCFG_RCR_PAGE4)
382 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
383 #else
384 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
385 #endif /* SYSCFG_RCR_PAGE8 */
386 /**
387 * @}
388 */
389 #endif /* SYSCFG_RCR_PAGE0 */
390
391 /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
392 * @{
393 */
394 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
395 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
396 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
397 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
398 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
399 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
400
401 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
402 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
403 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
404 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
405 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
406 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
407
408 /**
409 * @}
410 */
411
412 /**
413 * @}
414 */
415
416 /* Exported macros -----------------------------------------------------------*/
417 /** @defgroup HAL_Exported_Macros HAL Exported Macros
418 * @{
419 */
420
421 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
422 * @{
423 */
424 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
425 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
426 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
427 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
428
429 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
430 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
431 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
432 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
433
434 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
435 #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
436 #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
437 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
438
439 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
440 #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
441 #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
442 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
443
444 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
445 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
446 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
447 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
448
449 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
450 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
451 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
452 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
453
454 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
455 #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
456 #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
457 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
458
459 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
460 #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
461 #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
462 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
463
464 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
465 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
466 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
467 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
468
469 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
470 #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
471 #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
472 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
473
474 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
475 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
476 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
477 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
478
479 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
480 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
481 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
482 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
483
484 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
485 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
486 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
487 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
488
489 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
490 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
491 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
492 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
493
494 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
495 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
496 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
497 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
498
499 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
500 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
501 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
502 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
503
504 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
505 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
506 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
507 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
508 /**
509 * @}
510 */
511
512 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
513 * @{
514 */
515 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
516 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
517 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
518 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
519
520 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
521 #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
522 #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
523 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
524
525 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
526 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
527 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
528 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
529
530 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
531 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
532 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
533 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
534
535 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
536 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
537 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
538 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
539
540 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
541 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
542 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
543 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
544
545 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
546 #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
547 #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
548 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
549
550 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
551 #define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
552 #define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
553 #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
554 /**
555 * @}
556 */
557
558 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
559 * @{
560 */
561 #if defined(SYSCFG_CFGR1_MEM_MODE)
562 /** @brief Main Flash memory mapped at 0x00000000
563 */
564 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
565 #endif /* SYSCFG_CFGR1_MEM_MODE */
566
567 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
568 /** @brief System Flash memory mapped at 0x00000000
569 */
570 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
571 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
572 }while(0U)
573 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
574
575 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
576 /** @brief Embedded SRAM mapped at 0x00000000
577 */
578 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
579 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
580 }while(0U)
581 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
582
583 #if defined(SYSCFG_CFGR1_MEM_MODE_2)
584 #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
585 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
586 }while(0U)
587 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */
588 /**
589 * @}
590 */
591
592 /** @defgroup Encoder_Mode Encoder Mode
593 * @{
594 */
595 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
596 /** @brief No Encoder mode
597 */
598 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
599 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
600
601 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
602 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
603 */
604 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
605 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
606 }while(0U)
607 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
608
609 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
610 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
611 */
612 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
613 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
614 }while(0U)
615 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
616
617 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
618 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
619 */
620 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
621 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
622 }while(0U)
623 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
624 /**
625 * @}
626 */
627
628 /** @defgroup DMA_Remap_Enable DMA Remap Enable
629 * @{
630 */
631 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
632 /** @brief DMA remapping enable/disable macros
633 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
634 */
635 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
636 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
637 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
638 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
639 }while(0U)
640 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
641 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
642 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
643 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
644 }while(0U)
645 #elif defined(SYSCFG_CFGR1_DMA_RMP)
646 /** @brief DMA remapping enable/disable macros
647 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
648 */
649 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
650 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
651 }while(0U)
652 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
653 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
654 }while(0U)
655 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
656 /**
657 * @}
658 */
659
660 /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
661 * @{
662 */
663 /** @brief Fast-mode Plus driving capability enable/disable macros
664 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
665 * That you can find above these macros.
666 */
667 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
668 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
669 }while(0U)
670
671 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
672 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
673 }while(0U)
674 /**
675 * @}
676 */
677
678 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
679 * @{
680 */
681 /** @brief SYSCFG interrupt enable/disable macros
682 * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
683 */
684 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
685 SYSCFG->CFGR1 |= (__INTERRUPT__); \
686 }while(0U)
687
688 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
689 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
690 }while(0U)
691 /**
692 * @}
693 */
694
695 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
696 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
697 * @{
698 */
699 /** @brief USB interrupt remapping enable/disable macros
700 */
701 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
702 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
703 /**
704 * @}
705 */
706 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
707
708 #if defined(SYSCFG_CFGR1_VBAT)
709 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
710 * @{
711 */
712 /** @brief SYSCFG interrupt enable/disable macros
713 */
714 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
715 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
716 /**
717 * @}
718 */
719 #endif /* SYSCFG_CFGR1_VBAT */
720
721 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
722 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
723 * @{
724 */
725 /** @brief SYSCFG Break Lockup lock
726 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
727 * @note The selected configuration is locked and can be unlocked by system reset
728 */
729 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
730 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
731 }while(0U)
732 /**
733 * @}
734 */
735 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
736
737 #if defined(SYSCFG_CFGR2_PVD_LOCK)
738 /** @defgroup PVD_Lock_Enable PVD Lock
739 * @{
740 */
741 /** @brief SYSCFG Break PVD lock
742 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
743 * @note The selected configuration is locked and can be unlocked by system reset
744 */
745 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
746 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
747 }while(0U)
748 /**
749 * @}
750 */
751 #endif /* SYSCFG_CFGR2_PVD_LOCK */
752
753 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
754 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
755 * @{
756 */
757 /** @brief SYSCFG Break SRAM PARITY lock
758 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
759 * @note The selected configuration is locked and can be unlocked by system reset
760 */
761 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
762 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
763 }while(0U)
764 /**
765 * @}
766 */
767 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
768
769 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
770 * @{
771 */
772 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
773 /** @brief Trigger remapping enable/disable macros
774 * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
775 */
776 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
777 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
778 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
779 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
780 }while(0U)
781 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
782 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
783 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
784 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
785 }while(0U)
786 #else
787 /** @brief Trigger remapping enable/disable macros
788 * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
789 */
790 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
791 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
792 }while(0U)
793 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
794 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
795 }while(0U)
796 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
797 /**
798 * @}
799 */
800
801 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
802 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
803 * @{
804 */
805 /** @brief ADC trigger remapping enable/disable macros
806 * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
807 */
808 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
809 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
810 }while(0U)
811 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
812 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
813 }while(0U)
814 /**
815 * @}
816 */
817 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
818
819 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
820 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
821 * @{
822 */
823 /**
824 * @brief Parity check on RAM disable macro
825 * @note Disabling the parity check on RAM locks the configuration bit.
826 * To re-enable the parity check on RAM perform a system reset.
827 */
828 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
829 /**
830 * @}
831 */
832 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
833
834 #if defined(SYSCFG_RCR_PAGE0)
835 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
836 * @{
837 */
838 /** @brief CCM RAM page write protection enable macro
839 * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
840 * @note write protection can only be disabled by a system reset
841 */
842 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
843 SYSCFG->RCR |= (__PAGE_WP__); \
844 }while(0U)
845 /**
846 * @}
847 */
848 #endif /* SYSCFG_RCR_PAGE0 */
849
850 /**
851 * @}
852 */
853 /* Exported functions --------------------------------------------------------*/
854 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
855 * @{
856 */
857
858 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
859 * @brief Initialization and de-initialization functions
860 * @{
861 */
862 /* Initialization and de-initialization functions ******************************/
863 HAL_StatusTypeDef HAL_Init(void);
864 HAL_StatusTypeDef HAL_DeInit(void);
865 void HAL_MspInit(void);
866 void HAL_MspDeInit(void);
867 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
868 /**
869 * @}
870 */
871
872 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
873 * @brief HAL Control functions
874 * @{
875 */
876 /* Peripheral Control functions ************************************************/
877 void HAL_IncTick(void);
878 void HAL_Delay(__IO uint32_t Delay);
879 void HAL_SuspendTick(void);
880 void HAL_ResumeTick(void);
881 uint32_t HAL_GetTick(void);
882 uint32_t HAL_GetHalVersion(void);
883 uint32_t HAL_GetREVID(void);
884 uint32_t HAL_GetDEVID(void);
885 uint32_t HAL_GetUIDw0(void);
886 uint32_t HAL_GetUIDw1(void);
887 uint32_t HAL_GetUIDw2(void);
888 void HAL_DBGMCU_EnableDBGSleepMode(void);
889 void HAL_DBGMCU_DisableDBGSleepMode(void);
890 void HAL_DBGMCU_EnableDBGStopMode(void);
891 void HAL_DBGMCU_DisableDBGStopMode(void);
892 void HAL_DBGMCU_EnableDBGStandbyMode(void);
893 void HAL_DBGMCU_DisableDBGStandbyMode(void);
894 /**
895 * @}
896 */
897
898 /**
899 * @}
900 */
901
902 /**
903 * @}
904 */
905
906 /**
907 * @}
908 */
909
910 #ifdef __cplusplus
911 }
912 #endif
913
914 #endif /* __STM32F3xx_HAL_H */
915
916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/