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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal_can.h
blobbcc92b9d7d55c4d53b5feb541fc8ff2985a76536
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_can.h
4 * @author MCD Application Team
5 * @brief Header file of CAN HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_CAN_H
38 #define __STM32F3xx_CAN_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
45 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
46 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
47 defined(STM32F302x8) || \
48 defined(STM32F373xC) || defined(STM32F378xx)
49
50 /* Includes ------------------------------------------------------------------*/
51 #include "stm32f3xx_hal_def.h"
52
53 /** @addtogroup STM32F3xx_HAL_Driver
54 * @{
55 */
56
57 /** @addtogroup CAN
58 * @{
59 */
60
61 /* Exported types ------------------------------------------------------------*/
62 /** @defgroup CAN_Exported_Types CAN Exported Types
63 * @{
64 */
65 /**
66 * @brief HAL State structures definition
67 */
68 typedef enum
69 {
70 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
71 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
72 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
73 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
74 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
75 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
76 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
77 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
78 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
79 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
80 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
81 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
82
83 }HAL_CAN_StateTypeDef;
84
85 /**
86 * @brief CAN init structure definition
87 */
88 typedef struct
89 {
90 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
91 This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
92
93 uint32_t Mode; /*!< Specifies the CAN operating mode.
94 This parameter can be a value of @ref CAN_operating_mode */
95
96 uint32_t SJW; /*!< Specifies the maximum number of time quanta
97 the CAN hardware is allowed to lengthen or
98 shorten a bit to perform resynchronization.
99 This parameter can be a value of @ref CAN_synchronisation_jump_width */
100
101 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
102 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
103
104 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
105 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
106
107 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
108 This parameter can be set to ENABLE or DISABLE. */
109
110 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
111 This parameter can be set to ENABLE or DISABLE. */
112
113 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
114 This parameter can be set to ENABLE or DISABLE. */
115
116 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
117 This parameter can be set to ENABLE or DISABLE. */
118
119 uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
120 This parameter can be set to ENABLE or DISABLE. */
121
122 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
123 This parameter can be set to ENABLE or DISABLE. */
124 }CAN_InitTypeDef;
125
126 /**
127 * @brief CAN filter configuration structure definition
128 */
129 typedef struct
130 {
131 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
132 configuration, first one for a 16-bit configuration).
133 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
134
135 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
136 configuration, second one for a 16-bit configuration).
137 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
138
139 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
140 according to the mode (MSBs for a 32-bit configuration,
141 first one for a 16-bit configuration).
142 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
143
144 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
145 according to the mode (LSBs for a 32-bit configuration,
146 second one for a 16-bit configuration).
147 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
148
149 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
150 This parameter can be a value of @ref CAN_filter_FIFO */
151
152 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
153 This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
154
155 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
156 This parameter can be a value of @ref CAN_filter_mode */
157
158 uint32_t FilterScale; /*!< Specifies the filter scale.
159 This parameter can be a value of @ref CAN_filter_scale */
160
161 uint32_t FilterActivation; /*!< Enable or disable the filter.
162 This parameter can be set to ENABLE or DISABLE. */
163
164 uint32_t BankNumber; /*!< Select the start slave bank filter
165 F3 devices don't support CAN2 interface (Slave). Therefore this parameter
166 is meaningless but it has been kept for compatibility accross STM32 families */
167
168 }CAN_FilterConfTypeDef;
169
170 /**
171 * @brief CAN Tx message structure definition
172 */
173 typedef struct
174 {
175 uint32_t StdId; /*!< Specifies the standard identifier.
176 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
177
178 uint32_t ExtId; /*!< Specifies the extended identifier.
179 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
180
181 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
182 This parameter can be a value of @ref CAN_identifier_type */
183
184 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
185 This parameter can be a value of @ref CAN_remote_transmission_request */
186
187 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
188 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
189
190 uint8_t Data[8]; /*!< Contains the data to be transmitted.
191 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
192
193 }CanTxMsgTypeDef;
194
195 /**
196 * @brief CAN Rx message structure definition
197 */
198 typedef struct
199 {
200 uint32_t StdId; /*!< Specifies the standard identifier.
201 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
202
203 uint32_t ExtId; /*!< Specifies the extended identifier.
204 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
205
206 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
207 This parameter can be a value of @ref CAN_identifier_type */
208
209 uint32_t RTR; /*!< Specifies the type of frame for the received message.
210 This parameter can be a value of @ref CAN_remote_transmission_request */
211
212 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
213 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
214
215 uint8_t Data[8]; /*!< Contains the data to be received.
216 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
217
218 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
219 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
220
221 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
222 This parameter can be CAN_FIFO0 or CAN_FIFO1 */
223
224 }CanRxMsgTypeDef;
225
226 /**
227 * @brief CAN handle Structure definition
228 */
229 typedef struct
230 {
231 CAN_TypeDef *Instance; /*!< Register base address */
232
233 CAN_InitTypeDef Init; /*!< CAN required parameters */
234
235 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
236
237 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
238
239 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
240
241 HAL_LockTypeDef Lock; /*!< CAN locking object */
242
243 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
244
245 __IO uint32_t ErrorCode; /*!< CAN Error code
246 This parameter can be a value of @ref CAN_Error_Code */
247
248 }CAN_HandleTypeDef;
249 /**
250 * @}
251 */
252
253 /* Exported constants --------------------------------------------------------*/
254
255 /** @defgroup CAN_Exported_Constants CAN Exported Constants
256 * @{
257 */
258
259 /** @defgroup CAN_Error_Code CAN Error Code
260 * @{
261 */
262 #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
263 #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
264 #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
265 #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
266 #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
267 #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
268 #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
269 #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
270 #define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
271 #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
272 #define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
273 #define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
274 #define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
275 /**
276 * @}
277 */
278
279 /** @defgroup CAN_InitStatus CAN InitStatus
280 * @{
281 */
282 #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
283 #define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
284 /**
285 * @}
286 */
287
288 /** @defgroup CAN_operating_mode CAN Operating Mode
289 * @{
290 */
291 #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
292 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
293 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
294 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
295 /**
296 * @}
297 */
298
299
300 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
301 * @{
302 */
303 #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
304 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
305 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
306 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
307 /**
308 * @}
309 */
310
311 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
312 * @{
313 */
314 #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
315 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
316 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
317 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
318 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
319 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
320 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
321 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
322 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
323 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
324 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
325 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
326 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
327 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
328 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
329 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
330 /**
331 * @}
332 */
333
334 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
335 * @{
336 */
337 #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
338 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
339 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
340 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
341 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
342 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
343 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
344 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
345 /**
346 * @}
347 */
348
349 /** @defgroup CAN_filter_mode CAN Filter Mode
350 * @{
351 */
352 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
353 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
354 /**
355 * @}
356 */
357
358 /** @defgroup CAN_filter_scale CAN Filter Scale
359 * @{
360 */
361 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
362 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
363 /**
364 * @}
365 */
366
367 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
368 * @{
369 */
370 #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
371 #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
372 /**
373 * @}
374 */
375
376 /** @defgroup CAN_identifier_type CAN Identifier Type
377 * @{
378 */
379 #define CAN_ID_STD (0x00000000U) /*!< Standard Id */
380 #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
381 /**
382 * @}
383 */
384
385 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
386 * @{
387 */
388 #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
389 #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
390 /**
391 * @}
392 */
393
394 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
395 * @{
396 */
397 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
398 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
399 /**
400 * @}
401 */
402
403 /** @defgroup CAN_flags CAN Flags
404 * @{
405 */
406 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
407 and CAN_ClearFlag() functions. */
408 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
409 CAN_GetFlagStatus() function. */
410
411 /* Transmit Flags */
412 #define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
413 #define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
414 #define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
415 #define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
416 #define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
417 #define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
418 #define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
419 #define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
420 #define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
421
422 /* Receive Flags */
423 #define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
424 #define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
425
426 #define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
427 #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
428
429 /* Operating Mode Flags */
430 #define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
431 #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
432 #define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
433 #define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
434 #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
435 /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
436 In this case the SLAK bit can be polled.*/
437
438 /* Error Flags */
439 #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
440 #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
441 #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
442
443 /**
444 * @}
445 */
446
447
448 /** @defgroup CAN_interrupts CAN Interrupts
449 * @{
450 */
451 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
452
453 /* Receive Interrupts */
454 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
455 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
456 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
457 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
458 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
459 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
460
461 /* Operating Mode Interrupts */
462 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
463 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
464
465 /* Error Interrupts */
466 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
467 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
468 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
469 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
470 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
471
472 /**
473 * @}
474 */
475
476 /** @defgroup CAN_Mailboxes CAN Mailboxes
477 * @{
478 */
479 /* Mailboxes definition */
480 #define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
481 #define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
482 #define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
483 /**
484 * @}
485 */
486
487 /**
488 * @}
489 */
490
491 /* Exported macros -----------------------------------------------------------*/
492 /** @defgroup CAN_Exported_Macros CAN Exported Macros
493 * @{
494 */
495
496 /** @brief Reset CAN handle state
497 * @param __HANDLE__ CAN handle.
498 * @retval None
499 */
500 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
501
502 /**
503 * @brief Enable the specified CAN interrupts.
504 * @param __HANDLE__ CAN handle.
505 * @param __INTERRUPT__ CAN Interrupt
506 * @retval None
507 */
508 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
509
510 /**
511 * @brief Disable the specified CAN interrupts.
512 * @param __HANDLE__ CAN handle.
513 * @param __INTERRUPT__ CAN Interrupt
514 * @retval None
515 */
516 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
517
518 /**
519 * @brief Return the number of pending received messages.
520 * @param __HANDLE__ CAN handle.
521 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
522 * @retval The number of pending message.
523 */
524 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
525 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
526
527 /** @brief Check whether the specified CAN flag is set or not.
528 * @param __HANDLE__ specifies the CAN Handle.
529 * @param __FLAG__ specifies the flag to check.
530 * This parameter can be one of the following values:
531 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
532 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
533 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
534 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
535 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
536 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
537 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
538 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
539 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
540 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
541 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
542 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
543 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
544 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
545 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
546 * @arg CAN_FLAG_WKU: Wake up Flag
547 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
548 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
549 * @arg CAN_FLAG_EWG: Error Warning Flag
550 * @arg CAN_FLAG_EPV: Error Passive Flag
551 * @arg CAN_FLAG_BOF: Bus-Off Flag
552 * @retval The new state of __FLAG__ (TRUE or FALSE).
553 */
554 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
555 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
556 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
557 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
558 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
559 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
560
561 /** @brief Clear the specified CAN pending flag.
562 * @param __HANDLE__ specifies the CAN Handle.
563 * @param __FLAG__ specifies the flag to check.
564 * This parameter can be one of the following values:
565 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
566 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
567 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
568 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
569 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
570 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
571 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
572 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
573 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
574 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
575 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
576 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
577 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
578 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
579 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
580 * @arg CAN_FLAG_WKU: Wake up Flag
581 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
582 * @arg CAN_FLAG_EWG: Error Warning Flag
583 * @arg CAN_FLAG_EPV: Error Passive Flag
584 * @arg CAN_FLAG_BOF: Bus-Off Flag
585 * @retval The new state of __FLAG__ (TRUE or FALSE).
586 */
587 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
588 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
589 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
590 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
591 (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
592
593
594 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
595 * @param __HANDLE__ specifies the CAN Handle.
596 * @param __INTERRUPT__ specifies the CAN interrupt source to check.
597 * This parameter can be one of the following values:
598 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
599 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
600 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
601 * @retval The new state of __IT__ (TRUE or FALSE).
602 */
603 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
604
605 /**
606 * @brief Check the transmission status of a CAN Frame.
607 * @param __HANDLE__ CAN handle.
608 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
609 * @retval The new status of transmission (TRUE or FALSE).
610 */
611 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
612 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
613 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
614 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
615
616 /**
617 * @brief Release the specified receive FIFO.
618 * @param __HANDLE__ CAN handle.
619 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
620 * @retval None
621 */
622 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
623 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
624
625 /**
626 * @brief Cancel a transmit request.
627 * @param __HANDLE__ specifies the CAN Handle.
628 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
629 * @retval None
630 */
631 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
632 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
633 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
634 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
635
636 /**
637 * @brief Enable or disables the DBG Freeze for CAN.
638 * @param __HANDLE__ specifies the CAN Handle.
639 * @param __NEWSTATE__ new state of the CAN peripheral.
640 * This parameter can be: ENABLE (CAN reception/transmission is frozen
641 * during debug. Reception FIFOs can still be accessed/controlled normally)
642 * or DISABLE (CAN is working during debug).
643 * @retval None
644 */
645 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
646 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
647
648 /**
649 * @}
650 */
651
652 /* Exported functions --------------------------------------------------------*/
653 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
654 * @{
655 */
656
657 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
658 * @brief Initialization and Configuration functions
659 * @{
660 */
661
662 /* Initialization and de-initialization functions *****************************/
663 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
664 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
665 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
666 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
667 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
668 /**
669 * @}
670 */
671
672 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
673 * @brief I/O operation functions
674 * @{
675 */
676 /* IO operation functions *****************************************************/
677 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
678 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
679 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
680 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
681 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
682 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
683 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
684 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
685 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
686 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
687 /**
688 * @}
689 */
690
691 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
692 * @brief CAN Peripheral State functions
693 * @{
694 */
695 /* Peripheral State and Error functions ***************************************/
696 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
697 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
698 /**
699 * @}
700 */
701
702 /**
703 * @}
704 */
705
706 /* Private types -------------------------------------------------------------*/
707 /** @defgroup CAN_Private_Types CAN Private Types
708 * @{
709 */
710
711 /**
712 * @}
713 */
714
715 /* Private variables ---------------------------------------------------------*/
716 /** @defgroup CAN_Private_Variables CAN Private Variables
717 * @{
718 */
719
720 /**
721 * @}
722 */
723
724 /* Private constants ---------------------------------------------------------*/
725 /** @defgroup CAN_Private_Constants CAN Private Constants
726 * @{
727 */
728 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
729 #define CAN_FLAG_MASK (0x000000FFU)
730 /**
731 * @}
732 */
733
734 /* Private Macros -----------------------------------------------------------*/
735 /** @defgroup CAN_Private_Macros CAN Private Macros
736 * @{
737 */
738
739 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
740 ((MODE) == CAN_MODE_LOOPBACK)|| \
741 ((MODE) == CAN_MODE_SILENT) || \
742 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
743
744 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
745 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
746
747 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
748
749 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
750
751 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
752
753 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
754
755 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
756 ((MODE) == CAN_FILTERMODE_IDLIST))
757
758 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
759 ((SCALE) == CAN_FILTERSCALE_32BIT))
760
761 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
762 ((FIFO) == CAN_FILTER_FIFO1))
763
764 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
765
766 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
767 #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
768 #define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
769 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
770
771 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
772 ((IDTYPE) == CAN_ID_EXT))
773
774 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
775
776 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
777
778 #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
779 ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
780 ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
781 ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
782 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
783 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
784 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
785
786 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
787 ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
788 ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
789 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
790 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
791 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
792
793 /**
794 * @}
795 */
796 /* End of private macros -----------------------------------------------------*/
797
798 /**
799 * @}
800 */
801
802 /**
803 * @}
804 */
805
806 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
807 /* STM32F302xC || STM32F303xC || STM32F358xx || */
808 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
809 /* STM32F302x8 || */
810 /* STM32F373xC || STM32F378xx */
811
812 #ifdef __cplusplus
813 }
814 #endif
815
816 #endif /* __STM32F3xx_CAN_H */
817
818
819 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/