lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of DMA HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_HAL_DMA_H
  38 #define __STM32F3xx_HAL_DMA_H
  39
  40 #ifdef __cplusplus
  41  extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f3xx_hal_def.h"
  46
  47 /** @addtogroup STM32F3xx_HAL_Driver
  48   * @{
  49   */
  50
  51 /** @addtogroup DMA
  52   * @{
  53   */
  54
  55 /* Exported types ------------------------------------------------------------*/
  56
  57 /** @defgroup DMA_Exported_Types DMA Exported Types
  58   * @{
  59   */
  60
  61 /**
  62   * @brief  DMA Configuration Structure definition
  63   */
  64 typedef struct
  65 {
  66   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  67                                            from memory to memory or from peripheral to memory.
  68                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  69
  70   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  71                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  72
  73   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  74                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  75
  76   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  77                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  78
  79   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  80                                            This parameter can be a value of @ref DMA_Memory_data_size */
  81
  82   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  83                                            This parameter can be a value of @ref DMA_mode
  84                                            @note The circular buffer mode cannot be used if the memory-to-memory
  85                                            data transfer is configured on the selected Channel */
  86
  87   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  88                                             This parameter can be a value of @ref DMA_Priority_level */
  89 } DMA_InitTypeDef;
  90
  91 /**
  92   * @brief  HAL DMA State structures definition
  93   */
  94 typedef enum
  95 {
  96   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
  97   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
  98   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
  99   HAL_DMA_STATE_TIMEOUT           = 0x03   /*!< DMA timeout state                   */
 100 }HAL_DMA_StateTypeDef;
 101
 102 /**
 103   * @brief  HAL DMA Error Code structure definition
 104   */
 105 typedef enum
 106 {
 107   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
 108   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
 109 }HAL_DMA_LevelCompleteTypeDef;
 110
 111 /**
 112   * @brief  HAL DMA Callback ID structure definition
 113   */
 114 typedef enum
 115 {
 116   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 117   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
 118   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
 119   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
 120   HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
 121 }HAL_DMA_CallbackIDTypeDef;
 122
 123 /**
 124   * @brief  DMA handle Structure definition
 125   */
 126 typedef struct __DMA_HandleTypeDef
 127 {
 128   DMA_Channel_TypeDef   *Instance;                                                    /*!< Register base address                  */
 129
 130   DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
 131
 132   HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
 133
 134   HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 135
 136   void                  *Parent;                                                      /*!< Parent object state                    */
 137
 138   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 139
 140   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 141
 142   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 143
 144   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */
 145
 146   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
 147
 148   DMA_TypeDef          *DmaBaseAddress;                                               /*!< DMA Channel Base Address               */
 149
 150   uint32_t              ChannelIndex;                                                 /*!< DMA Channel Index                      */
 151 } DMA_HandleTypeDef;
 152 /**
 153   * @}
 154   */
 155
 156 /* Exported constants --------------------------------------------------------*/
 157
 158 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 159   * @{
 160   */
 161
 162 /** @defgroup DMA_Error_Code DMA Error Code
 163   * @{
 164   */
 165 #define HAL_DMA_ERROR_NONE          (0x00000000U)    /*!< No error             */
 166 #define HAL_DMA_ERROR_TE            (0x00000001U)    /*!< Transfer error       */
 167 #define HAL_DMA_ERROR_NO_XFER       (0x00000004U)    /*!< no ongoin transfer   */
 168 #define HAL_DMA_ERROR_TIMEOUT       (0x00000020U)    /*!< Timeout error        */
 169 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)    /*!< Not supported mode */
 170 /**
 171   * @}
 172   */
 173
 174 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 175   * @{
 176   */
 177 #define DMA_PERIPH_TO_MEMORY         (0x00000000U)        /*!< Peripheral to memory direction */
 178 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 179 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
 180
 181 /**
 182   * @}
 183   */
 184
 185 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 186   * @{
 187   */
 188 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 189 #define DMA_PINC_DISABLE       (0x00000000U)    /*!< Peripheral increment mode Disable */
 190 /**
 191   * @}
 192   */
 193
 194 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 195   * @{
 196   */
 197 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 198 #define DMA_MINC_DISABLE        (0x00000000U)    /*!< Memory increment mode Disable */
 199 /**
 200   * @}
 201   */
 202
 203 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 204   * @{
 205   */
 206 #define DMA_PDATAALIGN_BYTE          (0x00000000U)       /*!< Peripheral data alignment : Byte     */
 207 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 208 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 209 /**
 210   * @}
 211   */
 212
 213 /** @defgroup DMA_Memory_data_size DMA Memory data size
 214   * @{
 215   */
 216 #define DMA_MDATAALIGN_BYTE          (0x00000000U)       /*!< Memory data alignment : Byte     */
 217 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
 218 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
 219 /**
 220   * @}
 221   */
 222
 223 /** @defgroup DMA_mode DMA mode
 224   * @{
 225   */
 226 #define DMA_NORMAL         (0x00000000U)      /*!< Normal Mode                  */
 227 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup DMA_Priority_level DMA Priority level
 233   * @{
 234   */
 235 #define DMA_PRIORITY_LOW             (0x00000000U)    /*!< Priority level : Low       */
 236 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 237 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 238 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 239 /**
 240   * @}
 241   */
 242
 243
 244 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 245   * @{
 246   */
 247 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 248 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 249 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 250 /**
 251   * @}
 252   */
 253
 254 /** @defgroup DMA_flag_definitions DMA flag definitions
 255   * @{
 256   */
 257 #define DMA_FLAG_GL1                      (0x00000001U)
 258 #define DMA_FLAG_TC1                      (0x00000002U)
 259 #define DMA_FLAG_HT1                      (0x00000004U)
 260 #define DMA_FLAG_TE1                      (0x00000008U)
 261 #define DMA_FLAG_GL2                      (0x00000010U)
 262 #define DMA_FLAG_TC2                      (0x00000020U)
 263 #define DMA_FLAG_HT2                      (0x00000040U)
 264 #define DMA_FLAG_TE2                      (0x00000080U)
 265 #define DMA_FLAG_GL3                      (0x00000100U)
 266 #define DMA_FLAG_TC3                      (0x00000200U)
 267 #define DMA_FLAG_HT3                      (0x00000400U)
 268 #define DMA_FLAG_TE3                      (0x00000800U)
 269 #define DMA_FLAG_GL4                      (0x00001000U)
 270 #define DMA_FLAG_TC4                      (0x00002000U)
 271 #define DMA_FLAG_HT4                      (0x00004000U)
 272 #define DMA_FLAG_TE4                      (0x00008000U)
 273 #define DMA_FLAG_GL5                      (0x00010000U)
 274 #define DMA_FLAG_TC5                      (0x00020000U)
 275 #define DMA_FLAG_HT5                      (0x00040000U)
 276 #define DMA_FLAG_TE5                      (0x00080000U)
 277 #define DMA_FLAG_GL6                      (0x00100000U)
 278 #define DMA_FLAG_TC6                      (0x00200000U)
 279 #define DMA_FLAG_HT6                      (0x00400000U)
 280 #define DMA_FLAG_TE6                      (0x00800000U)
 281 #define DMA_FLAG_GL7                      (0x01000000U)
 282 #define DMA_FLAG_TC7                      (0x02000000U)
 283 #define DMA_FLAG_HT7                      (0x04000000U)
 284 #define DMA_FLAG_TE7                      (0x08000000U)
 285 /**
 286   * @}
 287   */
 288
 289 /**
 290   * @}
 291   */
 292
 293
 294 /* Exported macro ------------------------------------------------------------*/
 295 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 296   * @{
 297   */
 298
 299 /** @brief  Reset DMA handle state
 300   * @param  __HANDLE__ DMA handle.
 301   * @retval None
 302   */
 303 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 304
 305 /**
 306   * @brief  Enable the specified DMA Channel.
 307   * @param  __HANDLE__ DMA handle
 308   * @retval None
 309   */
 310 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
 311
 312 /**
 313   * @brief  Disable the specified DMA Channel.
 314   * @param  __HANDLE__ DMA handle
 315   * @retval None
 316   */
 317 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
 318
 319
 320 /* Interrupt & Flag management */
 321
 322 /**
 323   * @brief  Enables the specified DMA Channel interrupts.
 324   * @param  __HANDLE__ DMA handle
 325   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 326   *          This parameter can be any combination of the following values:
 327   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 328   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 329   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 330   * @retval None
 331   */
 332 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
 333
 334 /**
 335   * @brief  Disables the specified DMA Channel interrupts.
 336   * @param  __HANDLE__ DMA handle
 337   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 338   *          This parameter can be any combination of the following values:
 339   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 340   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 341   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 342   * @retval None
 343   */
 344 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
 345
 346 /**
 347   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
 348   * @param  __HANDLE__ DMA handle
 349   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
 350   *          This parameter can be one of the following values:
 351   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 352   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 353   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 354   * @retval The state of DMA_IT (SET or RESET).
 355   */
 356 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
 357
 358 /**
 359   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
 360   * @param  __HANDLE__ DMA handle
 361   *
 362   * @retval The number of remaining data units in the current DMA Channel transfer.
 363   */
 364 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
 365
 366 /**
 367   * @}
 368   */
 369
 370 /* Include DMA HAL Extended module */
 371 #include "stm32f3xx_hal_dma_ex.h"
 372
 373 /* Exported functions --------------------------------------------------------*/
 374 /** @addtogroup DMA_Exported_Functions
 375   * @{
 376   */
 377
 378 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 379   * @{
 380   */
 381 /* Initialization and de-initialization functions *****************************/
 382 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 383 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 384 /**
 385   * @}
 386   */
 387
 388 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
 389   * @{
 390   */
 391 /* Input and Output operation functions *****************************************************/
 392 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 393 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 394 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 395 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 396 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 397 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 398 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
 399 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 400 /**
 401   * @}
 402   */
 403
 404 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
 405   * @{
 406   */
 407 /* Peripheral State and Error functions ***************************************/
 408 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 409 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 410 /**
 411   * @}
 412   */
 413
 414 /**
 415   * @}
 416   */
 417 /* Private macros ------------------------------------------------------------*/
 418 /** @defgroup DMA_Private_Macros DMA Private Macros
 419   * @brief    DMA private macros
 420   * @{
 421   */
 422
 423 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
 424
 425 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 426                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 427                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 428
 429 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 430                                             ((STATE) == DMA_PINC_DISABLE))
 431
 432 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 433                                         ((STATE) == DMA_MINC_DISABLE))
 434
 435 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 436                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 437                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 438
 439 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 440                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 441                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 442
 443 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 444                            ((MODE) == DMA_CIRCULAR))
 445
 446 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 447                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 448                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 449                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 450
 451 /**
 452   * @}
 453   */
 454
 455
 456 /**
 457   * @}
 458   */
 459
 460 /**
 461   * @}
 462   */
 463
 464 #ifdef __cplusplus
 465 }
 466 #endif
 467
 468 #endif /* __STM32F3xx_HAL_DMA_H */
 469
 470 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/