lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_spi.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of SPI HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_HAL_SPI_H
  38 #define __STM32F3xx_HAL_SPI_H
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f3xx_hal_def.h"
  46
  47 /** @addtogroup STM32F3xx_HAL_Driver
  48   * @{
  49   */
  50
  51 /** @addtogroup SPI
  52   * @{
  53   */
  54
  55 /* Exported types ------------------------------------------------------------*/
  56 /** @defgroup SPI_Exported_Types SPI Exported Types
  57   * @{
  58   */
  59
  60 /**
  61   * @brief  SPI Configuration Structure definition
  62   */
  63 typedef struct
  64 {
  65   uint32_t Mode;                /*!< Specifies the SPI operating mode.
  66                                      This parameter can be a value of @ref SPI_Mode */
  67
  68   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
  69                                      This parameter can be a value of @ref SPI_Direction */
  70
  71   uint32_t DataSize;            /*!< Specifies the SPI data size.
  72                                      This parameter can be a value of @ref SPI_Data_Size */
  73
  74   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
  75                                      This parameter can be a value of @ref SPI_Clock_Polarity */
  76
  77   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
  78                                      This parameter can be a value of @ref SPI_Clock_Phase */
  79
  80   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
  81                                      hardware (NSS pin) or by software using the SSI bit.
  82                                      This parameter can be a value of @ref SPI_Slave_Select_management */
  83
  84   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
  85                                      used to configure the transmit and receive SCK clock.
  86                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
  87                                      @note The communication clock is derived from the master
  88                                      clock. The slave clock does not need to be set. */
  89
  90   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
  91                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
  92
  93   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
  94                                      This parameter can be a value of @ref SPI_TI_mode */
  95
  96   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
  97                                      This parameter can be a value of @ref SPI_CRC_Calculation */
  98
  99   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
 100                                      This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
 101
 102   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
 103                                      CRC Length is only used with Data8 and Data16, not other data size
 104                                      This parameter can be a value of @ref SPI_CRC_length */
 105
 106   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
 107                                      This parameter can be a value of @ref SPI_NSSP_Mode
 108                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
 109                                      it takes effect only if the SPI interface is configured as Motorola SPI
 110                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
 111                                      CPOL setting is ignored).. */
 112 } SPI_InitTypeDef;
 113
 114 /**
 115   * @brief  HAL SPI State structure definition
 116   */
 117 typedef enum
 118 {
 119   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
 120   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
 121   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
 122   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
 123   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
 124   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
 125   HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
 126   HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
 127 } HAL_SPI_StateTypeDef;
 128
 129 /**
 130   * @brief  SPI handle Structure definition
 131   */
 132 typedef struct __SPI_HandleTypeDef
 133 {
 134   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
 135
 136   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
 137
 138   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
 139
 140   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
 141
 142   __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
 143
 144   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
 145
 146   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
 147
 148   __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
 149
 150   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
 151
 152   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
 153
 154   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
 155
 156   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
 157
 158   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
 159
 160   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
 161
 162   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
 163
 164   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
 165
 166 } SPI_HandleTypeDef;
 167
 168 /**
 169   * @}
 170   */
 171
 172 /* Exported constants --------------------------------------------------------*/
 173 /** @defgroup SPI_Exported_Constants SPI Exported Constants
 174   * @{
 175   */
 176
 177 /** @defgroup SPI_Error_Code SPI Error Code
 178   * @{
 179   */
 180 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
 181 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
 182 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
 183 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
 184 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
 185 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
 186 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
 187 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
 188 /**
 189   * @}
 190   */
 191
 192 /** @defgroup SPI_Mode SPI Mode
 193   * @{
 194   */
 195 #define SPI_MODE_SLAVE                  (0x00000000U)
 196 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup SPI_Direction SPI Direction Mode
 202   * @{
 203   */
 204 #define SPI_DIRECTION_2LINES            (0x00000000U)
 205 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
 206 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
 207 /**
 208   * @}
 209   */
 210
 211 /** @defgroup SPI_Data_Size SPI Data Size
 212   * @{
 213   */
 214 #define SPI_DATASIZE_4BIT               (0x00000300U)
 215 #define SPI_DATASIZE_5BIT               (0x00000400U)
 216 #define SPI_DATASIZE_6BIT               (0x00000500U)
 217 #define SPI_DATASIZE_7BIT               (0x00000600U)
 218 #define SPI_DATASIZE_8BIT               (0x00000700U)
 219 #define SPI_DATASIZE_9BIT               (0x00000800U)
 220 #define SPI_DATASIZE_10BIT              (0x00000900U)
 221 #define SPI_DATASIZE_11BIT              (0x00000A00U)
 222 #define SPI_DATASIZE_12BIT              (0x00000B00U)
 223 #define SPI_DATASIZE_13BIT              (0x00000C00U)
 224 #define SPI_DATASIZE_14BIT              (0x00000D00U)
 225 #define SPI_DATASIZE_15BIT              (0x00000E00U)
 226 #define SPI_DATASIZE_16BIT              (0x00000F00U)
 227 /**
 228   * @}
 229   */
 230
 231 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
 232   * @{
 233   */
 234 #define SPI_POLARITY_LOW                (0x00000000U)
 235 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 236 /**
 237   * @}
 238   */
 239
 240 /** @defgroup SPI_Clock_Phase SPI Clock Phase
 241   * @{
 242   */
 243 #define SPI_PHASE_1EDGE                 (0x00000000U)
 244 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 245 /**
 246   * @}
 247   */
 248
 249 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
 250   * @{
 251   */
 252 #define SPI_NSS_SOFT                    SPI_CR1_SSM
 253 #define SPI_NSS_HARD_INPUT              (0x00000000U)
 254 #define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
 255 /**
 256   * @}
 257   */
 258
 259 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
 260   * @{
 261   */
 262 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
 263 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
 264 /**
 265   * @}
 266   */
 267
 268 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
 269   * @{
 270   */
 271 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
 272 #define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
 273 #define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
 274 #define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
 275 #define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
 276 #define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
 277 #define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
 278 #define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
 279 /**
 280   * @}
 281   */
 282
 283 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
 284   * @{
 285   */
 286 #define SPI_FIRSTBIT_MSB                (0x00000000U)
 287 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 288 /**
 289   * @}
 290   */
 291
 292 /** @defgroup SPI_TI_mode SPI TI Mode
 293   * @{
 294   */
 295 #define SPI_TIMODE_DISABLE              (0x00000000U)
 296 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
 297 /**
 298   * @}
 299   */
 300
 301 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
 302   * @{
 303   */
 304 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
 305 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
 306 /**
 307   * @}
 308   */
 309
 310 /** @defgroup SPI_CRC_length SPI CRC Length
 311   * @{
 312   * This parameter can be one of the following values:
 313   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
 314   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
 315   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
 316   */
 317 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
 318 #define SPI_CRC_LENGTH_8BIT             (0x00000001U)
 319 #define SPI_CRC_LENGTH_16BIT            (0x00000002U)
 320 /**
 321   * @}
 322   */
 323
 324 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
 325   * @{
 326   * This parameter can be one of the following values:
 327   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
 328   *          RXNE event is generated if the FIFO
 329   *          level is greater or equal to 1/2(16-bits).
 330   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
 331   *          level is greater or equal to 1/4(8 bits). */
 332 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
 333 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
 334 #define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
 335
 336 /**
 337   * @}
 338   */
 339
 340 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
 341   * @{
 342   */
 343 #define SPI_IT_TXE                      SPI_CR2_TXEIE
 344 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
 345 #define SPI_IT_ERR                      SPI_CR2_ERRIE
 346 /**
 347   * @}
 348   */
 349
 350 /** @defgroup SPI_Flags_definition SPI Flags Definition
 351   * @{
 352   */
 353 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
 354 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
 355 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
 356 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
 357 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
 358 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
 359 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
 360 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
 361 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
 362 /**
 363   * @}
 364   */
 365
 366 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
 367   * @{
 368   */
 369 #define SPI_FTLVL_EMPTY                 (0x00000000U)
 370 #define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
 371 #define SPI_FTLVL_HALF_FULL             (0x00001000U)
 372 #define SPI_FTLVL_FULL                  (0x00001800U)
 373
 374 /**
 375   * @}
 376   */
 377
 378 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
 379   * @{
 380   */
 381 #define SPI_FRLVL_EMPTY                 (0x00000000U)
 382 #define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
 383 #define SPI_FRLVL_HALF_FULL             (0x00000400U)
 384 #define SPI_FRLVL_FULL                  (0x00000600U)
 385 /**
 386   * @}
 387   */
 388
 389 /**
 390   * @}
 391   */
 392
 393 /* Exported macros -----------------------------------------------------------*/
 394 /** @defgroup SPI_Exported_Macros SPI Exported Macros
 395   * @{
 396   */
 397
 398 /** @brief  Reset SPI handle state.
 399   * @param  __HANDLE__ specifies the SPI Handle.
 400   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 401   * @retval None
 402   */
 403 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 404
 405 /** @brief  Enable the specified SPI interrupts.
 406   * @param  __HANDLE__ specifies the SPI Handle.
 407   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 408   * @param  __INTERRUPT__ specifies the interrupt source to enable.
 409   *         This parameter can be one of the following values:
 410   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 411   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 412   *            @arg SPI_IT_ERR: Error interrupt enable
 413   * @retval None
 414   */
 415 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 416
 417 /** @brief  Disable the specified SPI interrupts.
 418   * @param  __HANDLE__ specifies the SPI handle.
 419   *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
 420   * @param  __INTERRUPT__ specifies the interrupt source to disable.
 421   *         This parameter can be one of the following values:
 422   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 423   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 424   *            @arg SPI_IT_ERR: Error interrupt enable
 425   * @retval None
 426   */
 427 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 428
 429 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
 430   * @param  __HANDLE__ specifies the SPI Handle.
 431   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 432   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
 433   *          This parameter can be one of the following values:
 434   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 435   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 436   *            @arg SPI_IT_ERR: Error interrupt enable
 437   * @retval The new state of __IT__ (TRUE or FALSE).
 438   */
 439 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 440
 441 /** @brief  Check whether the specified SPI flag is set or not.
 442   * @param  __HANDLE__ specifies the SPI Handle.
 443   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 444   * @param  __FLAG__ specifies the flag to check.
 445   *         This parameter can be one of the following values:
 446   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
 447   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
 448   *            @arg SPI_FLAG_CRCERR: CRC error flag
 449   *            @arg SPI_FLAG_MODF: Mode fault flag
 450   *            @arg SPI_FLAG_OVR: Overrun flag
 451   *            @arg SPI_FLAG_BSY: Busy flag
 452   *            @arg SPI_FLAG_FRE: Frame format error flag
 453   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
 454   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
 455   * @retval The new state of __FLAG__ (TRUE or FALSE).
 456   */
 457 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 458
 459 /** @brief  Clear the SPI CRCERR pending flag.
 460   * @param  __HANDLE__ specifies the SPI Handle.
 461   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 462   * @retval None
 463   */
 464 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
 465
 466 /** @brief  Clear the SPI MODF pending flag.
 467   * @param  __HANDLE__ specifies the SPI Handle.
 468   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 469   * @retval None
 470   */
 471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
 472   do{                                                    \
 473     __IO uint32_t tmpreg_modf = 0x00U;                   \
 474     tmpreg_modf = (__HANDLE__)->Instance->SR;            \
 475     CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
 476     UNUSED(tmpreg_modf);                                 \
 477   } while(0U)
 478
 479 /** @brief  Clear the SPI OVR pending flag.
 480   * @param  __HANDLE__ specifies the SPI Handle.
 481   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 482   * @retval None
 483   */
 484 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
 485   do{                                              \
 486     __IO uint32_t tmpreg_ovr = 0x00U;              \
 487     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
 488     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
 489     UNUSED(tmpreg_ovr);                            \
 490   } while(0U)
 491
 492 /** @brief  Clear the SPI FRE pending flag.
 493   * @param  __HANDLE__ specifies the SPI Handle.
 494   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 495   * @retval None
 496   */
 497 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
 498   do{                                              \
 499   __IO uint32_t tmpreg_fre = 0x00U;                \
 500   tmpreg_fre = (__HANDLE__)->Instance->SR;         \
 501   UNUSED(tmpreg_fre);                              \
 502   }while(0U)
 503
 504 /** @brief  Enable the SPI peripheral.
 505   * @param  __HANDLE__ specifies the SPI Handle.
 506   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 507   * @retval None
 508   */
 509 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 510
 511 /** @brief  Disable the SPI peripheral.
 512   * @param  __HANDLE__ specifies the SPI Handle.
 513   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 514   * @retval None
 515   */
 516 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 517
 518 /**
 519   * @}
 520   */
 521
 522 /* Private macros ------------------------------------------------------------*/
 523 /** @defgroup SPI_Private_Macros SPI Private Macros
 524   * @{
 525   */
 526
 527 /** @brief  Set the SPI transmit-only mode.
 528   * @param  __HANDLE__ specifies the SPI Handle.
 529   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 530   * @retval None
 531   */
 532 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 533
 534 /** @brief  Set the SPI receive-only mode.
 535   * @param  __HANDLE__ specifies the SPI Handle.
 536   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 537   * @retval None
 538   */
 539 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 540
 541 /** @brief  Reset the CRC calculation of the SPI.
 542   * @param  __HANDLE__ specifies the SPI Handle.
 543   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 544   * @retval None
 545   */
 546 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
 547                                        SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
 548
 549 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
 550                            ((MODE) == SPI_MODE_MASTER))
 551
 552 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
 553                                 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
 554                                 ((MODE) == SPI_DIRECTION_1LINE))
 555
 556 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 557
 558 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
 559                                                 ((MODE) == SPI_DIRECTION_1LINE))
 560
 561 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
 562                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
 563                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
 564                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
 565                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
 566                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
 567                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
 568                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
 569                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
 570                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
 571                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
 572                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
 573                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
 574
 575 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
 576                            ((CPOL) == SPI_POLARITY_HIGH))
 577
 578 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
 579                            ((CPHA) == SPI_PHASE_2EDGE))
 580
 581 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
 582                          ((NSS) == SPI_NSS_HARD_INPUT) || \
 583                          ((NSS) == SPI_NSS_HARD_OUTPUT))
 584
 585 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
 586                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
 587
 588 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
 589                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
 590                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
 591                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
 592                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
 593                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
 594                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
 595                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 596
 597 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
 598                                ((BIT) == SPI_FIRSTBIT_LSB))
 599
 600 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
 601                              ((MODE) == SPI_TIMODE_ENABLE))
 602
 603 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
 604                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
 605
 606 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
 607                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
 608                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
 609
 610 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
 611
 612 #define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
 613
 614
 615 /**
 616   * @}
 617   */
 618
 619 /* Include SPI HAL Extended module */
 620 #include "stm32f3xx_hal_spi_ex.h"
 621
 622 /* Exported functions --------------------------------------------------------*/
 623 /** @addtogroup SPI_Exported_Functions
 624   * @{
 625   */
 626
 627 /** @addtogroup SPI_Exported_Functions_Group1
 628   * @{
 629   */
 630 /* Initialization/de-initialization functions  ********************************/
 631 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
 632 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
 633 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 634 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 635 /**
 636   * @}
 637   */
 638
 639 /** @addtogroup SPI_Exported_Functions_Group2
 640   * @{
 641   */
 642 /* I/O operation functions  ***************************************************/
 643 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 644 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 645 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
 646                                           uint32_t Timeout);
 647 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 648 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 649 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 650                                              uint16_t Size);
 651 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 652 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 653 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 654                                               uint16_t Size);
 655 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 656 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 657 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
 658 /* Transfer Abort functions */
 659 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
 660 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 661
 662 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 663 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 664 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 665 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
 666 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 667 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 668 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 669 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 670 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 671 /**
 672   * @}
 673   */
 674
 675 /** @addtogroup SPI_Exported_Functions_Group3
 676   * @{
 677   */
 678 /* Peripheral State and Error functions ***************************************/
 679 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
 680 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 681 /**
 682   * @}
 683   */
 684
 685 /**
 686   * @}
 687   */
 688
 689 /**
 690   * @}
 691   */
 692
 693 /**
 694   * @}
 695   */
 696
 697 #ifdef __cplusplus
 698 }
 699 #endif
 700
 701 #endif /* __STM32F3xx_HAL_SPI_H */
 702
 703 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/