lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_tsc.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of TSC HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_HAL_TSC_H
  38 #define __STM32F3xx_HAL_TSC_H
  39
  40 #ifdef __cplusplus
  41  extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f3xx_hal_def.h"
  46
  47 /** @addtogroup STM32F3xx_HAL_Driver
  48   * @{
  49   */
  50
  51 /** @addtogroup TSC
  52   * @{
  53   */
  54
  55 /* Exported types ------------------------------------------------------------*/
  56 /** @defgroup TSC_Exported_Types TSC Exported Types
  57   * @{
  58   */
  59
  60 /**
  61   * @brief TSC state structure definition
  62   */
  63 typedef enum
  64 {
  65   HAL_TSC_STATE_RESET  = 0x00U, /*!< TSC registers have their reset value */
  66   HAL_TSC_STATE_READY  = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
  67   HAL_TSC_STATE_BUSY   = 0x02U, /*!< TSC initialization or acquisition is on-going */
  68   HAL_TSC_STATE_ERROR  = 0x03U  /*!< Acquisition is completed with max count error */
  69 } HAL_TSC_StateTypeDef;
  70
  71 /**
  72   * @brief TSC group status structure definition
  73   */
  74 typedef enum
  75 {
  76   TSC_GROUP_ONGOING   = 0x00U, /*!< Acquisition on group is on-going or not started */
  77   TSC_GROUP_COMPLETED = 0x01U  /*!< Acquisition on group is completed with success (no max count error) */
  78 } TSC_GroupStatusTypeDef;
  79
  80 /**
  81   * @brief TSC init structure definition
  82   */
  83 typedef struct
  84 {
  85   uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
  86                                          This parameter can be a value of @ref TSC_CTPulseHL_Config  */
  87   uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
  88                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
  89   uint32_t SpreadSpectrum;          /*!< Spread spectrum activation
  90                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
  91   uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
  92                                          This parameter must be a number between Min_Data = 0 and Max_Data = 127U */
  93   uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
  94                                          This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
  95   uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
  96                                          This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
  97   uint32_t MaxCountValue;           /*!< Max count value
  98                                          This parameter can be a value of @ref TSC_MaxCount_Value  */
  99   uint32_t IODefaultMode;           /*!< IO default mode
 100                                          This parameter can be a value of @ref TSC_IO_Default_Mode  */
 101   uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
 102                                          This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
 103   uint32_t AcquisitionMode;         /*!< Acquisition mode
 104                                          This parameter can be a value of @ref TSC_Acquisition_Mode  */
 105   uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation
 106                                          This parameter can be set to ENABLE or DISABLE. */
 107   uint32_t ChannelIOs;              /*!< Channel IOs mask */
 108   uint32_t ShieldIOs;               /*!< Shield IOs mask */
 109   uint32_t SamplingIOs;             /*!< Sampling IOs mask */
 110 } TSC_InitTypeDef;
 111
 112 /**
 113   * @brief TSC IOs configuration structure definition
 114   */
 115 typedef struct
 116 {
 117   uint32_t ChannelIOs;  /*!< Channel IOs mask */
 118   uint32_t ShieldIOs;   /*!< Shield IOs mask */
 119   uint32_t SamplingIOs; /*!< Sampling IOs mask */
 120 } TSC_IOConfigTypeDef;
 121
 122 /**
 123   * @brief  TSC handle Structure definition
 124   */
 125 typedef struct
 126 {
 127   TSC_TypeDef               *Instance; /*!< Register base address */
 128   TSC_InitTypeDef           Init;      /*!< Initialization parameters */
 129   __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
 130   HAL_LockTypeDef           Lock;      /*!< Lock feature */
 131 } TSC_HandleTypeDef;
 132
 133 /**
 134   * @}
 135   */
 136
 137 /* Exported constants --------------------------------------------------------*/
 138 /** @defgroup TSC_Exported_Constants TSC Exported Constants
 139   * @{
 140   */
 141
 142 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length
 143   * @{
 144   */
 145 #define TSC_CTPH_1CYCLE   ((uint32_t)( 0U << 28U))
 146 #define TSC_CTPH_2CYCLES  ((uint32_t)( 1U << 28U))
 147 #define TSC_CTPH_3CYCLES  ((uint32_t)( 2U << 28U))
 148 #define TSC_CTPH_4CYCLES  ((uint32_t)( 3U << 28U))
 149 #define TSC_CTPH_5CYCLES  ((uint32_t)( 4U << 28U))
 150 #define TSC_CTPH_6CYCLES  ((uint32_t)( 5U << 28U))
 151 #define TSC_CTPH_7CYCLES  ((uint32_t)( 6U << 28U))
 152 #define TSC_CTPH_8CYCLES  ((uint32_t)( 7U << 28U))
 153 #define TSC_CTPH_9CYCLES  ((uint32_t)( 8U << 28U))
 154 #define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
 155 #define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
 156 #define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
 157 #define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
 158 #define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
 159 #define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
 160 #define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
 161 /**
 162   * @}
 163   */
 164
 165 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
 166   * @{
 167   */
 168 #define TSC_CTPL_1CYCLE   ((uint32_t)( 0U << 24U))
 169 #define TSC_CTPL_2CYCLES  ((uint32_t)( 1U << 24U))
 170 #define TSC_CTPL_3CYCLES  ((uint32_t)( 2U << 24U))
 171 #define TSC_CTPL_4CYCLES  ((uint32_t)( 3U << 24U))
 172 #define TSC_CTPL_5CYCLES  ((uint32_t)( 4U << 24U))
 173 #define TSC_CTPL_6CYCLES  ((uint32_t)( 5U << 24U))
 174 #define TSC_CTPL_7CYCLES  ((uint32_t)( 6U << 24U))
 175 #define TSC_CTPL_8CYCLES  ((uint32_t)( 7U << 24U))
 176 #define TSC_CTPL_9CYCLES  ((uint32_t)( 8U << 24U))
 177 #define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
 178 #define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
 179 #define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
 180 #define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
 181 #define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
 182 #define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
 183 #define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
 184 /**
 185   * @}
 186   */
 187
 188 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
 189   * @{
 190   */
 191 #define TSC_SS_PRESC_DIV1 (0U)
 192 #define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC)
 193 /**
 194   * @}
 195   */
 196
 197 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
 198   * @{
 199   */
 200 #define TSC_PG_PRESC_DIV1   ((uint32_t)(0U << 12U))
 201 #define TSC_PG_PRESC_DIV2   ((uint32_t)(1U << 12U))
 202 #define TSC_PG_PRESC_DIV4   ((uint32_t)(2U << 12U))
 203 #define TSC_PG_PRESC_DIV8   ((uint32_t)(3U << 12U))
 204 #define TSC_PG_PRESC_DIV16  ((uint32_t)(4U << 12U))
 205 #define TSC_PG_PRESC_DIV32  ((uint32_t)(5U << 12U))
 206 #define TSC_PG_PRESC_DIV64  ((uint32_t)(6U << 12U))
 207 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
 208 /**
 209   * @}
 210   */
 211
 212 /** @defgroup TSC_MaxCount_Value Max Count Value
 213   * @{
 214   */
 215 #define TSC_MCV_255   ((uint32_t)(0U << 5U))
 216 #define TSC_MCV_511   ((uint32_t)(1U << 5U))
 217 #define TSC_MCV_1023  ((uint32_t)(2U << 5U))
 218 #define TSC_MCV_2047  ((uint32_t)(3U << 5U))
 219 #define TSC_MCV_4095  ((uint32_t)(4U << 5U))
 220 #define TSC_MCV_8191  ((uint32_t)(5U << 5U))
 221 #define TSC_MCV_16383 ((uint32_t)(6U << 5U))
 222 /**
 223   * @}
 224   */
 225
 226 /** @defgroup TSC_IO_Default_Mode IO Default Mode
 227   * @{
 228   */
 229 #define TSC_IODEF_OUT_PP_LOW (0U)
 230 #define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
 231 /**
 232   * @}
 233   */
 234
 235 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
 236   * @{
 237   */
 238 #define TSC_SYNC_POLARITY_FALLING      (0U)
 239 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
 240 /**
 241   * @}
 242   */
 243
 244 /** @defgroup TSC_Acquisition_Mode Acquisition Mode
 245   * @{
 246   */
 247 #define TSC_ACQ_MODE_NORMAL  (0U)
 248 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
 249 /**
 250   * @}
 251   */
 252
 253 /** @defgroup TSC_IO_Mode IO Mode
 254   * @{
 255   */
 256 #define TSC_IOMODE_UNUSED   (0U)
 257 #define TSC_IOMODE_CHANNEL  (1U)
 258 #define TSC_IOMODE_SHIELD   (2U)
 259 #define TSC_IOMODE_SAMPLING (3U)
 260 /**
 261   * @}
 262   */
 263
 264 /** @defgroup TSC_interrupts_definition Interrupts definition
 265   * @{
 266   */
 267 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
 268 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
 269 /**
 270   * @}
 271   */
 272
 273 /** @defgroup TSC_flags_definition Flags definition
 274   * @{
 275   */
 276 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
 277 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
 278 /**
 279   * @}
 280   */
 281
 282 /** @defgroup TSC_Group_definition Group definition
 283   * @{
 284   */
 285 #define TSC_NB_OF_GROUPS (8U)
 286
 287 #define TSC_GROUP1 (0x00000001U)
 288 #define TSC_GROUP2 (0x00000002U)
 289 #define TSC_GROUP3 (0x00000004U)
 290 #define TSC_GROUP4 (0x00000008U)
 291 #define TSC_GROUP5 (0x00000010U)
 292 #define TSC_GROUP6 (0x00000020U)
 293 #define TSC_GROUP7 (0x00000040U)
 294 #define TSC_GROUP8 (0x00000080U)
 295 #define TSC_ALL_GROUPS (0x000000FFU)
 296
 297 #define TSC_GROUP1_IDX (0U)
 298 #define TSC_GROUP2_IDX (1U)
 299 #define TSC_GROUP3_IDX (2U)
 300 #define TSC_GROUP4_IDX (3U)
 301 #define TSC_GROUP5_IDX (4U)
 302 #define TSC_GROUP6_IDX (5U)
 303 #define TSC_GROUP7_IDX (6U)
 304 #define TSC_GROUP8_IDX (7U)
 305
 306 #define TSC_GROUP1_IO1 (0x00000001U)
 307 #define TSC_GROUP1_IO2 (0x00000002U)
 308 #define TSC_GROUP1_IO3 (0x00000004U)
 309 #define TSC_GROUP1_IO4 (0x00000008U)
 310 #define TSC_GROUP1_ALL_IOS (0x0000000FU)
 311
 312 #define TSC_GROUP2_IO1 (0x00000010U)
 313 #define TSC_GROUP2_IO2 (0x00000020U)
 314 #define TSC_GROUP2_IO3 (0x00000040U)
 315 #define TSC_GROUP2_IO4 (0x00000080U)
 316 #define TSC_GROUP2_ALL_IOS (0x000000F0U)
 317
 318 #define TSC_GROUP3_IO1 (0x00000100U)
 319 #define TSC_GROUP3_IO2 (0x00000200U)
 320 #define TSC_GROUP3_IO3 (0x00000400U)
 321 #define TSC_GROUP3_IO4 (0x00000800U)
 322 #define TSC_GROUP3_ALL_IOS (0x00000F00U)
 323
 324 #define TSC_GROUP4_IO1 (0x00001000U)
 325 #define TSC_GROUP4_IO2 (0x00002000U)
 326 #define TSC_GROUP4_IO3 (0x00004000U)
 327 #define TSC_GROUP4_IO4 (0x00008000U)
 328 #define TSC_GROUP4_ALL_IOS (0x0000F000U)
 329
 330 #define TSC_GROUP5_IO1 (0x00010000U)
 331 #define TSC_GROUP5_IO2 (0x00020000U)
 332 #define TSC_GROUP5_IO3 (0x00040000U)
 333 #define TSC_GROUP5_IO4 (0x00080000U)
 334 #define TSC_GROUP5_ALL_IOS (0x000F0000U)
 335
 336 #define TSC_GROUP6_IO1 (0x00100000U)
 337 #define TSC_GROUP6_IO2 (0x00200000U)
 338 #define TSC_GROUP6_IO3 (0x00400000U)
 339 #define TSC_GROUP6_IO4 (0x00800000U)
 340 #define TSC_GROUP6_ALL_IOS (0x00F00000U)
 341
 342 #define TSC_GROUP7_IO1 (0x01000000U)
 343 #define TSC_GROUP7_IO2 (0x02000000U)
 344 #define TSC_GROUP7_IO3 (0x04000000U)
 345 #define TSC_GROUP7_IO4 (0x08000000U)
 346 #define TSC_GROUP7_ALL_IOS (0x0F000000U)
 347
 348 #define TSC_GROUP8_IO1 (0x10000000U)
 349 #define TSC_GROUP8_IO2 (0x20000000U)
 350 #define TSC_GROUP8_IO3 (0x40000000U)
 351 #define TSC_GROUP8_IO4 (0x80000000U)
 352 #define TSC_GROUP8_ALL_IOS (0xF0000000U)
 353
 354 #define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
 355 /**
 356   * @}
 357   */
 358
 359 /**
 360   * @}
 361   */
 362
 363 /* Exported macros -----------------------------------------------------------*/
 364
 365 /** @defgroup TSC_Exported_Macros TSC Exported Macros
 366  * @{
 367  */
 368
 369 /** @brief Reset TSC handle state.
 370   * @param  __HANDLE__ TSC handle
 371   * @retval None
 372   */
 373 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
 374
 375 /**
 376   * @brief Enable the TSC peripheral.
 377   * @param  __HANDLE__ TSC handle
 378   * @retval None
 379   */
 380 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
 381
 382 /**
 383   * @brief Disable the TSC peripheral.
 384   * @param  __HANDLE__ TSC handle
 385   * @retval None
 386   */
 387 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
 388
 389 /**
 390   * @brief Start acquisition.
 391   * @param  __HANDLE__ TSC handle
 392   * @retval None
 393   */
 394 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
 395
 396 /**
 397   * @brief Stop acquisition.
 398   * @param  __HANDLE__ TSC handle
 399   * @retval None
 400   */
 401 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
 402
 403 /**
 404   * @brief Set IO default mode to output push-pull low.
 405   * @param  __HANDLE__ TSC handle
 406   * @retval None
 407   */
 408 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
 409
 410 /**
 411   * @brief Set IO default mode to input floating.
 412   * @param  __HANDLE__ TSC handle
 413   * @retval None
 414   */
 415 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
 416
 417 /**
 418   * @brief Set synchronization polarity to falling edge.
 419   * @param  __HANDLE__ TSC handle
 420   * @retval None
 421   */
 422 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
 423
 424 /**
 425   * @brief Set synchronization polarity to rising edge and high level.
 426   * @param  __HANDLE__ TSC handle
 427   * @retval None
 428   */
 429 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
 430
 431 /**
 432   * @brief Enable TSC interrupt.
 433   * @param  __HANDLE__ TSC handle
 434   * @param  __INTERRUPT__ TSC interrupt
 435   * @retval None
 436   */
 437 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
 438
 439 /**
 440   * @brief Disable TSC interrupt.
 441   * @param  __HANDLE__ TSC handle
 442   * @param  __INTERRUPT__ TSC interrupt
 443   * @retval None
 444   */
 445 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
 446
 447 /** @brief Check whether the specified TSC interrupt source is enabled or not.
 448   * @param  __HANDLE__ TSC Handle
 449   * @param  __INTERRUPT__ TSC interrupt
 450   * @retval SET or RESET
 451   */
 452 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 453
 454 /**
 455   * @brief Check whether the specified TSC flag is set or not.
 456   * @param  __HANDLE__ TSC handle
 457   * @param  __FLAG__ TSC flag
 458   * @retval SET or RESET
 459   */
 460 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 461
 462 /**
 463   * @brief Clear the TSC's pending flag.
 464   * @param  __HANDLE__ TSC handle
 465   * @param  __FLAG__ TSC flag
 466   * @retval None
 467   */
 468 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 469
 470 /**
 471   * @brief Enable schmitt trigger hysteresis on a group of IOs.
 472   * @param  __HANDLE__ TSC handle
 473   * @param  __GX_IOY_MASK__ IOs mask
 474   * @retval None
 475   */
 476 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
 477
 478 /**
 479   * @brief Disable schmitt trigger hysteresis on a group of IOs.
 480   * @param  __HANDLE__ TSC handle
 481   * @param  __GX_IOY_MASK__ IOs mask
 482   * @retval None
 483   */
 484 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 485
 486 /**
 487   * @brief Open analog switch on a group of IOs.
 488   * @param  __HANDLE__ TSC handle
 489   * @param  __GX_IOY_MASK__ IOs mask
 490   * @retval None
 491   */
 492 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 493
 494 /**
 495   * @brief Close analog switch on a group of IOs.
 496   * @param  __HANDLE__ TSC handle
 497   * @param  __GX_IOY_MASK__ IOs mask
 498   * @retval None
 499   */
 500 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
 501
 502 /**
 503   * @brief Enable a group of IOs in channel mode.
 504   * @param  __HANDLE__ TSC handle
 505   * @param  __GX_IOY_MASK__ IOs mask
 506   * @retval None
 507   */
 508 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
 509
 510 /**
 511   * @brief Disable a group of channel IOs.
 512   * @param  __HANDLE__ TSC handle
 513   * @param  __GX_IOY_MASK__ IOs mask
 514   * @retval None
 515   */
 516 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 517
 518 /**
 519   * @brief Enable a group of IOs in sampling mode.
 520   * @param  __HANDLE__ TSC handle
 521   * @param  __GX_IOY_MASK__ IOs mask
 522   * @retval None
 523   */
 524 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
 525
 526 /**
 527   * @brief Disable a group of sampling IOs.
 528   * @param  __HANDLE__ TSC handle
 529   * @param  __GX_IOY_MASK__ IOs mask
 530   * @retval None
 531   */
 532 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 533
 534 /**
 535   * @brief Enable acquisition groups.
 536   * @param  __HANDLE__ TSC handle
 537   * @param  __GX_MASK__ Groups mask
 538   * @retval None
 539   */
 540 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
 541
 542 /**
 543   * @brief Disable acquisition groups.
 544   * @param  __HANDLE__ TSC handle
 545   * @param  __GX_MASK__ Groups mask
 546   * @retval None
 547   */
 548 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
 549
 550 /** @brief Gets acquisition group status.
 551   * @param  __HANDLE__ TSC Handle
 552   * @param  __GX_INDEX__ Group index
 553   * @retval SET or RESET
 554   */
 555 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
 556 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
 557
 558 /**
 559   * @}
 560   */
 561
 562 /* Private macros ------------------------------------------------------------*/
 563
 564 /** @defgroup TSC_Private_Macros TSC Private Macros
 565   * @{
 566   */
 567
 568 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
 569                           ((VAL) == TSC_CTPH_2CYCLES) || \
 570                           ((VAL) == TSC_CTPH_3CYCLES) || \
 571                           ((VAL) == TSC_CTPH_4CYCLES) || \
 572                           ((VAL) == TSC_CTPH_5CYCLES) || \
 573                           ((VAL) == TSC_CTPH_6CYCLES) || \
 574                           ((VAL) == TSC_CTPH_7CYCLES) || \
 575                           ((VAL) == TSC_CTPH_8CYCLES) || \
 576                           ((VAL) == TSC_CTPH_9CYCLES) || \
 577                           ((VAL) == TSC_CTPH_10CYCLES) || \
 578                           ((VAL) == TSC_CTPH_11CYCLES) || \
 579                           ((VAL) == TSC_CTPH_12CYCLES) || \
 580                           ((VAL) == TSC_CTPH_13CYCLES) || \
 581                           ((VAL) == TSC_CTPH_14CYCLES) || \
 582                           ((VAL) == TSC_CTPH_15CYCLES) || \
 583                           ((VAL) == TSC_CTPH_16CYCLES))
 584
 585 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
 586                           ((VAL) == TSC_CTPL_2CYCLES) || \
 587                           ((VAL) == TSC_CTPL_3CYCLES) || \
 588                           ((VAL) == TSC_CTPL_4CYCLES) || \
 589                           ((VAL) == TSC_CTPL_5CYCLES) || \
 590                           ((VAL) == TSC_CTPL_6CYCLES) || \
 591                           ((VAL) == TSC_CTPL_7CYCLES) || \
 592                           ((VAL) == TSC_CTPL_8CYCLES) || \
 593                           ((VAL) == TSC_CTPL_9CYCLES) || \
 594                           ((VAL) == TSC_CTPL_10CYCLES) || \
 595                           ((VAL) == TSC_CTPL_11CYCLES) || \
 596                           ((VAL) == TSC_CTPL_12CYCLES) || \
 597                           ((VAL) == TSC_CTPL_13CYCLES) || \
 598                           ((VAL) == TSC_CTPL_14CYCLES) || \
 599                           ((VAL) == TSC_CTPL_15CYCLES) || \
 600                           ((VAL) == TSC_CTPL_16CYCLES))
 601
 602 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
 603
 604 #define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
 605
 606 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
 607
 608 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
 609                               ((VAL) == TSC_PG_PRESC_DIV2) || \
 610                               ((VAL) == TSC_PG_PRESC_DIV4) || \
 611                               ((VAL) == TSC_PG_PRESC_DIV8) || \
 612                               ((VAL) == TSC_PG_PRESC_DIV16) || \
 613                               ((VAL) == TSC_PG_PRESC_DIV32) || \
 614                               ((VAL) == TSC_PG_PRESC_DIV64) || \
 615                               ((VAL) == TSC_PG_PRESC_DIV128))
 616
 617 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
 618                          ((VAL) == TSC_MCV_511) || \
 619                          ((VAL) == TSC_MCV_1023) || \
 620                          ((VAL) == TSC_MCV_2047) || \
 621                          ((VAL) == TSC_MCV_4095) || \
 622                          ((VAL) == TSC_MCV_8191) || \
 623                          ((VAL) == TSC_MCV_16383))
 624
 625 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
 626
 627 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
 628
 629 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
 630
 631 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
 632                             ((VAL) == TSC_IOMODE_CHANNEL) || \
 633                             ((VAL) == TSC_IOMODE_SHIELD) || \
 634                             ((VAL) == TSC_IOMODE_SAMPLING))
 635
 636 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
 637
 638 #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
 639
 640 /**
 641   * @}
 642   */
 643
 644 /* Exported functions --------------------------------------------------------*/
 645 /** @addtogroup TSC_Exported_Functions
 646   * @{
 647   */
 648
 649 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
 650  *  @{
 651  */
 652  /* Initialization and de-initialization functions *****************************/
 653 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
 654 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
 655 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
 656 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
 657 /**
 658   * @}
 659   */
 660
 661 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
 662  *  @{
 663  */
 664 /* IO operation functions *****************************************************/
 665 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
 666 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
 667 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
 668 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
 669 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
 670 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
 671 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
 672 /**
 673   * @}
 674   */
 675
 676 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
 677  *  @{
 678  */
 679 /* Peripheral Control functions ***********************************************/
 680 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
 681 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
 682 /**
 683   * @}
 684   */
 685
 686 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
 687  *  @{
 688  */
 689 /* Peripheral State and Error functions ***************************************/
 690 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
 691 /**
 692   * @}
 693   */
 694
 695 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
 696  * @{
 697  */
 698 /******* TSC IRQHandler and Callbacks used in Interrupt mode */
 699 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
 700 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
 701 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
 702 /**
 703   * @}
 704   */
 705
 706 /**
 707   * @}
 708   */
 709
 710 /**
 711   * @}
 712   */
 713
 714 /**
 715   * @}
 716   */
 717
 718 #ifdef __cplusplus
 719 }
 720 #endif
 721
 722 #endif /*__STM32F3xx_TSC_H */
 723
 724 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/