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1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_ADC_H
38 #define __STM32F3xx_LL_ADC_H
40 #ifdef __cplusplus
42 #endif
44 /* Includes ------------------------------------------------------------------*/
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
51 /* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. */
52 /* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
53 /* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
54 /* features (refer to reference manual). */
55 /* - STM32F37x: */
56 /* ADC IP 1Msamples/sec, 1 ADC instance */
57 /* This file contains the drivers of these ADC IP, located in 2 area */
58 /* delimited by compilation switches. */
60 #if defined(ADC5_V1_1)
62 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
64 /** @defgroup ADC_LL ADC
65 * @{
66 */
68 /* Private types -------------------------------------------------------------*/
69 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
73 * @{
74 */
76 /* Internal mask for ADC group regular sequencer: */
77 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
78 /* - sequencer register offset */
79 /* - sequencer rank bits position into the selected register */
81 /* Internal register offset for ADC group regular sequencer configuration */
82 /* (offset placed into a spare area of literal definition) */
83 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
84 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
85 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
86 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
88 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
89 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
91 /* Definition of ADC group regular sequencer bits information to be inserted */
92 /* into ADC group regular sequencer ranks literals definition. */
93 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
94 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
95 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
96 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
97 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
98 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
99 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
100 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
101 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
102 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
103 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
104 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
105 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
106 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
107 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
108 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
112 /* Internal mask for ADC group injected sequencer: */
113 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
114 /* - data register offset */
115 /* - sequencer rank bits position into the selected register */
117 /* Internal register offset for ADC group injected data register */
118 /* (offset placed into a spare area of literal definition) */
119 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
120 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
121 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
122 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
124 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
125 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
127 /* Definition of ADC group injected sequencer bits information to be inserted */
128 /* into ADC group injected sequencer ranks literals definition. */
129 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
130 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
131 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
132 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
136 /* Internal mask for ADC group regular trigger: */
137 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
138 /* - regular trigger source */
139 /* - regular trigger edge */
140 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
142 /* Mask containing trigger source masks for each of possible */
143 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
144 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
145 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
146 ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \
147 ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \
148 ((ADC_CFGR_EXTSEL) << (4U * 3U)) )
150 /* Mask containing trigger edge masks for each of possible */
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
153 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
154 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
155 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
156 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
158 /* Definition of ADC group regular trigger bits information. */
159 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
160 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
164 /* Internal definitions for ADC group regular trigger sources: */
165 /* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources */
166 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
167 /* available on the selected device). */
169 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
170 /* Internal mask offset for ADC group injected trigger sources */
171 /* available only on specific ADC instances. */
172 /* (offset placed into a spare area of literal definition) */
173 #define ADC_REG_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
174 #define ADC_REG_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
175 #endif
177 /* Internal mask for ADC group injected trigger: */
178 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
179 /* - injected trigger source */
180 /* - injected trigger edge */
181 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
183 /* Mask containing trigger source masks for each of possible */
184 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
185 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
186 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
187 ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \
188 ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \
189 ((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
191 /* Mask containing trigger edge masks for each of possible */
192 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
193 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
194 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
195 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
196 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
197 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
199 /* Definition of ADC group injected trigger bits information. */
200 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
201 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
205 /* Internal definitions for ADC group injected trigger sources: */
206 /* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources */
207 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
208 /* available on the selected device). */
210 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
211 /* Internal mask offset for ADC group injected trigger sources */
212 /* available only on specific ADC instances. */
213 /* (offset placed into a spare area of literal definition) */
214 #define ADC_INJ_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
215 #define ADC_INJ_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
216 #endif
221 /* Internal mask for ADC channel: */
222 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
223 /* - channel identifier defined by number */
224 /* - channel identifier defined by bitfield */
225 /* - channel differentiation between external channels (connected to */
226 /* GPIO pins) and internal channels (connected to internal paths) */
227 /* - channel sampling time defined by SMPRx register offset */
228 /* and SMPx bits positions into SMPRx register */
229 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
230 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
231 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
232 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
233 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
234 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
236 /* Channel differentiation between external and internal channels */
238 #define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
239 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
241 /* Internal register offset for ADC channel sampling time configuration */
242 /* (offset placed into a spare area of literal definition) */
243 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
244 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
245 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
247 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
248 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
250 /* Definition of channels ID number information to be inserted into */
251 /* channels literals definition. */
252 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
253 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
254 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
255 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
256 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
257 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
258 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
259 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
260 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
261 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
262 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
263 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
264 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
265 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
266 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
267 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
268 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
269 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
270 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
272 /* Definition of channels ID bitfield information to be inserted into */
273 /* channels literals definition. */
274 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
275 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
276 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
277 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
278 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
279 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
280 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
281 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
282 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
283 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
284 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
285 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
286 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
287 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
288 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
289 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
290 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
291 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
292 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
294 /* Definition of channels sampling time information to be inserted into */
295 /* channels literals definition. */
296 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
297 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
298 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
299 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
300 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
301 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
302 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
303 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
304 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
305 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
306 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
307 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
308 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
309 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
310 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
311 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
312 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
313 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
314 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
317 /* Internal mask for ADC mode single or differential ended: */
318 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
319 /* the relevant bits for: */
320 /* (concatenation of multiple bits used in different registers) */
321 /* - ADC calibration: calibration start, calibration factor get or set */
322 /* - ADC channels: set each ADC channel ending mode */
323 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
324 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
325 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
326 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
329 /* Internal mask for ADC analog watchdog: */
330 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
331 /* (concatenation of multiple bits used in different analog watchdogs, */
332 /* (feature of several watchdogs not available on all STM32 families)). */
333 /* - analog watchdog 1: monitored channel defined by number, */
334 /* selection of ADC group (ADC groups regular and-or injected). */
335 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
336 /* selection on groups. */
338 /* Internal register offset for ADC analog watchdog channel configuration */
339 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
340 #define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
341 #define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
343 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
344 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
345 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
346 #define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
348 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
350 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
351 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
352 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
354 /* Internal register offset for ADC analog watchdog threshold configuration */
355 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
356 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
357 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
358 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
361 /* Internal mask for ADC offset: */
362 /* Internal register offset for ADC offset number configuration */
363 #define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
364 #define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
365 #define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
366 #define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
367 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
370 /* ADC registers bits positions */
371 #define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
372 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
373 #define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
374 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
375 #define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
378 /* ADC registers bits groups */
379 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
382 /* ADC internal channels related definitions */
383 /* Internal voltage reference VrefInt */
384 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
385 #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
386 /* Temperature sensor */
387 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature 25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
388 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
389 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 25) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
390 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
391 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
394 /**
395 * @}
396 */
399 /* Private macros ------------------------------------------------------------*/
400 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
401 * @{
402 */
404 /**
405 * @brief Driver macro reserved for internal use: isolate bits with the
406 * selected mask and shift them to the register LSB
407 * (shift mask on register position bit 0).
408 * @param __BITS__ Bits in register 32 bits
409 * @param __MASK__ Mask in register 32 bits
410 * @retval Bits in register 32 bits
411 */
412 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
413 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
415 /**
416 * @brief Driver macro reserved for internal use: set a pointer to
417 * a register from a register basis from which an offset
418 * is applied.
419 * @param __REG__ Register basis from which the offset is applied.
420 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
421 * @retval Pointer to register address
422 */
423 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
424 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
426 /**
427 * @}
428 */
431 /* Exported types ------------------------------------------------------------*/
432 #if defined(USE_FULL_LL_DRIVER)
433 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
434 * @{
435 */
437 /**
438 * @brief Structure definition of some features of ADC common parameters
439 * and multimode
440 * (all ADC instances belonging to the same ADC common instance).
441 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
442 * is conditioned to ADC instances state (all ADC instances
443 * sharing the same ADC common instance):
444 * All ADC instances sharing the same ADC common instance must be
445 * disabled.
446 */
448 {
450 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
451 @note On this STM32 serie, if ADC group injected is used, some
452 clock ratio constraints between ADC clock and AHB clock
453 must be respected. Refer to reference manual.
455 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
457 #if defined(ADC_MULTIMODE_SUPPORT)
458 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
459 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
461 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
463 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
464 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
466 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
469 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
471 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
476 /**
477 * @brief Structure definition of some features of ADC instance.
478 * @note These parameters have an impact on ADC scope: ADC instance.
479 * Affects both group regular and group injected (availability
480 * of ADC group injected depends on STM32 families).
481 * Refer to corresponding unitary functions into
482 * @ref ADC_LL_EF_Configuration_ADC_Instance .
483 * @note The setting of these parameters by function @ref LL_ADC_Init()
484 * is conditioned to ADC state:
485 * ADC instance must be disabled.
486 * This condition is applied to all ADC features, for efficiency
487 * and compatibility over all STM32 families. However, the different
488 * features can be set under different ADC state conditions
489 * (setting possible with ADC enabled without conversion on going,
490 * ADC enabled with conversion on going, ...)
491 * Each feature can be updated afterwards with a unitary function
492 * and potentially with ADC in a different state than disabled,
493 * refer to description of each function for setting
494 * conditioned to ADC state.
495 */
497 {
499 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
501 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
504 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
506 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
509 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
511 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
515 /**
516 * @brief Structure definition of some features of ADC group regular.
517 * @note These parameters have an impact on ADC scope: ADC group regular.
518 * Refer to corresponding unitary functions into
519 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
520 * (functions with prefix "REG").
521 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
522 * is conditioned to ADC state:
523 * ADC instance must be disabled.
524 * This condition is applied to all ADC features, for efficiency
525 * and compatibility over all STM32 families. However, the different
526 * features can be set under different ADC state conditions
527 * (setting possible with ADC enabled without conversion on going,
528 * ADC enabled with conversion on going, ...)
529 * Each feature can be updated afterwards with a unitary function
530 * and potentially with ADC in a different state than disabled,
531 * refer to description of each function for setting
532 * conditioned to ADC state.
533 */
535 {
536 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
537 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
538 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
539 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
540 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
542 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
545 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
547 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
549 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
550 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
551 @note This parameter has an effect only if group regular sequencer is enabled
552 (scan length of 2 ranks or more).
554 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
556 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
557 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
558 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
560 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
562 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
563 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
565 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
568 data preserved or overwritten.
569 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
571 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
575 /**
576 * @brief Structure definition of some features of ADC group injected.
577 * @note These parameters have an impact on ADC scope: ADC group injected.
578 * Refer to corresponding unitary functions into
579 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
580 * (functions with prefix "INJ").
581 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
582 * is conditioned to ADC state:
583 * ADC instance must be disabled.
584 * This condition is applied to all ADC features, for efficiency
585 * and compatibility over all STM32 families. However, the different
586 * features can be set under different ADC state conditions
587 * (setting possible with ADC enabled without conversion on going,
588 * ADC enabled with conversion on going, ...)
589 * Each feature can be updated afterwards with a unitary function
590 * and potentially with ADC in a different state than disabled,
591 * refer to description of each function for setting
592 * conditioned to ADC state.
593 */
595 {
596 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
597 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
598 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
599 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
600 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
602 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
605 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
607 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
609 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
610 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
611 @note This parameter has an effect only if group injected sequencer is enabled
612 (scan length of 2 ranks or more).
614 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
616 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
617 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
618 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
620 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
624 /**
625 * @}
626 */
629 /* Exported constants --------------------------------------------------------*/
630 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
631 * @{
632 */
634 /** @defgroup ADC_LL_EC_FLAG ADC flags
635 * @brief Flags defines which can be used with LL_ADC_ReadReg function
636 * @{
637 */
639 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
640 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
642 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
643 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
644 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
645 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
649 #if defined(ADC_MULTIMODE_SUPPORT)
650 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
651 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
652 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
653 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
654 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
655 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
656 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
657 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
658 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
659 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
660 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
661 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
662 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
663 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
664 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
665 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
666 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
667 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
668 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
669 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
670 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
671 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
672 #endif
673 /**
674 * @}
675 */
677 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
678 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
679 * @{
680 */
682 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
683 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
685 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
686 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
687 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
688 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
692 /**
693 * @}
694 */
696 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
697 * @{
698 */
699 /* List of ADC registers intended to be used (most commonly) with */
700 /* DMA transfer. */
701 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
702 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
703 #if defined(ADC_MULTIMODE_SUPPORT)
704 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
705 #endif
706 /**
707 * @}
708 */
710 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
711 * @{
712 */
713 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
714 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
715 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
716 #define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
717 /**
718 * @}
719 */
721 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
722 * @{
723 */
724 /* Note: Other measurement paths to internal channels may be available */
725 /* (connections to other peripherals). */
726 /* If they are not listed below, they do not require any specific */
727 /* path enable. In this case, Access to measurement path is done */
728 /* only by selecting the corresponding ADC internal channel. */
729 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
730 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
731 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
732 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
733 /**
734 * @}
735 */
737 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
738 * @{
739 */
744 /**
745 * @}
746 */
748 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
749 * @{
750 */
751 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
752 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
753 /**
754 * @}
755 */
757 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
758 * @{
759 */
761 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
762 /**
763 * @}
764 */
766 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
767 * @{
768 */
769 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
770 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
771 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
772 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
773 /**
774 * @}
775 */
777 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
778 * @{
779 */
780 #define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
781 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
782 /**
783 * @}
784 */
786 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
787 * @{
788 */
789 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
790 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
791 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
792 /**
793 * @}
794 */
796 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
797 * @{
798 */
799 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
800 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
801 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
802 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
803 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
804 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
805 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
806 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
807 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
808 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
809 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
810 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
811 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
812 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
813 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
814 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
815 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
816 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
817 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
818 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
819 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
820 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
821 #if defined(OPAMP1_CSR_OPAMP1EN)
822 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
823 #endif
824 #if defined(OPAMP2_CSR_OPAMP2EN)
825 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
826 #endif
827 #if defined(OPAMP3_CSR_OPAMP3EN)
828 #define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
829 #endif
830 #if defined(OPAMP4_CSR_OPAMP4EN)
831 #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
832 #endif
833 /**
834 * @}
835 */
837 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
838 * @{
839 */
840 #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
841 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
842 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for */
843 /* ADC instances ADCx available on the selected device) */
844 /* Note: Literal without suffix "ADCxy" means that external trigger */
845 /* is available on all ADC instances. */
846 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
847 /* register SYSCFG_CFGR4. Refer to reference manual. */
848 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
849 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
850 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
851 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
852 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
853 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
854 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
855 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
856 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
857 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
858 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
859 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
860 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
861 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
862 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
863 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
864 #if defined(STM32F303xE) || defined(STM32F398xx)
865 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
866 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
867 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
868 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
869 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
872 /* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for */
873 /* ADC instances ADCx available on the selected device) */
874 /* Note: Literal without suffix "ADCxy" means that external trigger */
875 /* is available on all ADC instances. */
876 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
877 /* register SYSCFG_CFGR4. Refer to reference manual. */
878 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
879 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
880 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
881 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
882 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
883 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
884 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
885 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
886 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
887 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
888 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
889 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
890 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
891 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
892 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
893 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
894 #if defined(STM32F303xE) || defined(STM32F398xx)
895 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
896 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
897 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
900 #elif defined(STM32F303x8) || defined(STM32F328xx)
901 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
902 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
903 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
904 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
905 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
906 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
907 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
908 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
909 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
910 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
911 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
912 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
913 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
914 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
915 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
917 #elif defined(STM32F334x8)
918 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
919 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
920 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
921 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
922 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
923 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
924 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
925 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
926 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
927 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
928 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
929 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
930 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
931 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
933 #elif defined(STM32F302xC) || defined(STM32F302xE)
934 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
935 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
936 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
937 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
938 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
939 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
940 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
941 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
942 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
943 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
944 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
945 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
946 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
947 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
949 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
950 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
951 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
952 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
953 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
954 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
955 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
956 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
957 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
958 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
959 #endif
960 /**
961 * @}
962 */
964 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
965 * @{
966 */
967 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
968 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
969 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
970 /**
971 * @}
972 */
974 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
975 * @{
976 */
977 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
978 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
979 /**
980 * @}
981 */
983 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
984 * @{
985 */
986 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
987 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
988 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
989 /**
990 * @}
991 */
993 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
994 * @{
995 */
996 #define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
997 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
998 /**
999 * @}
1000 */
1002 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1003 * @{
1004 */
1005 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1006 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1007 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1008 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1009 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1010 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1011 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1012 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1013 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1014 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1015 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1016 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1017 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1018 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1019 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1020 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1021 /**
1022 * @}
1023 */
1025 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1026 * @{
1027 */
1028 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
1029 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1030 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1031 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1032 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1033 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1034 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1035 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1036 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1037 /**
1038 * @}
1039 */
1041 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1042 * @{
1043 */
1044 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1045 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1046 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1047 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1048 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1049 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1050 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1051 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1052 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1053 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1054 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1055 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1056 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1057 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1058 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1059 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1060 /**
1061 * @}
1062 */
1064 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1065 * @{
1066 */
1067 #define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
1068 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
1069 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for */
1070 /* ADC instances ADCx available on the selected device) */
1071 /* Note: Literal without suffix "ADCxy" means that external trigger */
1072 /* is available on all ADC instances. */
1073 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
1074 /* register SYSCFG_CFGR4. Refer to reference manual. */
1075 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1076 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1077 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1078 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1079 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1080 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1081 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1082 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1083 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1084 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1085 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1086 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1087 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1088 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1089 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1090 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1091 #if defined(STM32F303xE) || defined(STM32F398xx)
1092 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
1093 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
1094 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1097 /* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for */
1098 /* ADC instances ADCx available on the selected device) */
1099 /* Note: Literal without suffix "ADCxy" means that external trigger */
1100 /* is available on all ADC instances. */
1101 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event). */
1102 /* JEXT2 is the main trigger, JEXT5 is kept as spare trigger for */
1103 /* future devices. */
1104 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
1105 /* register SYSCFG_CFGR4. Refer to reference manual. */
1106 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1107 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1108 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1109 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1110 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1111 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1112 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1113 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1114 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1115 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1116 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1117 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1118 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1119 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
1120 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1121 #if defined(STM32F303xE) || defined(STM32F398xx)
1122 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
1123 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
1124 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1127 #elif defined(STM32F303x8) || defined(STM32F328xx)
1128 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1129 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1130 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1131 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1132 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1133 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1134 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1135 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1136 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1137 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1138 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1139 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1140 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1141 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1142 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1143 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1145 #elif defined(STM32F334x8)
1146 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1147 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1148 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1149 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1150 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1151 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1152 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1153 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
1154 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
1155 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1156 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1157 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1158 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1159 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1161 #elif defined(STM32F302xC) || defined(STM32F302xE)
1162 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1163 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1164 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1165 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1166 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1167 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1168 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1169 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1170 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1171 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1172 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1173 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1174 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1176 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1177 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1178 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1179 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1180 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1181 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1182 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1183 #endif
1184 /**
1185 * @}
1186 */
1188 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1189 * @{
1190 */
1191 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1192 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1193 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1194 /**
1195 * @}
1196 */
1198 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1199 * @{
1200 */
1201 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1202 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1203 /**
1204 * @}
1205 */
1207 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1208 * @{
1209 */
1210 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1211 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1212 /**
1213 * @}
1214 */
1216 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1217 * @{
1218 */
1219 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1220 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1221 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1222 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1223 /**
1224 * @}
1225 */
1227 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1228 * @{
1229 */
1230 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
1231 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1232 /**
1233 * @}
1234 */
1236 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1237 * @{
1238 */
1239 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1240 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1241 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1242 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1243 /**
1244 * @}
1245 */
1247 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1248 * @{
1249 */
1251 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1252 #define LL_ADC_SAMPLINGTIME_4CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 4.5 ADC clock cycles */
1253 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
1254 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 19.5 ADC clock cycles */
1255 #define LL_ADC_SAMPLINGTIME_61CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
1256 #define LL_ADC_SAMPLINGTIME_181CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 181.5 ADC clock cycles */
1257 #define LL_ADC_SAMPLINGTIME_601CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
1258 /**
1259 * @}
1260 */
1262 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1263 * @{
1264 */
1265 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1266 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1267 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1268 /**
1269 * @}
1270 */
1272 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1273 * @{
1274 */
1275 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1276 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1277 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1278 /**
1279 * @}
1280 */
1282 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1283 * @{
1284 */
1285 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
1286 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1287 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1288 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1289 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1290 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1291 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1292 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1293 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1294 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1295 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1296 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1297 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1298 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1299 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1300 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1301 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1302 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1303 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1304 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1305 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1306 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1307 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1308 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1309 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1310 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1311 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1312 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1313 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1314 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1315 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1316 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1317 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1318 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1319 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1320 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1321 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1322 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1323 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1324 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1325 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1326 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1327 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1328 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1329 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1330 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1331 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1332 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1333 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1334 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1335 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1336 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1337 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1338 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1339 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1340 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1341 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1342 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1343 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1344 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1345 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1346 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1347 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1348 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1349 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1350 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1351 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1352 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1353 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1354 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1355 #if defined(OPAMP1_CSR_OPAMP1EN)
1356 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1357 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1358 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1359 #endif
1360 #if defined(OPAMP2_CSR_OPAMP2EN)
1361 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1362 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1363 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1364 #endif
1365 #if defined(OPAMP3_CSR_OPAMP3EN)
1366 #define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1367 #define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1368 #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1369 #endif
1370 #if defined(OPAMP4_CSR_OPAMP4EN)
1371 #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1372 #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1373 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1374 #endif
1375 /**
1376 * @}
1377 */
1379 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1380 * @{
1381 */
1384 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1385 /**
1386 * @}
1387 */
1389 #if defined(ADC_MULTIMODE_SUPPORT)
1390 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1391 * @{
1392 */
1393 #define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */
1394 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1395 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1396 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1397 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1398 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1399 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1400 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1401 /**
1402 * @}
1403 */
1405 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1406 * @{
1407 */
1408 #define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1409 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1410 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1411 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1412 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1413 /**
1414 * @}
1415 */
1417 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1418 * @{
1419 */
1420 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1421 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1422 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1423 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1424 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1425 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1426 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1427 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1428 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1429 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1430 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1431 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1432 /**
1433 * @}
1434 */
1436 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1437 * @{
1438 */
1439 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1440 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1441 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1442 /**
1443 * @}
1444 */
1449 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1450 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1451 * not timeout values.
1452 * For details on delays values, refer to descriptions in source code
1453 * above each literal definition.
1454 * @{
1455 */
1457 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1458 /* not timeout values. */
1459 /* Timeout values for ADC operations are dependent to device clock */
1460 /* configuration (system clock versus ADC clock), */
1461 /* and therefore must be defined in user application. */
1462 /* Indications for estimation of ADC timeout delays, for this */
1463 /* STM32 serie: */
1464 /* - ADC calibration time: maximum delay is 112/fADC. */
1465 /* (refer to device datasheet, parameter "tCAL") */
1466 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1467 /* (refer to device datasheet, parameter "tSTAB") */
1468 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1469 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1470 /* cycles */
1471 /* - ADC conversion time: duration depending on ADC clock and ADC */
1472 /* configuration. */
1473 /* (refer to device reference manual, section "Timing") */
1475 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1476 /* Delay set to maximum value (refer to device datasheet, */
1477 /* parameter "tADCVREG_STUP"). */
1478 /* Unit: us */
1479 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1481 /* Delay for internal voltage reference stabilization time. */
1482 /* Delay set to maximum value (refer to device datasheet, */
1483 /* parameter "tstart_vrefint"). */
1484 /* Unit: us */
1485 #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */
1487 /* Delay for temperature sensor stabilization time. */
1488 /* Literal set to maximum value (refer to device datasheet, */
1489 /* parameter "tSTART"). */
1490 /* Unit: us */
1491 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
1493 /* Delay required between ADC end of calibration and ADC enable. */
1494 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1495 /* are required between ADC end of calibration and ADC enable. */
1496 /* Wait time can be computed in user application by waiting for the */
1497 /* equivalent number of CPU cycles, by taking into account */
1498 /* ratio of CPU clock versus ADC clock prescalers. */
1499 /* Unit: ADC clock cycles. */
1500 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */
1502 /**
1503 * @}
1504 */
1506 /**
1507 * @}
1508 */
1511 /* Exported macro ------------------------------------------------------------*/
1512 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1513 * @{
1514 */
1516 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1517 * @{
1518 */
1520 /**
1521 * @brief Write a value in ADC register
1522 * @param __INSTANCE__ ADC Instance
1523 * @param __REG__ Register to be written
1524 * @param __VALUE__ Value to be written in the register
1525 * @retval None
1526 */
1527 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1529 /**
1530 * @brief Read a value in ADC register
1531 * @param __INSTANCE__ ADC Instance
1532 * @param __REG__ Register to be read
1533 * @retval Register value
1534 */
1535 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1536 /**
1537 * @}
1538 */
1540 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1541 * @{
1542 */
1544 /**
1545 * @brief Helper macro to get ADC channel number in decimal format
1546 * from literals LL_ADC_CHANNEL_x.
1547 * @note Example:
1548 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1549 * will return decimal number "4".
1550 * @note The input can be a value from functions where a channel
1551 * number is returned, either defined with number
1552 * or with bitfield (only one bit must be set).
1553 * @param __CHANNEL__ This parameter can be one of the following values:
1554 * @arg @ref LL_ADC_CHANNEL_0
1555 * @arg @ref LL_ADC_CHANNEL_1
1556 * @arg @ref LL_ADC_CHANNEL_2
1557 * @arg @ref LL_ADC_CHANNEL_3
1558 * @arg @ref LL_ADC_CHANNEL_4
1559 * @arg @ref LL_ADC_CHANNEL_5
1560 * @arg @ref LL_ADC_CHANNEL_6
1561 * @arg @ref LL_ADC_CHANNEL_7
1562 * @arg @ref LL_ADC_CHANNEL_8
1563 * @arg @ref LL_ADC_CHANNEL_9
1564 * @arg @ref LL_ADC_CHANNEL_10
1565 * @arg @ref LL_ADC_CHANNEL_11
1566 * @arg @ref LL_ADC_CHANNEL_12
1567 * @arg @ref LL_ADC_CHANNEL_13
1568 * @arg @ref LL_ADC_CHANNEL_14
1569 * @arg @ref LL_ADC_CHANNEL_15
1570 * @arg @ref LL_ADC_CHANNEL_16
1571 * @arg @ref LL_ADC_CHANNEL_17
1572 * @arg @ref LL_ADC_CHANNEL_18
1573 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1574 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1575 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1576 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1577 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1578 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1579 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1580 *
1581 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1582 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1583 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1584 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1585 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1586 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1587 * @retval Value between Min_Data=0 and Max_Data=18
1588 */
1589 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1590 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
1591 ? ( \
1592 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1593 ) \
1594 : \
1595 ( \
1596 POSITION_VAL((__CHANNEL__)) \
1597 ) \
1598 )
1600 /**
1601 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1602 * from number in decimal format.
1603 * @note Example:
1604 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1605 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1606 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1607 * @retval Returned value can be one of the following values:
1608 * @arg @ref LL_ADC_CHANNEL_0
1609 * @arg @ref LL_ADC_CHANNEL_1
1610 * @arg @ref LL_ADC_CHANNEL_2
1611 * @arg @ref LL_ADC_CHANNEL_3
1612 * @arg @ref LL_ADC_CHANNEL_4
1613 * @arg @ref LL_ADC_CHANNEL_5
1614 * @arg @ref LL_ADC_CHANNEL_6
1615 * @arg @ref LL_ADC_CHANNEL_7
1616 * @arg @ref LL_ADC_CHANNEL_8
1617 * @arg @ref LL_ADC_CHANNEL_9
1618 * @arg @ref LL_ADC_CHANNEL_10
1619 * @arg @ref LL_ADC_CHANNEL_11
1620 * @arg @ref LL_ADC_CHANNEL_12
1621 * @arg @ref LL_ADC_CHANNEL_13
1622 * @arg @ref LL_ADC_CHANNEL_14
1623 * @arg @ref LL_ADC_CHANNEL_15
1624 * @arg @ref LL_ADC_CHANNEL_16
1625 * @arg @ref LL_ADC_CHANNEL_17
1626 * @arg @ref LL_ADC_CHANNEL_18
1627 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1628 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1629 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1630 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1631 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1632 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1633 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1634 *
1635 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1636 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1637 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1638 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1639 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1640 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
1641 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
1642 * comparison with internal channel parameter to be done
1643 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1644 */
1645 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1646 (((__DECIMAL_NB__) <= 9U) \
1647 ? ( \
1648 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1649 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1650 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1651 ) \
1652 : \
1653 ( \
1654 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1655 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1656 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1657 ) \
1658 )
1660 /**
1661 * @brief Helper macro to determine whether the selected channel
1662 * corresponds to literal definitions of driver.
1663 * @note The different literal definitions of ADC channels are:
1664 * - ADC internal channel:
1665 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1666 * - ADC external channel (channel connected to a GPIO pin):
1667 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1668 * @note The channel parameter must be a value defined from literal
1669 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1670 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1671 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1672 * must not be a value from functions where a channel number is
1673 * returned from ADC registers,
1674 * because internal and external channels share the same channel
1675 * number in ADC registers. The differentiation is made only with
1676 * parameters definitions of driver.
1677 * @param __CHANNEL__ This parameter can be one of the following values:
1678 * @arg @ref LL_ADC_CHANNEL_0
1679 * @arg @ref LL_ADC_CHANNEL_1
1680 * @arg @ref LL_ADC_CHANNEL_2
1681 * @arg @ref LL_ADC_CHANNEL_3
1682 * @arg @ref LL_ADC_CHANNEL_4
1683 * @arg @ref LL_ADC_CHANNEL_5
1684 * @arg @ref LL_ADC_CHANNEL_6
1685 * @arg @ref LL_ADC_CHANNEL_7
1686 * @arg @ref LL_ADC_CHANNEL_8
1687 * @arg @ref LL_ADC_CHANNEL_9
1688 * @arg @ref LL_ADC_CHANNEL_10
1689 * @arg @ref LL_ADC_CHANNEL_11
1690 * @arg @ref LL_ADC_CHANNEL_12
1691 * @arg @ref LL_ADC_CHANNEL_13
1692 * @arg @ref LL_ADC_CHANNEL_14
1693 * @arg @ref LL_ADC_CHANNEL_15
1694 * @arg @ref LL_ADC_CHANNEL_16
1695 * @arg @ref LL_ADC_CHANNEL_17
1696 * @arg @ref LL_ADC_CHANNEL_18
1697 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1698 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1699 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1700 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1701 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1702 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1703 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1704 *
1705 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1706 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1707 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1708 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1709 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1710 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1711 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1712 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1713 */
1714 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1715 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1717 /**
1718 * @brief Helper macro to convert a channel defined from parameter
1719 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1720 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1721 * to its equivalent parameter definition of a ADC external channel
1722 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1723 * @note The channel parameter can be, additionally to a value
1724 * defined from parameter definition of a ADC internal channel
1725 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1726 * a value defined from parameter definition of
1727 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1728 * or a value from functions where a channel number is returned
1729 * from ADC registers.
1730 * @param __CHANNEL__ This parameter can be one of the following values:
1731 * @arg @ref LL_ADC_CHANNEL_0
1732 * @arg @ref LL_ADC_CHANNEL_1
1733 * @arg @ref LL_ADC_CHANNEL_2
1734 * @arg @ref LL_ADC_CHANNEL_3
1735 * @arg @ref LL_ADC_CHANNEL_4
1736 * @arg @ref LL_ADC_CHANNEL_5
1737 * @arg @ref LL_ADC_CHANNEL_6
1738 * @arg @ref LL_ADC_CHANNEL_7
1739 * @arg @ref LL_ADC_CHANNEL_8
1740 * @arg @ref LL_ADC_CHANNEL_9
1741 * @arg @ref LL_ADC_CHANNEL_10
1742 * @arg @ref LL_ADC_CHANNEL_11
1743 * @arg @ref LL_ADC_CHANNEL_12
1744 * @arg @ref LL_ADC_CHANNEL_13
1745 * @arg @ref LL_ADC_CHANNEL_14
1746 * @arg @ref LL_ADC_CHANNEL_15
1747 * @arg @ref LL_ADC_CHANNEL_16
1748 * @arg @ref LL_ADC_CHANNEL_17
1749 * @arg @ref LL_ADC_CHANNEL_18
1750 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1751 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1752 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1753 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1754 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1755 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1756 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1757 *
1758 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1759 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1760 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1761 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1762 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1763 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1764 * @retval Returned value can be one of the following values:
1765 * @arg @ref LL_ADC_CHANNEL_0
1766 * @arg @ref LL_ADC_CHANNEL_1
1767 * @arg @ref LL_ADC_CHANNEL_2
1768 * @arg @ref LL_ADC_CHANNEL_3
1769 * @arg @ref LL_ADC_CHANNEL_4
1770 * @arg @ref LL_ADC_CHANNEL_5
1771 * @arg @ref LL_ADC_CHANNEL_6
1772 * @arg @ref LL_ADC_CHANNEL_7
1773 * @arg @ref LL_ADC_CHANNEL_8
1774 * @arg @ref LL_ADC_CHANNEL_9
1775 * @arg @ref LL_ADC_CHANNEL_10
1776 * @arg @ref LL_ADC_CHANNEL_11
1777 * @arg @ref LL_ADC_CHANNEL_12
1778 * @arg @ref LL_ADC_CHANNEL_13
1779 * @arg @ref LL_ADC_CHANNEL_14
1780 * @arg @ref LL_ADC_CHANNEL_15
1781 * @arg @ref LL_ADC_CHANNEL_16
1782 * @arg @ref LL_ADC_CHANNEL_17
1783 * @arg @ref LL_ADC_CHANNEL_18
1784 */
1785 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1786 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1788 /**
1789 * @brief Helper macro to determine whether the internal channel
1790 * selected is available on the ADC instance selected.
1791 * @note The channel parameter must be a value defined from parameter
1792 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1793 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1794 * must not be a value defined from parameter definition of
1795 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1796 * or a value from functions where a channel number is
1797 * returned from ADC registers,
1798 * because internal and external channels share the same channel
1799 * number in ADC registers. The differentiation is made only with
1800 * parameters definitions of driver.
1801 * @param __ADC_INSTANCE__ ADC instance
1802 * @param __CHANNEL__ This parameter can be one of the following values:
1803 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1804 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1805 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1806 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1807 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1808 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1809 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1810 *
1811 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1812 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1813 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1814 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1815 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1816 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1817 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1818 * Value "1" if the internal channel selected is available on the ADC instance selected.
1819 */
1820 #if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
1821 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1822 (((__ADC_INSTANCE__) == ADC1) \
1823 ? ( \
1824 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1825 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1826 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1827 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1828 ) \
1829 : \
1830 ((__ADC_INSTANCE__) == ADC2) \
1831 ? ( \
1832 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1833 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1834 ) \
1835 : \
1836 ((__ADC_INSTANCE__) == ADC3) \
1837 ? ( \
1838 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1839 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
1840 ) \
1841 : \
1842 ((__ADC_INSTANCE__) == ADC4) \
1843 ? ( \
1844 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1845 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) \
1846 ) \
1847 : \
1848 (0U) \
1849 )
1850 #elif defined (ADC1) && defined (ADC2)
1851 #if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
1852 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1853 (((__ADC_INSTANCE__) == ADC1) \
1854 ? ( \
1855 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1856 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1857 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1858 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1859 ) \
1860 : \
1861 ((__ADC_INSTANCE__) == ADC2) \
1862 ? ( \
1863 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1864 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1865 ) \
1866 : \
1867 (0U) \
1868 )
1869 #elif defined(OPAMP2_CSR_OPAMP2EN)
1870 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1871 (((__ADC_INSTANCE__) == ADC1) \
1872 ? ( \
1873 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1874 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1875 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1876 ) \
1877 : \
1878 ((__ADC_INSTANCE__) == ADC2) \
1879 ? ( \
1880 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1881 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1882 ) \
1883 : \
1884 (0U) \
1885 )
1886 #else
1887 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1888 (((__ADC_INSTANCE__) == ADC1) \
1889 ? ( \
1890 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1891 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1892 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1893 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1894 ) \
1895 : \
1896 ((__ADC_INSTANCE__) == ADC2) \
1897 ? ( \
1898 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1899 ) \
1900 : \
1901 (0U) \
1902 )
1903 #endif
1904 #elif defined (ADC1)
1905 #if defined(OPAMP1_CSR_OPAMP1EN)
1906 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1907 ( \
1908 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1909 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1910 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1911 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1912 )
1913 #else
1914 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1915 ( \
1916 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1917 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1918 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1919 )
1920 #endif
1921 #endif
1923 /**
1924 * @brief Helper macro to define ADC analog watchdog parameter:
1925 * define a single channel to monitor with analog watchdog
1926 * from sequencer channel and groups definition.
1927 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1928 * Example:
1929 * LL_ADC_SetAnalogWDMonitChannels(
1930 * ADC1, LL_ADC_AWD1,
1931 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1932 * @param __CHANNEL__ This parameter can be one of the following values:
1933 * @arg @ref LL_ADC_CHANNEL_0
1934 * @arg @ref LL_ADC_CHANNEL_1
1935 * @arg @ref LL_ADC_CHANNEL_2
1936 * @arg @ref LL_ADC_CHANNEL_3
1937 * @arg @ref LL_ADC_CHANNEL_4
1938 * @arg @ref LL_ADC_CHANNEL_5
1939 * @arg @ref LL_ADC_CHANNEL_6
1940 * @arg @ref LL_ADC_CHANNEL_7
1941 * @arg @ref LL_ADC_CHANNEL_8
1942 * @arg @ref LL_ADC_CHANNEL_9
1943 * @arg @ref LL_ADC_CHANNEL_10
1944 * @arg @ref LL_ADC_CHANNEL_11
1945 * @arg @ref LL_ADC_CHANNEL_12
1946 * @arg @ref LL_ADC_CHANNEL_13
1947 * @arg @ref LL_ADC_CHANNEL_14
1948 * @arg @ref LL_ADC_CHANNEL_15
1949 * @arg @ref LL_ADC_CHANNEL_16
1950 * @arg @ref LL_ADC_CHANNEL_17
1951 * @arg @ref LL_ADC_CHANNEL_18
1952 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1953 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1954 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1955 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1956 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1957 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1958 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1959 *
1960 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1961 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1962 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1963 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1964 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1965 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
1966 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
1967 * comparison with internal channel parameter to be done
1968 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1969 * @param __GROUP__ This parameter can be one of the following values:
1970 * @arg @ref LL_ADC_GROUP_REGULAR
1971 * @arg @ref LL_ADC_GROUP_INJECTED
1972 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1973 * @retval Returned value can be one of the following values:
1974 * @arg @ref LL_ADC_AWD_DISABLE
1975 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1976 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1977 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1978 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1979 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1980 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1981 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1982 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1983 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1984 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1985 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1986 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1987 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1988 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1989 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1990 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1991 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1992 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1993 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1994 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1995 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1996 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1997 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1998 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1999 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2000 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2001 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2002 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2003 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2004 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2005 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2006 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2007 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2008 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2009 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2010 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2011 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2012 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2013 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2014 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2015 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2016 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2017 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2018 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2019 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2020 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2021 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2022 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2023 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2024 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2025 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2026 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2027 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2028 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2029 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2030 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2031 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2032 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2033 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2034 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2035 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
2036 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
2037 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
2038 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2039 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2040 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2041 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2042 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2043 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2044 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
2045 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
2046 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
2047 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
2048 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
2049 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
2050 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
2051 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
2052 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
2053 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
2054 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
2055 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
2056 *
2057 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
2058 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
2059 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
2060 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
2061 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
2062 * (5) On STM32F3, ADC channel available only on all ADC instances, but
2063 * only one ADC instance is allowed to be connected to VrefInt at the same time.
2064 */
2065 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2066 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2067 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2068 : \
2069 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2070 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2071 : \
2072 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2073 )
2075 /**
2076 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2077 * or low in function of ADC resolution, when ADC resolution is
2078 * different of 12 bits.
2079 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2080 * or @ref LL_ADC_SetAnalogWDThresholds().
2081 * Example, with a ADC resolution of 8 bits, to set the value of
2082 * analog watchdog threshold high (on 8 bits):
2083 * LL_ADC_SetAnalogWDThresholds
2084 * (< ADCx param >,
2085 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2086 * );
2087 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2088 * @arg @ref LL_ADC_RESOLUTION_12B
2089 * @arg @ref LL_ADC_RESOLUTION_10B
2090 * @arg @ref LL_ADC_RESOLUTION_8B
2091 * @arg @ref LL_ADC_RESOLUTION_6B
2092 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2093 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2094 */
2095 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2096 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2098 /**
2099 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2100 * or low in function of ADC resolution, when ADC resolution is
2101 * different of 12 bits.
2102 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2103 * Example, with a ADC resolution of 8 bits, to get the value of
2104 * analog watchdog threshold high (on 8 bits):
2105 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2106 * (LL_ADC_RESOLUTION_8B,
2107 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2108 * );
2109 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2110 * @arg @ref LL_ADC_RESOLUTION_12B
2111 * @arg @ref LL_ADC_RESOLUTION_10B
2112 * @arg @ref LL_ADC_RESOLUTION_8B
2113 * @arg @ref LL_ADC_RESOLUTION_6B
2114 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2115 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2116 */
2117 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2118 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2120 /**
2121 * @brief Helper macro to get the ADC analog watchdog threshold high
2122 * or low from raw value containing both thresholds concatenated.
2123 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2124 * Example, to get analog watchdog threshold high from the register raw value:
2125 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2126 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2127 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2128 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2129 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2130 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2131 */
2132 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2133 (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
2135 /**
2136 * @brief Helper macro to set the ADC calibration value with both single ended
2137 * and differential modes calibration factors concatenated.
2138 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2139 * Example, to set calibration factors single ended to 0x55
2140 * and differential ended to 0x2A:
2141 * LL_ADC_SetCalibrationFactor(
2142 * ADC1,
2143 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2144 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2145 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2146 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2147 */
2148 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2149 (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
2151 #if defined(ADC_MULTIMODE_SUPPORT)
2152 /**
2153 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2154 * or ADC slave from raw value with both ADC conversion data concatenated.
2155 * @note This macro is intended to be used when multimode transfer by DMA
2156 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2157 * In this case the transferred data need to processed with this macro
2158 * to separate the conversion data of ADC master and ADC slave.
2159 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2160 * @arg @ref LL_ADC_MULTI_MASTER
2161 * @arg @ref LL_ADC_MULTI_SLAVE
2162 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2163 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2164 */
2165 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2166 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2167 #endif
2169 /**
2170 * @brief Helper macro to select the ADC common instance
2171 * to which is belonging the selected ADC instance.
2172 * @note ADC common register instance can be used for:
2173 * - Set parameters common to several ADC instances
2174 * - Multimode (for devices with several ADC instances)
2175 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2176 * @param __ADCx__ ADC instance
2177 * @retval ADC common register instance
2178 */
2179 #if defined(ADC3) && defined(ADC4)
2180 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2181 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2182 ? ( \
2183 (ADC12_COMMON) \
2184 ) \
2185 : \
2186 ( \
2187 (ADC34_COMMON) \
2188 ) \
2189 )
2190 #elif defined(ADC1) && defined(ADC2)
2191 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2192 (ADC12_COMMON)
2193 #else
2194 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2195 (ADC1_COMMON)
2196 #endif
2198 /**
2199 * @brief Helper macro to check if all ADC instances sharing the same
2200 * ADC common instance are disabled.
2201 * @note This check is required by functions with setting conditioned to
2202 * ADC state:
2203 * All ADC instances of the ADC common group must be disabled.
2204 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2205 * @note On devices with only 1 ADC common instance, parameter of this macro
2206 * is useless and can be ignored (parameter kept for compatibility
2207 * with devices featuring several ADC common instances).
2208 * @param __ADCXY_COMMON__ ADC common instance
2209 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2210 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2211 * are disabled.
2212 * Value "1" if at least one ADC instance sharing the same ADC common instance
2213 * is enabled.
2214 */
2215 #if defined(ADC3) && defined(ADC4)
2216 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2217 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2218 ? ( \
2219 (LL_ADC_IsEnabled(ADC1) | \
2220 LL_ADC_IsEnabled(ADC2) ) \
2221 ) \
2222 : \
2223 ( \
2224 (LL_ADC_IsEnabled(ADC3) | \
2225 LL_ADC_IsEnabled(ADC4) ) \
2226 ) \
2227 )
2228 #elif defined(ADC1) && defined(ADC2)
2229 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2230 (LL_ADC_IsEnabled(ADC1) | \
2231 LL_ADC_IsEnabled(ADC2) )
2232 #else
2233 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2234 LL_ADC_IsEnabled(ADC1)
2235 #endif
2237 /**
2238 * @brief Helper macro to define the ADC conversion data full-scale digital
2239 * value corresponding to the selected ADC resolution.
2240 * @note ADC conversion data full-scale corresponds to voltage range
2241 * determined by analog voltage references Vref+ and Vref-
2242 * (refer to reference manual).
2243 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2244 * @arg @ref LL_ADC_RESOLUTION_12B
2245 * @arg @ref LL_ADC_RESOLUTION_10B
2246 * @arg @ref LL_ADC_RESOLUTION_8B
2247 * @arg @ref LL_ADC_RESOLUTION_6B
2248 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2249 */
2250 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2251 (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
2253 /**
2254 * @brief Helper macro to convert the ADC conversion data from
2255 * a resolution to another resolution.
2256 * @param __DATA__ ADC conversion data to be converted
2257 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
2258 * This parameter can be one of the following values:
2259 * @arg @ref LL_ADC_RESOLUTION_12B
2260 * @arg @ref LL_ADC_RESOLUTION_10B
2261 * @arg @ref LL_ADC_RESOLUTION_8B
2262 * @arg @ref LL_ADC_RESOLUTION_6B
2263 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2264 * This parameter can be one of the following values:
2265 * @arg @ref LL_ADC_RESOLUTION_12B
2266 * @arg @ref LL_ADC_RESOLUTION_10B
2267 * @arg @ref LL_ADC_RESOLUTION_8B
2268 * @arg @ref LL_ADC_RESOLUTION_6B
2269 * @retval ADC conversion data to the requested resolution
2270 */
2271 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2272 __ADC_RESOLUTION_CURRENT__,\
2273 __ADC_RESOLUTION_TARGET__) \
2274 (((__DATA__) \
2275 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \
2276 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \
2277 )
2279 /**
2280 * @brief Helper macro to calculate the voltage (unit: mVolt)
2281 * corresponding to a ADC conversion data (unit: digital value).
2282 * @note Analog reference voltage (Vref+) must be either known from
2283 * user board environment or can be calculated using ADC measurement
2284 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2285 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2286 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2287 * (unit: digital value).
2288 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2289 * @arg @ref LL_ADC_RESOLUTION_12B
2290 * @arg @ref LL_ADC_RESOLUTION_10B
2291 * @arg @ref LL_ADC_RESOLUTION_8B
2292 * @arg @ref LL_ADC_RESOLUTION_6B
2293 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2294 */
2295 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2296 __ADC_DATA__,\
2297 __ADC_RESOLUTION__) \
2298 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2299 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2300 )
2302 /**
2303 * @brief Helper macro to calculate analog reference voltage (Vref+)
2304 * (unit: mVolt) from ADC conversion data of internal voltage
2305 * reference VrefInt.
2306 * @note Computation is using VrefInt calibration value
2307 * stored in system memory for each device during production.
2308 * @note This voltage depends on user board environment: voltage level
2309 * connected to pin Vref+.
2310 * On devices with small package, the pin Vref+ is not present
2311 * and internally bonded to pin Vdda.
2312 * @note On this STM32 serie, calibration data of internal voltage reference
2313 * VrefInt corresponds to a resolution of 12 bits,
2314 * this is the recommended ADC resolution to convert voltage of
2315 * internal voltage reference VrefInt.
2316 * Otherwise, this macro performs the processing to scale
2317 * ADC conversion data to 12 bits.
2318 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2319 * of internal voltage reference VrefInt (unit: digital value).
2320 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2321 * @arg @ref LL_ADC_RESOLUTION_12B
2322 * @arg @ref LL_ADC_RESOLUTION_10B
2323 * @arg @ref LL_ADC_RESOLUTION_8B
2324 * @arg @ref LL_ADC_RESOLUTION_6B
2325 * @retval Analog reference voltage (unit: mV)
2326 */
2327 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2328 __ADC_RESOLUTION__) \
2329 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2330 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2331 (__ADC_RESOLUTION__), \
2332 LL_ADC_RESOLUTION_12B) \
2333 )
2335 /**
2336 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2337 * from ADC conversion data of internal temperature sensor.
2338 * @note Computation is using temperature sensor calibration values
2339 * stored in system memory for each device during production.
2340 * @note Calculation formula:
2341 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2342 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2343 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2344 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2345 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2346 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2347 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2348 * TEMP_DEGC_CAL1 (calibrated in factory)
2349 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2350 * TEMP_DEGC_CAL2 (calibrated in factory)
2351 * Caution: Calculation relevancy under reserve that calibration
2352 * parameters are correct (address and data).
2353 * To calculate temperature using temperature sensor
2354 * datasheet typical values (generic values less, therefore
2355 * less accurate than calibrated values),
2356 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2357 * @note As calculation input, the analog reference voltage (Vref+) must be
2358 * defined as it impacts the ADC LSB equivalent voltage.
2359 * @note Analog reference voltage (Vref+) must be either known from
2360 * user board environment or can be calculated using ADC measurement
2361 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2362 * @note On this STM32 serie, calibration data of temperature sensor
2363 * corresponds to a resolution of 12 bits,
2364 * this is the recommended ADC resolution to convert voltage of
2365 * temperature sensor.
2366 * Otherwise, this macro performs the processing to scale
2367 * ADC conversion data to 12 bits.
2368 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2369 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2370 * temperature sensor (unit: digital value).
2371 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2372 * sensor voltage has been measured.
2373 * This parameter can be one of the following values:
2374 * @arg @ref LL_ADC_RESOLUTION_12B
2375 * @arg @ref LL_ADC_RESOLUTION_10B
2376 * @arg @ref LL_ADC_RESOLUTION_8B
2377 * @arg @ref LL_ADC_RESOLUTION_6B
2378 * @retval Temperature (unit: degree Celsius)
2379 */
2380 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2381 __TEMPSENSOR_ADC_DATA__,\
2382 __ADC_RESOLUTION__) \
2383 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2384 (__ADC_RESOLUTION__), \
2385 LL_ADC_RESOLUTION_12B) \
2386 * (__VREFANALOG_VOLTAGE__)) \
2387 / TEMPSENSOR_CAL_VREFANALOG) \
2388 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2389 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2390 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2391 ) + TEMPSENSOR_CAL1_TEMP \
2392 )
2394 /**
2395 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2396 * from ADC conversion data of internal temperature sensor.
2397 * @note Computation is using temperature sensor typical values
2398 * (refer to device datasheet).
2399 * @note Calculation formula:
2400 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2401 * / Avg_Slope + CALx_TEMP
2402 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2403 * (unit: digital value)
2404 * Avg_Slope = temperature sensor slope
2405 * (unit: uV/Degree Celsius)
2406 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2407 * temperature CALx_TEMP (unit: mV)
2408 * Caution: Calculation relevancy under reserve the temperature sensor
2409 * of the current device has characteristics in line with
2410 * datasheet typical values.
2411 * If temperature sensor calibration values are available on
2412 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2413 * temperature calculation will be more accurate using
2414 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2415 * @note As calculation input, the analog reference voltage (Vref+) must be
2416 * defined as it impacts the ADC LSB equivalent voltage.
2417 * @note Analog reference voltage (Vref+) must be either known from
2418 * user board environment or can be calculated using ADC measurement
2419 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2420 * @note ADC measurement data must correspond to a resolution of 12bits
2421 * (full scale digital value 4095). If not the case, the data must be
2422 * preliminarily rescaled to an equivalent resolution of 12 bits.
2423 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2424 * On STM32F3, refer to device datasheet parameter "Avg_Slope".
2425 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2426 * On STM32F3, refer to device datasheet parameter "V25" (corresponding to TS_CAL1).
2427 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2428 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2429 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2430 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2431 * This parameter can be one of the following values:
2432 * @arg @ref LL_ADC_RESOLUTION_12B
2433 * @arg @ref LL_ADC_RESOLUTION_10B
2434 * @arg @ref LL_ADC_RESOLUTION_8B
2435 * @arg @ref LL_ADC_RESOLUTION_6B
2436 * @retval Temperature (unit: degree Celsius)
2437 */
2438 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2439 __TEMPSENSOR_TYP_CALX_V__,\
2440 __TEMPSENSOR_CALX_TEMP__,\
2441 __VREFANALOG_VOLTAGE__,\
2442 __TEMPSENSOR_ADC_DATA__,\
2443 __ADC_RESOLUTION__) \
2444 ((( ( \
2445 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2446 * 1000) \
2447 - \
2448 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2449 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2450 * 1000) \
2451 ) \
2452 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
2453 ) + (__TEMPSENSOR_CALX_TEMP__) \
2454 )
2456 /**
2457 * @}
2458 */
2460 /**
2461 * @}
2462 */
2465 /* Exported functions --------------------------------------------------------*/
2466 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2467 * @{
2468 */
2470 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2471 * @{
2472 */
2473 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2474 /* configuration of ADC instance, groups and multimode (if available): */
2475 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2477 /**
2478 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2479 * ADC register address from ADC instance and a list of ADC registers
2480 * intended to be used (most commonly) with DMA transfer.
2481 * @note These ADC registers are data registers:
2482 * when ADC conversion data is available in ADC data registers,
2483 * ADC generates a DMA transfer request.
2484 * @note This macro is intended to be used with LL DMA driver, refer to
2485 * function "LL_DMA_ConfigAddresses()".
2486 * Example:
2487 * LL_DMA_ConfigAddresses(DMA1,
2488 * LL_DMA_CHANNEL_1,
2489 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2490 * (uint32_t)&< array or variable >,
2491 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2492 * @note For devices with several ADC: in multimode, some devices
2493 * use a different data register outside of ADC instance scope
2494 * (common data register). This macro manages this register difference,
2495 * only ADC instance has to be set as parameter.
2496 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2497 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2498 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2499 * @param ADCx ADC instance
2500 * @param Register This parameter can be one of the following values:
2501 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2502 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2503 *
2504 * (1) Available on devices with several ADC instances.
2505 * @retval ADC register address
2506 */
2507 #if defined(ADC_MULTIMODE_SUPPORT)
2509 {
2513 {
2514 /* Retrieve address of register DR */
2516 }
2518 {
2519 /* Retrieve address of register CDR */
2521 }
2524 }
2525 #else
2527 {
2528 /* Retrieve address of register DR */
2530 }
2531 #endif
2533 /**
2534 * @}
2535 */
2537 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2538 * @{
2539 */
2541 /**
2542 * @brief Set parameter common to several ADC: Clock source and prescaler.
2543 * @note On this STM32 serie, if ADC group injected is used, some
2544 * clock ratio constraints between ADC clock and AHB clock
2545 * must be respected.
2546 * Refer to reference manual.
2547 * @note On this STM32 serie, setting of this feature is conditioned to
2548 * ADC state:
2549 * All ADC instances of the ADC common group must be disabled.
2550 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2551 * ADC instance or by using helper macro helper macro
2552 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2553 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2554 * CCR PRESC LL_ADC_SetCommonClock
2555 * @param ADCxy_COMMON ADC common instance
2556 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2557 * @param CommonClock This parameter can be one of the following values:
2558 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2559 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2560 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2561 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2562 * @retval None
2563 */
2564 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2565 {
2567 }
2569 /**
2570 * @brief Get parameter common to several ADC: Clock source and prescaler.
2571 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2572 * CCR PRESC LL_ADC_GetCommonClock
2573 * @param ADCxy_COMMON ADC common instance
2574 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2575 * @retval Returned value can be one of the following values:
2576 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2577 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2578 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2579 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2580 */
2582 {
2584 }
2586 /**
2587 * @brief Set parameter common to several ADC: measurement path to internal
2588 * channels (VrefInt, temperature sensor, ...).
2589 * @note One or several values can be selected.
2590 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2591 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2592 * @note Stabilization time of measurement path to internal channel:
2593 * After enabling internal paths, before starting ADC conversion,
2594 * a delay is required for internal voltage reference and
2595 * temperature sensor stabilization time.
2596 * Refer to device datasheet.
2597 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2598 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2599 * @note ADC internal channel sampling time constraint:
2600 * For ADC conversion of internal channels,
2601 * a sampling time minimum value is required.
2602 * Refer to device datasheet.
2603 * @note On this STM32 serie, setting of this feature is conditioned to
2604 * ADC state:
2605 * All ADC instances of the ADC common group must be disabled.
2606 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2607 * ADC instance or by using helper macro helper macro
2608 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2609 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2610 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2611 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2612 * @param ADCxy_COMMON ADC common instance
2613 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2614 * @param PathInternal This parameter can be a combination of the following values:
2615 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2616 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2617 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2618 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2619 * @retval None
2620 */
2621 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2622 {
2624 }
2626 /**
2627 * @brief Get parameter common to several ADC: measurement path to internal
2628 * channels (VrefInt, temperature sensor, ...).
2629 * @note One or several values can be selected.
2630 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2631 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2632 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2633 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2634 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2635 * @param ADCxy_COMMON ADC common instance
2636 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2637 * @retval Returned value can be a combination of the following values:
2638 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2639 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2640 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2641 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2642 */
2644 {
2645 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2646 }
2648 /**
2649 * @}
2650 */
2652 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2653 * @{
2654 */
2656 /**
2657 * @brief Set ADC calibration factor in the mode single-ended
2658 * or differential (for devices with differential mode available).
2659 * @note This function is intended to set calibration parameters
2660 * without having to perform a new calibration using
2661 * @ref LL_ADC_StartCalibration().
2662 * @note For devices with differential mode available:
2663 * Calibration of offset is specific to each of
2664 * single-ended and differential modes
2665 * (calibration factor must be specified for each of these
2666 * differential modes, if used afterwards and if the application
2667 * requires their calibration).
2668 * @note In case of setting calibration factors of both modes single ended
2669 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2670 * both calibration factors must be concatenated.
2671 * To perform this processing, use helper macro
2672 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2673 * @note On this STM32 serie, setting of this feature is conditioned to
2674 * ADC state:
2675 * ADC must be enabled, without calibration on going, without conversion
2676 * on going on group regular.
2677 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2678 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2679 * @param ADCx ADC instance
2680 * @param SingleDiff This parameter can be one of the following values:
2681 * @arg @ref LL_ADC_SINGLE_ENDED
2682 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2683 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2684 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2685 * @retval None
2686 */
2687 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2688 {
2692 }
2694 /**
2695 * @brief Get ADC calibration factor in the mode single-ended
2696 * or differential (for devices with differential mode available).
2697 * @note Calibration factors are set by hardware after performing
2698 * a calibration run using function @ref LL_ADC_StartCalibration().
2699 * @note For devices with differential mode available:
2700 * Calibration of offset is specific to each of
2701 * single-ended and differential modes
2702 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2703 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2704 * @param ADCx ADC instance
2705 * @param SingleDiff This parameter can be one of the following values:
2706 * @arg @ref LL_ADC_SINGLE_ENDED
2707 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2708 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2709 */
2711 {
2712 /* Retrieve bits with position in register depending on parameter */
2713 /* "SingleDiff". */
2714 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2715 /* containing other bits reserved for other purpose. */
2716 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
2717 }
2719 /**
2720 * @brief Set ADC resolution.
2721 * Refer to reference manual for alignments formats
2722 * dependencies to ADC resolutions.
2723 * @note On this STM32 serie, setting of this feature is conditioned to
2724 * ADC state:
2725 * ADC must be disabled or enabled without conversion on going
2726 * on either groups regular or injected.
2727 * @rmtoll CFGR RES LL_ADC_SetResolution
2728 * @param ADCx ADC instance
2729 * @param Resolution This parameter can be one of the following values:
2730 * @arg @ref LL_ADC_RESOLUTION_12B
2731 * @arg @ref LL_ADC_RESOLUTION_10B
2732 * @arg @ref LL_ADC_RESOLUTION_8B
2733 * @arg @ref LL_ADC_RESOLUTION_6B
2734 * @retval None
2735 */
2737 {
2739 }
2741 /**
2742 * @brief Get ADC resolution.
2743 * Refer to reference manual for alignments formats
2744 * dependencies to ADC resolutions.
2745 * @rmtoll CFGR RES LL_ADC_GetResolution
2746 * @param ADCx ADC instance
2747 * @retval Returned value can be one of the following values:
2748 * @arg @ref LL_ADC_RESOLUTION_12B
2749 * @arg @ref LL_ADC_RESOLUTION_10B
2750 * @arg @ref LL_ADC_RESOLUTION_8B
2751 * @arg @ref LL_ADC_RESOLUTION_6B
2752 */
2754 {
2756 }
2758 /**
2759 * @brief Set ADC conversion data alignment.
2760 * @note Refer to reference manual for alignments formats
2761 * dependencies to ADC resolutions.
2762 * @note On this STM32 serie, setting of this feature is conditioned to
2763 * ADC state:
2764 * ADC must be disabled or enabled without conversion on going
2765 * on either groups regular or injected.
2766 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2767 * @param ADCx ADC instance
2768 * @param DataAlignment This parameter can be one of the following values:
2769 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2770 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2771 * @retval None
2772 */
2774 {
2776 }
2778 /**
2779 * @brief Get ADC conversion data alignment.
2780 * @note Refer to reference manual for alignments formats
2781 * dependencies to ADC resolutions.
2782 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2783 * @param ADCx ADC instance
2784 * @retval Returned value can be one of the following values:
2785 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2786 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2787 */
2789 {
2791 }
2793 /**
2794 * @brief Set ADC low power mode.
2795 * @note Description of ADC low power modes:
2796 * - ADC low power mode "auto wait": Dynamic low power mode,
2797 * ADC conversions occurrences are limited to the minimum necessary
2798 * in order to reduce power consumption.
2799 * New ADC conversion starts only when the previous
2800 * unitary conversion data (for ADC group regular)
2801 * or previous sequence conversions data (for ADC group injected)
2802 * has been retrieved by user software.
2803 * In the meantime, ADC remains idle: does not performs any
2804 * other conversion.
2805 * This mode allows to automatically adapt the ADC conversions
2806 * triggers to the speed of the software that reads the data.
2807 * Moreover, this avoids risk of overrun for low frequency
2808 * applications.
2809 * How to use this low power mode:
2810 * - Do not use with interruption or DMA since these modes
2811 * have to clear immediately the EOC flag to free the
2812 * IRQ vector sequencer.
2813 * - Do use with polling: 1. Start conversion,
2814 * 2. Later on, when conversion data is needed: poll for end of
2815 * conversion to ensure that conversion is completed and
2816 * retrieve ADC conversion data. This will trig another
2817 * ADC conversion start.
2818 * - ADC low power mode "auto power-off" (feature available on
2819 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2820 * the ADC automatically powers-off after a conversion and
2821 * automatically wakes up when a new conversion is triggered
2822 * (with startup time between trigger and start of sampling).
2823 * This feature can be combined with low power mode "auto wait".
2824 * @note With ADC low power mode "auto wait", the ADC conversion data read
2825 * is corresponding to previous ADC conversion start, independently
2826 * of delay during which ADC was idle.
2827 * Therefore, the ADC conversion data may be outdated: does not
2828 * correspond to the current voltage level on the selected
2829 * ADC channel.
2830 * @note On this STM32 serie, setting of this feature is conditioned to
2831 * ADC state:
2832 * ADC must be disabled or enabled without conversion on going
2833 * on either groups regular or injected.
2834 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2835 * @param ADCx ADC instance
2836 * @param LowPowerMode This parameter can be one of the following values:
2837 * @arg @ref LL_ADC_LP_MODE_NONE
2838 * @arg @ref LL_ADC_LP_AUTOWAIT
2839 * @retval None
2840 */
2842 {
2844 }
2846 /**
2847 * @brief Get ADC low power mode:
2848 * @note Description of ADC low power modes:
2849 * - ADC low power mode "auto wait": Dynamic low power mode,
2850 * ADC conversions occurrences are limited to the minimum necessary
2851 * in order to reduce power consumption.
2852 * New ADC conversion starts only when the previous
2853 * unitary conversion data (for ADC group regular)
2854 * or previous sequence conversions data (for ADC group injected)
2855 * has been retrieved by user software.
2856 * In the meantime, ADC remains idle: does not performs any
2857 * other conversion.
2858 * This mode allows to automatically adapt the ADC conversions
2859 * triggers to the speed of the software that reads the data.
2860 * Moreover, this avoids risk of overrun for low frequency
2861 * applications.
2862 * How to use this low power mode:
2863 * - Do not use with interruption or DMA since these modes
2864 * have to clear immediately the EOC flag to free the
2865 * IRQ vector sequencer.
2866 * - Do use with polling: 1. Start conversion,
2867 * 2. Later on, when conversion data is needed: poll for end of
2868 * conversion to ensure that conversion is completed and
2869 * retrieve ADC conversion data. This will trig another
2870 * ADC conversion start.
2871 * - ADC low power mode "auto power-off" (feature available on
2872 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2873 * the ADC automatically powers-off after a conversion and
2874 * automatically wakes up when a new conversion is triggered
2875 * (with startup time between trigger and start of sampling).
2876 * This feature can be combined with low power mode "auto wait".
2877 * @note With ADC low power mode "auto wait", the ADC conversion data read
2878 * is corresponding to previous ADC conversion start, independently
2879 * of delay during which ADC was idle.
2880 * Therefore, the ADC conversion data may be outdated: does not
2881 * correspond to the current voltage level on the selected
2882 * ADC channel.
2883 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2884 * @param ADCx ADC instance
2885 * @retval Returned value can be one of the following values:
2886 * @arg @ref LL_ADC_LP_MODE_NONE
2887 * @arg @ref LL_ADC_LP_AUTOWAIT
2888 */
2890 {
2892 }
2894 /**
2895 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2896 * @note This function set the 2 items of offset configuration:
2897 * - ADC channel to which the offset programmed will be applied
2898 * (independently of channel mapped on ADC group regular
2899 * or group injected)
2900 * - Offset level (offset to be subtracted from the raw
2901 * converted data).
2902 * @note Caution: Offset format is dependent to ADC resolution:
2903 * offset has to be left-aligned on bit 11, the LSB (right bits)
2904 * are set to 0.
2905 * @note This function enables the offset, by default. It can be forced
2906 * to disable state using function LL_ADC_SetOffsetState().
2907 * @note If a channel is mapped on several offsets numbers, only the offset
2908 * with the lowest value is considered for the subtraction.
2909 * @note On this STM32 serie, setting of this feature is conditioned to
2910 * ADC state:
2911 * ADC must be disabled or enabled without conversion on going
2912 * on either groups regular or injected.
2913 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2914 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2915 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2916 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2917 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2918 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2919 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2920 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2921 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2922 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2923 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2924 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2925 * @param ADCx ADC instance
2926 * @param Offsety This parameter can be one of the following values:
2927 * @arg @ref LL_ADC_OFFSET_1
2928 * @arg @ref LL_ADC_OFFSET_2
2929 * @arg @ref LL_ADC_OFFSET_3
2930 * @arg @ref LL_ADC_OFFSET_4
2931 * @param Channel This parameter can be one of the following values:
2932 * @arg @ref LL_ADC_CHANNEL_0
2933 * @arg @ref LL_ADC_CHANNEL_1
2934 * @arg @ref LL_ADC_CHANNEL_2
2935 * @arg @ref LL_ADC_CHANNEL_3
2936 * @arg @ref LL_ADC_CHANNEL_4
2937 * @arg @ref LL_ADC_CHANNEL_5
2938 * @arg @ref LL_ADC_CHANNEL_6
2939 * @arg @ref LL_ADC_CHANNEL_7
2940 * @arg @ref LL_ADC_CHANNEL_8
2941 * @arg @ref LL_ADC_CHANNEL_9
2942 * @arg @ref LL_ADC_CHANNEL_10
2943 * @arg @ref LL_ADC_CHANNEL_11
2944 * @arg @ref LL_ADC_CHANNEL_12
2945 * @arg @ref LL_ADC_CHANNEL_13
2946 * @arg @ref LL_ADC_CHANNEL_14
2947 * @arg @ref LL_ADC_CHANNEL_15
2948 * @arg @ref LL_ADC_CHANNEL_16
2949 * @arg @ref LL_ADC_CHANNEL_17
2950 * @arg @ref LL_ADC_CHANNEL_18
2951 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
2952 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2953 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2954 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2955 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2956 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
2957 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
2958 *
2959 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
2960 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
2961 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
2962 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
2963 * (5) On STM32F3, ADC channel available only on all ADC instances, but
2964 * only one ADC instance is allowed to be connected to VrefInt at the same time.
2965 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2966 * @retval None
2967 */
2968 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2969 {
2975 }
2977 /**
2978 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2979 * Channel to which the offset programmed will be applied
2980 * (independently of channel mapped on ADC group regular
2981 * or group injected)
2982 * @note Usage of the returned channel number:
2983 * - To reinject this channel into another function LL_ADC_xxx:
2984 * the returned channel number is only partly formatted on definition
2985 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2986 * with parts of literals LL_ADC_CHANNEL_x or using
2987 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2988 * Then the selected literal LL_ADC_CHANNEL_x can be used
2989 * as parameter for another function.
2990 * - To get the channel number in decimal format:
2991 * process the returned value with the helper macro
2992 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2993 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2994 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2995 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2996 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2997 * @param ADCx ADC instance
2998 * @param Offsety This parameter can be one of the following values:
2999 * @arg @ref LL_ADC_OFFSET_1
3000 * @arg @ref LL_ADC_OFFSET_2
3001 * @arg @ref LL_ADC_OFFSET_3
3002 * @arg @ref LL_ADC_OFFSET_4
3003 * @retval Returned value can be one of the following values:
3004 * @arg @ref LL_ADC_CHANNEL_0
3005 * @arg @ref LL_ADC_CHANNEL_1
3006 * @arg @ref LL_ADC_CHANNEL_2
3007 * @arg @ref LL_ADC_CHANNEL_3
3008 * @arg @ref LL_ADC_CHANNEL_4
3009 * @arg @ref LL_ADC_CHANNEL_5
3010 * @arg @ref LL_ADC_CHANNEL_6
3011 * @arg @ref LL_ADC_CHANNEL_7
3012 * @arg @ref LL_ADC_CHANNEL_8
3013 * @arg @ref LL_ADC_CHANNEL_9
3014 * @arg @ref LL_ADC_CHANNEL_10
3015 * @arg @ref LL_ADC_CHANNEL_11
3016 * @arg @ref LL_ADC_CHANNEL_12
3017 * @arg @ref LL_ADC_CHANNEL_13
3018 * @arg @ref LL_ADC_CHANNEL_14
3019 * @arg @ref LL_ADC_CHANNEL_15
3020 * @arg @ref LL_ADC_CHANNEL_16
3021 * @arg @ref LL_ADC_CHANNEL_17
3022 * @arg @ref LL_ADC_CHANNEL_18
3023 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3024 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3025 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3026 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3027 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3028 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3029 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3030 *
3031 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3032 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3033 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3034 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3035 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3036 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
3037 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
3038 * comparison with internal channel parameter to be done
3039 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3040 */
3042 {
3046 }
3048 /**
3049 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3050 * Offset level (offset to be subtracted from the raw
3051 * converted data).
3052 * @note Caution: Offset format is dependent to ADC resolution:
3053 * offset has to be left-aligned on bit 11, the LSB (right bits)
3054 * are set to 0.
3055 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3056 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3057 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3058 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3059 * @param ADCx ADC instance
3060 * @param Offsety This parameter can be one of the following values:
3061 * @arg @ref LL_ADC_OFFSET_1
3062 * @arg @ref LL_ADC_OFFSET_2
3063 * @arg @ref LL_ADC_OFFSET_3
3064 * @arg @ref LL_ADC_OFFSET_4
3065 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3066 */
3068 {
3072 }
3074 /**
3075 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3076 * force offset state disable or enable
3077 * without modifying offset channel or offset value.
3078 * @note This function should be needed only in case of offset to be
3079 * enabled-disabled dynamically, and should not be needed in other cases:
3080 * function LL_ADC_SetOffset() automatically enables the offset.
3081 * @note On this STM32 serie, setting of this feature is conditioned to
3082 * ADC state:
3083 * ADC must be disabled or enabled without conversion on going
3084 * on either groups regular or injected.
3085 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3086 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3087 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3088 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3089 * @param ADCx ADC instance
3090 * @param Offsety This parameter can be one of the following values:
3091 * @arg @ref LL_ADC_OFFSET_1
3092 * @arg @ref LL_ADC_OFFSET_2
3093 * @arg @ref LL_ADC_OFFSET_3
3094 * @arg @ref LL_ADC_OFFSET_4
3095 * @param OffsetState This parameter can be one of the following values:
3096 * @arg @ref LL_ADC_OFFSET_DISABLE
3097 * @arg @ref LL_ADC_OFFSET_ENABLE
3098 * @retval None
3099 */
3100 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3101 {
3106 ADC_OFR1_OFFSET1_EN,
3107 OffsetState);
3108 }
3110 /**
3111 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3112 * offset state disabled or enabled.
3113 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3114 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3115 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3116 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3117 * @param ADCx ADC instance
3118 * @param Offsety This parameter can be one of the following values:
3119 * @arg @ref LL_ADC_OFFSET_1
3120 * @arg @ref LL_ADC_OFFSET_2
3121 * @arg @ref LL_ADC_OFFSET_3
3122 * @arg @ref LL_ADC_OFFSET_4
3123 * @retval Returned value can be one of the following values:
3124 * @arg @ref LL_ADC_OFFSET_DISABLE
3125 * @arg @ref LL_ADC_OFFSET_ENABLE
3126 */
3128 {
3132 }
3134 /**
3135 * @}
3136 */
3138 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3139 * @{
3140 */
3142 /**
3143 * @brief Set ADC group regular conversion trigger source:
3144 * internal (SW start) or from external IP (timer event,
3145 * external interrupt line).
3146 * @note On this STM32 serie, setting trigger source to external trigger
3147 * also set trigger polarity to rising edge
3148 * (default setting for compatibility with some ADC on other
3149 * STM32 families having this setting set by HW default value).
3150 * In case of need to modify trigger edge, use
3151 * function @ref LL_ADC_REG_SetTriggerEdge().
3152 * @note Availability of parameters of trigger sources from timer
3153 * depends on timers availability on the selected device.
3154 * @note On this STM32 serie, setting of this feature is conditioned to
3155 * ADC state:
3156 * ADC must be disabled or enabled without conversion on going
3157 * on group regular.
3158 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3159 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3160 * @param ADCx ADC instance
3161 * @param TriggerSource This parameter can be one of the following values:
3162 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3163 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3164 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3165 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
3166 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
3167 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
3168 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
3169 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3170 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
3171 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3172 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3173 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
3174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
3175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
3176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
3177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
3178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
3179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
3180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
3182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
3183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
3184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
3185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
3186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
3187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3188 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
3189 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
3190 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3191 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3192 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3193 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
3194 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3195 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
3196 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
3197 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
3198 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
3199 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
3200 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
3201 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
3202 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
3203 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
3204 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
3205 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
3206 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
3207 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
3208 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
3209 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
3211 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3212 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3213 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3214 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3215 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3216 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3217 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3218 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3219 * @retval None
3220 */
3222 {
3224 }
3226 /**
3227 * @brief Get ADC group regular conversion trigger source:
3228 * internal (SW start) or from external IP (timer event,
3229 * external interrupt line).
3230 * @note To determine whether group regular trigger source is
3231 * internal (SW start) or external, without detail
3232 * of which peripheral is selected as external trigger,
3233 * (equivalent to
3234 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3235 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3236 * @note Availability of parameters of trigger sources from timer
3237 * depends on timers availability on the selected device.
3238 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3239 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3240 * @param ADCx ADC instance
3241 * @retval Returned value can be one of the following values:
3242 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3243 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3244 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3245 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
3246 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
3247 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
3248 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
3249 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3250 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
3251 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3252 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3253 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
3254 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
3255 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
3256 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
3257 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
3258 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
3259 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
3260 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3261 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
3262 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
3263 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
3264 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
3265 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
3266 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
3267 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3268 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
3269 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
3270 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3271 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3272 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3273 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
3274 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3275 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
3276 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
3277 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
3278 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
3279 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
3280 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
3281 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
3282 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
3283 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
3284 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
3285 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
3286 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
3287 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
3288 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
3289 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
3291 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3292 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3293 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3294 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3295 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3296 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3297 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3298 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3299 */
3301 {
3304 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3305 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3306 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
3308 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3309 /* to match with triggers literals definition. */
3313 );
3314 }
3316 /**
3317 * @brief Get ADC group regular conversion trigger source internal (SW start)
3318 or external.
3319 * @note In case of group regular trigger source set to external trigger,
3320 * to determine which peripheral is selected as external trigger,
3321 * use function @ref LL_ADC_REG_GetTriggerSource().
3322 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3323 * @param ADCx ADC instance
3324 * @retval Value "0" if trigger source external trigger
3325 * Value "1" if trigger source SW start.
3326 */
3328 {
3330 }
3332 /**
3333 * @brief Set ADC group regular conversion trigger polarity.
3334 * @note Applicable only for trigger source set to external trigger.
3335 * @note On this STM32 serie, setting of this feature is conditioned to
3336 * ADC state:
3337 * ADC must be disabled or enabled without conversion on going
3338 * on group regular.
3339 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3340 * @param ADCx ADC instance
3341 * @param ExternalTriggerEdge This parameter can be one of the following values:
3342 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3343 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3344 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3345 * @retval None
3346 */
3347 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3348 {
3350 }
3352 /**
3353 * @brief Get ADC group regular conversion trigger polarity.
3354 * @note Applicable only for trigger source set to external trigger.
3355 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3356 * @param ADCx ADC instance
3357 * @retval Returned value can be one of the following values:
3358 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3359 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3360 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3361 */
3363 {
3365 }
3368 /**
3369 * @brief Set ADC group regular sequencer length and scan direction.
3370 * @note Description of ADC group regular sequencer features:
3371 * - For devices with sequencer fully configurable
3372 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3373 * sequencer length and each rank affectation to a channel
3374 * are configurable.
3375 * This function performs configuration of:
3376 * - Sequence length: Number of ranks in the scan sequence.
3377 * - Sequence direction: Unless specified in parameters, sequencer
3378 * scan direction is forward (from rank 1 to rank n).
3379 * Sequencer ranks are selected using
3380 * function "LL_ADC_REG_SetSequencerRanks()".
3381 * - For devices with sequencer not fully configurable
3382 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3383 * sequencer length and each rank affectation to a channel
3384 * are defined by channel number.
3385 * This function performs configuration of:
3386 * - Sequence length: Number of ranks in the scan sequence is
3387 * defined by number of channels set in the sequence,
3388 * rank of each channel is fixed by channel HW number.
3389 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3390 * - Sequence direction: Unless specified in parameters, sequencer
3391 * scan direction is forward (from lowest channel number to
3392 * highest channel number).
3393 * Sequencer ranks are selected using
3394 * function "LL_ADC_REG_SetSequencerChannels()".
3395 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3396 * ADC conversion on only 1 channel.
3397 * @note On this STM32 serie, setting of this feature is conditioned to
3398 * ADC state:
3399 * ADC must be disabled or enabled without conversion on going
3400 * on group regular.
3401 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3402 * @param ADCx ADC instance
3403 * @param SequencerNbRanks This parameter can be one of the following values:
3404 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3405 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3406 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3407 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3408 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3409 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3410 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3411 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3412 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3413 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3414 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3415 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3416 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3417 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3418 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3419 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3420 * @retval None
3421 */
3422 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3423 {
3425 }
3427 /**
3428 * @brief Get ADC group regular sequencer length and scan direction.
3429 * @note Description of ADC group regular sequencer features:
3430 * - For devices with sequencer fully configurable
3431 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3432 * sequencer length and each rank affectation to a channel
3433 * are configurable.
3434 * This function retrieves:
3435 * - Sequence length: Number of ranks in the scan sequence.
3436 * - Sequence direction: Unless specified in parameters, sequencer
3437 * scan direction is forward (from rank 1 to rank n).
3438 * Sequencer ranks are selected using
3439 * function "LL_ADC_REG_SetSequencerRanks()".
3440 * - For devices with sequencer not fully configurable
3441 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3442 * sequencer length and each rank affectation to a channel
3443 * are defined by channel number.
3444 * This function retrieves:
3445 * - Sequence length: Number of ranks in the scan sequence is
3446 * defined by number of channels set in the sequence,
3447 * rank of each channel is fixed by channel HW number.
3448 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3449 * - Sequence direction: Unless specified in parameters, sequencer
3450 * scan direction is forward (from lowest channel number to
3451 * highest channel number).
3452 * Sequencer ranks are selected using
3453 * function "LL_ADC_REG_SetSequencerChannels()".
3454 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3455 * ADC conversion on only 1 channel.
3456 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3457 * @param ADCx ADC instance
3458 * @retval Returned value can be one of the following values:
3459 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3460 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3461 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3462 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3463 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3464 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3465 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3466 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3467 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3468 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3469 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3470 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3471 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3472 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3473 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3474 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3475 */
3477 {
3479 }
3481 /**
3482 * @brief Set ADC group regular sequencer discontinuous mode:
3483 * sequence subdivided and scan conversions interrupted every selected
3484 * number of ranks.
3485 * @note It is not possible to enable both ADC group regular
3486 * continuous mode and sequencer discontinuous mode.
3487 * @note It is not possible to enable both ADC auto-injected mode
3488 * and ADC group regular sequencer discontinuous mode.
3489 * @note On this STM32 serie, setting of this feature is conditioned to
3490 * ADC state:
3491 * ADC must be disabled or enabled without conversion on going
3492 * on group regular.
3493 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3494 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3495 * @param ADCx ADC instance
3496 * @param SeqDiscont This parameter can be one of the following values:
3497 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3498 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3499 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3500 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3501 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3502 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3503 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3504 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3505 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3506 * @retval None
3507 */
3509 {
3511 }
3513 /**
3514 * @brief Get ADC group regular sequencer discontinuous mode:
3515 * sequence subdivided and scan conversions interrupted every selected
3516 * number of ranks.
3517 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3518 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3519 * @param ADCx ADC instance
3520 * @retval Returned value can be one of the following values:
3521 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3522 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3523 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3524 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3525 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3526 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3527 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3528 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3529 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3530 */
3532 {
3534 }
3536 /**
3537 * @brief Set ADC group regular sequence: channel on the selected
3538 * scan sequence rank.
3539 * @note This function performs configuration of:
3540 * - Channels ordering into each rank of scan sequence:
3541 * whatever channel can be placed into whatever rank.
3542 * @note On this STM32 serie, ADC group regular sequencer is
3543 * fully configurable: sequencer length and each rank
3544 * affectation to a channel are configurable.
3545 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3546 * @note Depending on devices and packages, some channels may not be available.
3547 * Refer to device datasheet for channels availability.
3548 * @note On this STM32 serie, to measure internal channels (VrefInt,
3549 * TempSensor, ...), measurement paths to internal channels must be
3550 * enabled separately.
3551 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3552 * @note On this STM32 serie, setting of this feature is conditioned to
3553 * ADC state:
3554 * ADC must be disabled or enabled without conversion on going
3555 * on group regular.
3556 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3557 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3558 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3559 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3560 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3561 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3562 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3563 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3564 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3565 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3566 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3567 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3568 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3569 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3570 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3571 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3572 * @param ADCx ADC instance
3573 * @param Rank This parameter can be one of the following values:
3574 * @arg @ref LL_ADC_REG_RANK_1
3575 * @arg @ref LL_ADC_REG_RANK_2
3576 * @arg @ref LL_ADC_REG_RANK_3
3577 * @arg @ref LL_ADC_REG_RANK_4
3578 * @arg @ref LL_ADC_REG_RANK_5
3579 * @arg @ref LL_ADC_REG_RANK_6
3580 * @arg @ref LL_ADC_REG_RANK_7
3581 * @arg @ref LL_ADC_REG_RANK_8
3582 * @arg @ref LL_ADC_REG_RANK_9
3583 * @arg @ref LL_ADC_REG_RANK_10
3584 * @arg @ref LL_ADC_REG_RANK_11
3585 * @arg @ref LL_ADC_REG_RANK_12
3586 * @arg @ref LL_ADC_REG_RANK_13
3587 * @arg @ref LL_ADC_REG_RANK_14
3588 * @arg @ref LL_ADC_REG_RANK_15
3589 * @arg @ref LL_ADC_REG_RANK_16
3590 * @param Channel This parameter can be one of the following values:
3591 * @arg @ref LL_ADC_CHANNEL_0
3592 * @arg @ref LL_ADC_CHANNEL_1
3593 * @arg @ref LL_ADC_CHANNEL_2
3594 * @arg @ref LL_ADC_CHANNEL_3
3595 * @arg @ref LL_ADC_CHANNEL_4
3596 * @arg @ref LL_ADC_CHANNEL_5
3597 * @arg @ref LL_ADC_CHANNEL_6
3598 * @arg @ref LL_ADC_CHANNEL_7
3599 * @arg @ref LL_ADC_CHANNEL_8
3600 * @arg @ref LL_ADC_CHANNEL_9
3601 * @arg @ref LL_ADC_CHANNEL_10
3602 * @arg @ref LL_ADC_CHANNEL_11
3603 * @arg @ref LL_ADC_CHANNEL_12
3604 * @arg @ref LL_ADC_CHANNEL_13
3605 * @arg @ref LL_ADC_CHANNEL_14
3606 * @arg @ref LL_ADC_CHANNEL_15
3607 * @arg @ref LL_ADC_CHANNEL_16
3608 * @arg @ref LL_ADC_CHANNEL_17
3609 * @arg @ref LL_ADC_CHANNEL_18
3610 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3611 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3612 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3613 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3614 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3615 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3616 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3617 *
3618 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3619 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3620 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3621 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3622 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3623 * only one ADC instance is allowed to be connected to VrefInt at the same time.
3624 * @retval None
3625 */
3626 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3627 {
3628 /* Set bits with content of parameter "Channel" with bits position */
3629 /* in register and register position depending on parameter "Rank". */
3630 /* Parameters "Rank" and "Channel" are used with masks because containing */
3631 /* other bits reserved for other purpose. */
3632 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
3636 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
3637 }
3639 /**
3640 * @brief Get ADC group regular sequence: channel on the selected
3641 * scan sequence rank.
3642 * @note On this STM32 serie, ADC group regular sequencer is
3643 * fully configurable: sequencer length and each rank
3644 * affectation to a channel are configurable.
3645 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3646 * @note Depending on devices and packages, some channels may not be available.
3647 * Refer to device datasheet for channels availability.
3648 * @note Usage of the returned channel number:
3649 * - To reinject this channel into another function LL_ADC_xxx:
3650 * the returned channel number is only partly formatted on definition
3651 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3652 * with parts of literals LL_ADC_CHANNEL_x or using
3653 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3654 * Then the selected literal LL_ADC_CHANNEL_x can be used
3655 * as parameter for another function.
3656 * - To get the channel number in decimal format:
3657 * process the returned value with the helper macro
3658 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3659 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3660 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3661 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3662 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3663 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3664 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3665 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3666 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3667 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3668 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3669 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3670 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3671 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3672 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3673 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3674 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3675 * @param ADCx ADC instance
3676 * @param Rank This parameter can be one of the following values:
3677 * @arg @ref LL_ADC_REG_RANK_1
3678 * @arg @ref LL_ADC_REG_RANK_2
3679 * @arg @ref LL_ADC_REG_RANK_3
3680 * @arg @ref LL_ADC_REG_RANK_4
3681 * @arg @ref LL_ADC_REG_RANK_5
3682 * @arg @ref LL_ADC_REG_RANK_6
3683 * @arg @ref LL_ADC_REG_RANK_7
3684 * @arg @ref LL_ADC_REG_RANK_8
3685 * @arg @ref LL_ADC_REG_RANK_9
3686 * @arg @ref LL_ADC_REG_RANK_10
3687 * @arg @ref LL_ADC_REG_RANK_11
3688 * @arg @ref LL_ADC_REG_RANK_12
3689 * @arg @ref LL_ADC_REG_RANK_13
3690 * @arg @ref LL_ADC_REG_RANK_14
3691 * @arg @ref LL_ADC_REG_RANK_15
3692 * @arg @ref LL_ADC_REG_RANK_16
3693 * @retval Returned value can be one of the following values:
3694 * @arg @ref LL_ADC_CHANNEL_0
3695 * @arg @ref LL_ADC_CHANNEL_1
3696 * @arg @ref LL_ADC_CHANNEL_2
3697 * @arg @ref LL_ADC_CHANNEL_3
3698 * @arg @ref LL_ADC_CHANNEL_4
3699 * @arg @ref LL_ADC_CHANNEL_5
3700 * @arg @ref LL_ADC_CHANNEL_6
3701 * @arg @ref LL_ADC_CHANNEL_7
3702 * @arg @ref LL_ADC_CHANNEL_8
3703 * @arg @ref LL_ADC_CHANNEL_9
3704 * @arg @ref LL_ADC_CHANNEL_10
3705 * @arg @ref LL_ADC_CHANNEL_11
3706 * @arg @ref LL_ADC_CHANNEL_12
3707 * @arg @ref LL_ADC_CHANNEL_13
3708 * @arg @ref LL_ADC_CHANNEL_14
3709 * @arg @ref LL_ADC_CHANNEL_15
3710 * @arg @ref LL_ADC_CHANNEL_16
3711 * @arg @ref LL_ADC_CHANNEL_17
3712 * @arg @ref LL_ADC_CHANNEL_18
3713 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3714 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3715 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3716 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3717 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3718 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3719 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3720 *
3721 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3722 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3723 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3724 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3725 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3726 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
3727 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
3728 * comparison with internal channel parameter to be done
3729 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3730 */
3732 {
3733 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
3738 );
3739 }
3741 /**
3742 * @brief Set ADC continuous conversion mode on ADC group regular.
3743 * @note Description of ADC continuous conversion mode:
3744 * - single mode: one conversion per trigger
3745 * - continuous mode: after the first trigger, following
3746 * conversions launched successively automatically.
3747 * @note It is not possible to enable both ADC group regular
3748 * continuous mode and sequencer discontinuous mode.
3749 * @note On this STM32 serie, setting of this feature is conditioned to
3750 * ADC state:
3751 * ADC must be disabled or enabled without conversion on going
3752 * on group regular.
3753 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3754 * @param ADCx ADC instance
3755 * @param Continuous This parameter can be one of the following values:
3756 * @arg @ref LL_ADC_REG_CONV_SINGLE
3757 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3758 * @retval None
3759 */
3761 {
3763 }
3765 /**
3766 * @brief Get ADC continuous conversion mode on ADC group regular.
3767 * @note Description of ADC continuous conversion mode:
3768 * - single mode: one conversion per trigger
3769 * - continuous mode: after the first trigger, following
3770 * conversions launched successively automatically.
3771 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3772 * @param ADCx ADC instance
3773 * @retval Returned value can be one of the following values:
3774 * @arg @ref LL_ADC_REG_CONV_SINGLE
3775 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3776 */
3778 {
3780 }
3782 /**
3783 * @brief Set ADC group regular conversion data transfer: no transfer or
3784 * transfer by DMA, and DMA requests mode.
3785 * @note If transfer by DMA selected, specifies the DMA requests
3786 * mode:
3787 * - Limited mode (One shot mode): DMA transfer requests are stopped
3788 * when number of DMA data transfers (number of
3789 * ADC conversions) is reached.
3790 * This ADC mode is intended to be used with DMA mode non-circular.
3791 * - Unlimited mode: DMA transfer requests are unlimited,
3792 * whatever number of DMA data transfers (number of
3793 * ADC conversions).
3794 * This ADC mode is intended to be used with DMA mode circular.
3795 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3796 * mode non-circular:
3797 * when DMA transfers size will be reached, DMA will stop transfers of
3798 * ADC conversions data ADC will raise an overrun error
3799 * (overrun flag and interruption if enabled).
3800 * @note For devices with several ADC instances: ADC multimode DMA
3801 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
3802 * @note To configure DMA source address (peripheral address),
3803 * use function @ref LL_ADC_DMA_GetRegAddr().
3804 * @note On this STM32 serie, setting of this feature is conditioned to
3805 * ADC state:
3806 * ADC must be disabled or enabled without conversion on going
3807 * on either groups regular or injected.
3808 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
3809 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
3810 * @param ADCx ADC instance
3811 * @param DMATransfer This parameter can be one of the following values:
3812 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3813 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3814 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3815 * @retval None
3816 */
3818 {
3820 }
3822 /**
3823 * @brief Get ADC group regular conversion data transfer: no transfer or
3824 * transfer by DMA, and DMA requests mode.
3825 * @note If transfer by DMA selected, specifies the DMA requests
3826 * mode:
3827 * - Limited mode (One shot mode): DMA transfer requests are stopped
3828 * when number of DMA data transfers (number of
3829 * ADC conversions) is reached.
3830 * This ADC mode is intended to be used with DMA mode non-circular.
3831 * - Unlimited mode: DMA transfer requests are unlimited,
3832 * whatever number of DMA data transfers (number of
3833 * ADC conversions).
3834 * This ADC mode is intended to be used with DMA mode circular.
3835 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3836 * mode non-circular:
3837 * when DMA transfers size will be reached, DMA will stop transfers of
3838 * ADC conversions data ADC will raise an overrun error
3839 * (overrun flag and interruption if enabled).
3840 * @note For devices with several ADC instances: ADC multimode DMA
3841 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
3842 * @note To configure DMA source address (peripheral address),
3843 * use function @ref LL_ADC_DMA_GetRegAddr().
3844 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
3845 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
3846 * @param ADCx ADC instance
3847 * @retval Returned value can be one of the following values:
3848 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3849 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3850 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3851 */
3853 {
3855 }
3857 /**
3858 * @brief Set ADC group regular behavior in case of overrun:
3859 * data preserved or overwritten.
3860 * @note Compatibility with devices without feature overrun:
3861 * other devices without this feature have a behavior
3862 * equivalent to data overwritten.
3863 * The default setting of overrun is data preserved.
3864 * Therefore, for compatibility with all devices, parameter
3865 * overrun should be set to data overwritten.
3866 * @note On this STM32 serie, setting of this feature is conditioned to
3867 * ADC state:
3868 * ADC must be disabled or enabled without conversion on going
3869 * on group regular.
3870 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3871 * @param ADCx ADC instance
3872 * @param Overrun This parameter can be one of the following values:
3873 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3874 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3875 * @retval None
3876 */
3878 {
3880 }
3882 /**
3883 * @brief Get ADC group regular behavior in case of overrun:
3884 * data preserved or overwritten.
3885 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3886 * @param ADCx ADC instance
3887 * @retval Returned value can be one of the following values:
3888 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3889 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3890 */
3892 {
3894 }
3896 /**
3897 * @}
3898 */
3900 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3901 * @{
3902 */
3904 /**
3905 * @brief Set ADC group injected conversion trigger source:
3906 * internal (SW start) or from external IP (timer event,
3907 * external interrupt line).
3908 * @note On this STM32 serie, setting trigger source to external trigger
3909 * also set trigger polarity to rising edge
3910 * (default setting for compatibility with some ADC on other
3911 * STM32 families having this setting set by HW default value).
3912 * In case of need to modify trigger edge, use
3913 * function @ref LL_ADC_INJ_SetTriggerEdge().
3914 * @note Caution to ADC group injected contexts queue: On this STM32 serie,
3915 * using successively several times this function will appear has
3916 * having no effect.
3917 * This is due to ADC group injected contexts queue (this feature
3918 * cannot be disabled on this STM32 serie).
3919 * To set several features of ADC group injected, use
3920 * function @ref LL_ADC_INJ_ConfigQueueContext().
3921 * @note Availability of parameters of trigger sources from timer
3922 * depends on timers availability on the selected device.
3923 * @note On this STM32 serie, setting of this feature is conditioned to
3924 * ADC state:
3925 * ADC must not be disabled. Can be enabled with or without conversion
3926 * on going on either groups regular or injected.
3927 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3928 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3929 * @param ADCx ADC instance
3930 * @param TriggerSource This parameter can be one of the following values:
3931 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3932 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3933 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3934 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
3935 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3936 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
3937 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3938 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3939 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
3940 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
3941 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
3942 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
3943 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
3944 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
3945 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
3946 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3947 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
3948 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
3949 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
3950 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
3951 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
3952 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
3953 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
3954 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3955 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3956 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
3957 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
3958 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
3959 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
3960 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
3961 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3962 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
3963 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
3964 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
3965 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
3966 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
3967 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
3968 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
3969 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
3970 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
3971 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
3972 *
3973 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3974 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3975 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3976 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3977 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3978 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3979 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3980 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3981 * @retval None
3982 */
3984 {
3986 }
3988 /**
3989 * @brief Get ADC group injected conversion trigger source:
3990 * internal (SW start) or from external IP (timer event,
3991 * external interrupt line).
3992 * @note To determine whether group injected trigger source is
3993 * internal (SW start) or external, without detail
3994 * of which peripheral is selected as external trigger,
3995 * (equivalent to
3996 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3997 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3998 * @note Availability of parameters of trigger sources from timer
3999 * depends on timers availability on the selected device.
4000 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4001 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4002 * @param ADCx ADC instance
4003 * @retval Returned value can be one of the following values:
4004 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4005 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4006 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4007 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
4008 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4009 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
4010 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
4011 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
4012 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
4013 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
4014 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
4015 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
4016 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
4017 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
4018 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
4019 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
4020 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
4021 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
4022 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
4023 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
4024 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
4025 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
4026 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
4027 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
4028 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
4029 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
4030 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
4031 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
4032 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
4033 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
4034 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4035 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
4036 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
4037 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
4038 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
4039 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
4040 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
4041 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
4042 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
4043 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
4044 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
4045 *
4046 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
4047 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
4048 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
4049 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
4050 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
4051 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
4052 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
4053 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
4054 */
4056 {
4059 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4060 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4061 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
4063 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4064 /* to match with triggers literals definition. */
4068 );
4069 }
4071 /**
4072 * @brief Get ADC group injected conversion trigger source internal (SW start)
4073 or external
4074 * @note In case of group injected trigger source set to external trigger,
4075 * to determine which peripheral is selected as external trigger,
4076 * use function @ref LL_ADC_INJ_GetTriggerSource.
4077 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4078 * @param ADCx ADC instance
4079 * @retval Value "0" if trigger source external trigger
4080 * Value "1" if trigger source SW start.
4081 */
4083 {
4084 return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
4085 }
4087 /**
4088 * @brief Set ADC group injected conversion trigger polarity.
4089 * Applicable only for trigger source set to external trigger.
4090 * @note On this STM32 serie, setting of this feature is conditioned to
4091 * ADC state:
4092 * ADC must not be disabled. Can be enabled with or without conversion
4093 * on going on either groups regular or injected.
4094 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4095 * @param ADCx ADC instance
4096 * @param ExternalTriggerEdge This parameter can be one of the following values:
4097 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4098 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4099 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4100 * @retval None
4101 */
4102 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4103 {
4105 }
4107 /**
4108 * @brief Get ADC group injected conversion trigger polarity.
4109 * Applicable only for trigger source set to external trigger.
4110 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4111 * @param ADCx ADC instance
4112 * @retval Returned value can be one of the following values:
4113 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4114 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4115 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4116 */
4118 {
4120 }
4122 /**
4123 * @brief Set ADC group injected sequencer length and scan direction.
4124 * @note This function performs configuration of:
4125 * - Sequence length: Number of ranks in the scan sequence.
4126 * - Sequence direction: Unless specified in parameters, sequencer
4127 * scan direction is forward (from rank 1 to rank n).
4128 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4129 * ADC conversion on only 1 channel.
4130 * @note Caution to ADC group injected contexts queue: On this STM32 serie,
4131 * using successively several times this function will appear has
4132 * having no effect.
4133 * This is due to ADC group injected contexts queue (this feature
4134 * cannot be disabled on this STM32 serie).
4135 * To set several features of ADC group injected, use
4136 * function @ref LL_ADC_INJ_ConfigQueueContext().
4137 * @note On this STM32 serie, setting of this feature is conditioned to
4138 * ADC state:
4139 * ADC must not be disabled. Can be enabled with or without conversion
4140 * on going on either groups regular or injected.
4141 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4142 * @param ADCx ADC instance
4143 * @param SequencerNbRanks This parameter can be one of the following values:
4144 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4145 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4146 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4147 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4148 * @retval None
4149 */
4150 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4151 {
4153 }
4155 /**
4156 * @brief Get ADC group injected sequencer length and scan direction.
4157 * @note This function retrieves:
4158 * - Sequence length: Number of ranks in the scan sequence.
4159 * - Sequence direction: Unless specified in parameters, sequencer
4160 * scan direction is forward (from rank 1 to rank n).
4161 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4162 * ADC conversion on only 1 channel.
4163 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4164 * @param ADCx ADC instance
4165 * @retval Returned value can be one of the following values:
4166 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4167 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4168 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4169 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4170 */
4172 {
4174 }
4176 /**
4177 * @brief Set ADC group injected sequencer discontinuous mode:
4178 * sequence subdivided and scan conversions interrupted every selected
4179 * number of ranks.
4180 * @note It is not possible to enable both ADC group injected
4181 * auto-injected mode and sequencer discontinuous mode.
4182 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4183 * @param ADCx ADC instance
4184 * @param SeqDiscont This parameter can be one of the following values:
4185 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4186 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4187 * @retval None
4188 */
4190 {
4192 }
4194 /**
4195 * @brief Get ADC group injected sequencer discontinuous mode:
4196 * sequence subdivided and scan conversions interrupted every selected
4197 * number of ranks.
4198 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4199 * @param ADCx ADC instance
4200 * @retval Returned value can be one of the following values:
4201 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4202 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4203 */
4205 {
4207 }
4209 /**
4210 * @brief Set ADC group injected sequence: channel on the selected
4211 * sequence rank.
4212 * @note Depending on devices and packages, some channels may not be available.
4213 * Refer to device datasheet for channels availability.
4214 * @note On this STM32 serie, to measure internal channels (VrefInt,
4215 * TempSensor, ...), measurement paths to internal channels must be
4216 * enabled separately.
4217 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4218 * @note Caution to ADC group injected contexts queue: On this STM32 serie,
4219 * using successively several times this function will appear has
4220 * having no effect.
4221 * This is due to ADC group injected contexts queue (this feature
4222 * cannot be disabled on this STM32 serie).
4223 * To set several features of ADC group injected, use
4224 * function @ref LL_ADC_INJ_ConfigQueueContext().
4225 * @note On this STM32 serie, setting of this feature is conditioned to
4226 * ADC state:
4227 * ADC must not be disabled. Can be enabled with or without conversion
4228 * on going on either groups regular or injected.
4229 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4230 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4231 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4232 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4233 * @param ADCx ADC instance
4234 * @param Rank This parameter can be one of the following values:
4235 * @arg @ref LL_ADC_INJ_RANK_1
4236 * @arg @ref LL_ADC_INJ_RANK_2
4237 * @arg @ref LL_ADC_INJ_RANK_3
4238 * @arg @ref LL_ADC_INJ_RANK_4
4239 * @param Channel This parameter can be one of the following values:
4240 * @arg @ref LL_ADC_CHANNEL_0
4241 * @arg @ref LL_ADC_CHANNEL_1
4242 * @arg @ref LL_ADC_CHANNEL_2
4243 * @arg @ref LL_ADC_CHANNEL_3
4244 * @arg @ref LL_ADC_CHANNEL_4
4245 * @arg @ref LL_ADC_CHANNEL_5
4246 * @arg @ref LL_ADC_CHANNEL_6
4247 * @arg @ref LL_ADC_CHANNEL_7
4248 * @arg @ref LL_ADC_CHANNEL_8
4249 * @arg @ref LL_ADC_CHANNEL_9
4250 * @arg @ref LL_ADC_CHANNEL_10
4251 * @arg @ref LL_ADC_CHANNEL_11
4252 * @arg @ref LL_ADC_CHANNEL_12
4253 * @arg @ref LL_ADC_CHANNEL_13
4254 * @arg @ref LL_ADC_CHANNEL_14
4255 * @arg @ref LL_ADC_CHANNEL_15
4256 * @arg @ref LL_ADC_CHANNEL_16
4257 * @arg @ref LL_ADC_CHANNEL_17
4258 * @arg @ref LL_ADC_CHANNEL_18
4259 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4260 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4261 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4262 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4263 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4264 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4265 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4266 *
4267 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4268 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4269 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4270 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4271 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4272 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4273 * @retval None
4274 */
4275 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4276 {
4277 /* Set bits with content of parameter "Channel" with bits position */
4278 /* in register depending on parameter "Rank". */
4279 /* Parameters "Rank" and "Channel" are used with masks because containing */
4280 /* other bits reserved for other purpose. */
4282 ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
4283 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
4284 }
4286 /**
4287 * @brief Get ADC group injected sequence: channel on the selected
4288 * sequence rank.
4289 * @note Depending on devices and packages, some channels may not be available.
4290 * Refer to device datasheet for channels availability.
4291 * @note Usage of the returned channel number:
4292 * - To reinject this channel into another function LL_ADC_xxx:
4293 * the returned channel number is only partly formatted on definition
4294 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4295 * with parts of literals LL_ADC_CHANNEL_x or using
4296 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4297 * Then the selected literal LL_ADC_CHANNEL_x can be used
4298 * as parameter for another function.
4299 * - To get the channel number in decimal format:
4300 * process the returned value with the helper macro
4301 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4302 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4303 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4304 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4305 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4306 * @param ADCx ADC instance
4307 * @param Rank This parameter can be one of the following values:
4308 * @arg @ref LL_ADC_INJ_RANK_1
4309 * @arg @ref LL_ADC_INJ_RANK_2
4310 * @arg @ref LL_ADC_INJ_RANK_3
4311 * @arg @ref LL_ADC_INJ_RANK_4
4312 * @retval Returned value can be one of the following values:
4313 * @arg @ref LL_ADC_CHANNEL_0
4314 * @arg @ref LL_ADC_CHANNEL_1
4315 * @arg @ref LL_ADC_CHANNEL_2
4316 * @arg @ref LL_ADC_CHANNEL_3
4317 * @arg @ref LL_ADC_CHANNEL_4
4318 * @arg @ref LL_ADC_CHANNEL_5
4319 * @arg @ref LL_ADC_CHANNEL_6
4320 * @arg @ref LL_ADC_CHANNEL_7
4321 * @arg @ref LL_ADC_CHANNEL_8
4322 * @arg @ref LL_ADC_CHANNEL_9
4323 * @arg @ref LL_ADC_CHANNEL_10
4324 * @arg @ref LL_ADC_CHANNEL_11
4325 * @arg @ref LL_ADC_CHANNEL_12
4326 * @arg @ref LL_ADC_CHANNEL_13
4327 * @arg @ref LL_ADC_CHANNEL_14
4328 * @arg @ref LL_ADC_CHANNEL_15
4329 * @arg @ref LL_ADC_CHANNEL_16
4330 * @arg @ref LL_ADC_CHANNEL_17
4331 * @arg @ref LL_ADC_CHANNEL_18
4332 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4333 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4334 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4335 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4336 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4337 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4338 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4339 *
4340 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4341 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4342 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4343 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4344 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4345 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
4346 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
4347 * comparison with internal channel parameter to be done
4348 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4349 */
4351 {
4353 ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
4355 );
4356 }
4358 /**
4359 * @brief Set ADC group injected conversion trigger:
4360 * independent or from ADC group regular.
4361 * @note This mode can be used to extend number of data registers
4362 * updated after one ADC conversion trigger and with data
4363 * permanently kept (not erased by successive conversions of scan of
4364 * ADC sequencer ranks), up to 5 data registers:
4365 * 1 data register on ADC group regular, 4 data registers
4366 * on ADC group injected.
4367 * @note If ADC group injected injected trigger source is set to an
4368 * external trigger, this feature must be must be set to
4369 * independent trigger.
4370 * ADC group injected automatic trigger is compliant only with
4371 * group injected trigger source set to SW start, without any
4372 * further action on ADC group injected conversion start or stop:
4373 * in this case, ADC group injected is controlled only
4374 * from ADC group regular.
4375 * @note It is not possible to enable both ADC group injected
4376 * auto-injected mode and sequencer discontinuous mode.
4377 * @note On this STM32 serie, setting of this feature is conditioned to
4378 * ADC state:
4379 * ADC must be disabled or enabled without conversion on going
4380 * on either groups regular or injected.
4381 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4382 * @param ADCx ADC instance
4383 * @param TrigAuto This parameter can be one of the following values:
4384 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4385 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4386 * @retval None
4387 */
4389 {
4391 }
4393 /**
4394 * @brief Get ADC group injected conversion trigger:
4395 * independent or from ADC group regular.
4396 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4397 * @param ADCx ADC instance
4398 * @retval Returned value can be one of the following values:
4399 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4400 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4401 */
4403 {
4405 }
4407 /**
4408 * @brief Set ADC group injected contexts queue mode.
4409 * @note A context is a setting of group injected sequencer:
4410 * - group injected trigger
4411 * - sequencer length
4412 * - sequencer ranks
4413 * If contexts queue is disabled:
4414 * - only 1 sequence can be configured
4415 * and is active perpetually.
4416 * If contexts queue is enabled:
4417 * - up to 2 contexts can be queued
4418 * and are checked in and out as a FIFO stack (first-in, first-out).
4419 * - If a new context is set when queues is full, error is triggered
4420 * by interruption "Injected Queue Overflow".
4421 * - Two behaviors are possible when all contexts have been processed:
4422 * the contexts queue can maintain the last context active perpetually
4423 * or can be empty and injected group triggers are disabled.
4424 * - Triggers can be only external (not internal SW start)
4425 * - Caution: The sequence must be fully configured in one time
4426 * (one write of register JSQR makes a check-in of a new context
4427 * into the queue).
4428 * Therefore functions to set separately injected trigger and
4429 * sequencer channels cannot be used, register JSQR must be set
4430 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4431 * @note This parameter can be modified only when no conversion is on going
4432 * on either groups regular or injected.
4433 * @note A modification of the context mode (bit JQDIS) causes the contexts
4434 * queue to be flushed and the register JSQR is cleared.
4435 * @note On this STM32 serie, setting of this feature is conditioned to
4436 * ADC state:
4437 * ADC must be disabled or enabled without conversion on going
4438 * on either groups regular or injected.
4439 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode
4440 * @param ADCx ADC instance
4441 * @param QueueMode This parameter can be one of the following values:
4442 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4443 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4444 * @retval None
4445 */
4447 {
4449 }
4451 /**
4452 * @brief Get ADC group injected context queue mode.
4453 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode
4454 * @param ADCx ADC instance
4455 * @retval Returned value can be one of the following values:
4456 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4457 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4458 */
4460 {
4462 }
4464 /**
4465 * @brief Set one context on ADC group injected that will be checked in
4466 * contexts queue.
4467 * @note A context is a setting of group injected sequencer:
4468 * - group injected trigger
4469 * - sequencer length
4470 * - sequencer ranks
4471 * This function is intended to be used when contexts queue is enabled,
4472 * because the sequence must be fully configured in one time
4473 * (functions to set separately injected trigger and sequencer channels
4474 * cannot be used):
4475 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4476 * @note In the contexts queue, only the active context can be read.
4477 * The parameters of this function can be read using functions:
4478 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4479 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4480 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4481 * @note On this STM32 serie, to measure internal channels (VrefInt,
4482 * TempSensor, ...), measurement paths to internal channels must be
4483 * enabled separately.
4484 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4485 * @note On this STM32 serie, setting of this feature is conditioned to
4486 * ADC state:
4487 * ADC must not be disabled. Can be enabled with or without conversion
4488 * on going on either groups regular or injected.
4489 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4490 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4491 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4492 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4493 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4494 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4495 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4496 * @param ADCx ADC instance
4497 * @param TriggerSource This parameter can be one of the following values:
4498 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4499 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4500 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4501 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
4502 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4503 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
4504 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
4505 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
4506 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
4507 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
4508 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
4509 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
4510 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
4511 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
4512 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
4513 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
4514 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
4515 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
4516 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
4517 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
4518 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
4519 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
4520 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
4521 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
4522 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
4523 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
4524 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
4525 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
4526 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
4527 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
4528 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4529 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
4530 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
4531 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
4532 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
4533 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
4534 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
4535 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
4536 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
4537 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
4538 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
4539 *
4540 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
4541 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
4542 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
4543 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
4544 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
4545 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
4546 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
4547 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
4548 * @param ExternalTriggerEdge This parameter can be one of the following values:
4549 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4550 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4551 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4552 *
4553 * Note: This parameter is discarded in case of SW start:
4554 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4555 * @param SequencerNbRanks This parameter can be one of the following values:
4556 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4557 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4558 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4559 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4560 * @param Rank1_Channel This parameter can be one of the following values:
4561 * @arg @ref LL_ADC_CHANNEL_0
4562 * @arg @ref LL_ADC_CHANNEL_1
4563 * @arg @ref LL_ADC_CHANNEL_2
4564 * @arg @ref LL_ADC_CHANNEL_3
4565 * @arg @ref LL_ADC_CHANNEL_4
4566 * @arg @ref LL_ADC_CHANNEL_5
4567 * @arg @ref LL_ADC_CHANNEL_6
4568 * @arg @ref LL_ADC_CHANNEL_7
4569 * @arg @ref LL_ADC_CHANNEL_8
4570 * @arg @ref LL_ADC_CHANNEL_9
4571 * @arg @ref LL_ADC_CHANNEL_10
4572 * @arg @ref LL_ADC_CHANNEL_11
4573 * @arg @ref LL_ADC_CHANNEL_12
4574 * @arg @ref LL_ADC_CHANNEL_13
4575 * @arg @ref LL_ADC_CHANNEL_14
4576 * @arg @ref LL_ADC_CHANNEL_15
4577 * @arg @ref LL_ADC_CHANNEL_16
4578 * @arg @ref LL_ADC_CHANNEL_17
4579 * @arg @ref LL_ADC_CHANNEL_18
4580 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4581 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4582 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4583 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4584 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4585 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4586 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4587 *
4588 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4589 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4590 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4591 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4592 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4593 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4594 * @param Rank2_Channel This parameter can be one of the following values:
4595 * @arg @ref LL_ADC_CHANNEL_0
4596 * @arg @ref LL_ADC_CHANNEL_1
4597 * @arg @ref LL_ADC_CHANNEL_2
4598 * @arg @ref LL_ADC_CHANNEL_3
4599 * @arg @ref LL_ADC_CHANNEL_4
4600 * @arg @ref LL_ADC_CHANNEL_5
4601 * @arg @ref LL_ADC_CHANNEL_6
4602 * @arg @ref LL_ADC_CHANNEL_7
4603 * @arg @ref LL_ADC_CHANNEL_8
4604 * @arg @ref LL_ADC_CHANNEL_9
4605 * @arg @ref LL_ADC_CHANNEL_10
4606 * @arg @ref LL_ADC_CHANNEL_11
4607 * @arg @ref LL_ADC_CHANNEL_12
4608 * @arg @ref LL_ADC_CHANNEL_13
4609 * @arg @ref LL_ADC_CHANNEL_14
4610 * @arg @ref LL_ADC_CHANNEL_15
4611 * @arg @ref LL_ADC_CHANNEL_16
4612 * @arg @ref LL_ADC_CHANNEL_17
4613 * @arg @ref LL_ADC_CHANNEL_18
4614 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4615 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4616 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4617 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4618 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4619 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4620 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4621 *
4622 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4623 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4624 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4625 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4626 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4627 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4628 * @param Rank3_Channel This parameter can be one of the following values:
4629 * @arg @ref LL_ADC_CHANNEL_0
4630 * @arg @ref LL_ADC_CHANNEL_1
4631 * @arg @ref LL_ADC_CHANNEL_2
4632 * @arg @ref LL_ADC_CHANNEL_3
4633 * @arg @ref LL_ADC_CHANNEL_4
4634 * @arg @ref LL_ADC_CHANNEL_5
4635 * @arg @ref LL_ADC_CHANNEL_6
4636 * @arg @ref LL_ADC_CHANNEL_7
4637 * @arg @ref LL_ADC_CHANNEL_8
4638 * @arg @ref LL_ADC_CHANNEL_9
4639 * @arg @ref LL_ADC_CHANNEL_10
4640 * @arg @ref LL_ADC_CHANNEL_11
4641 * @arg @ref LL_ADC_CHANNEL_12
4642 * @arg @ref LL_ADC_CHANNEL_13
4643 * @arg @ref LL_ADC_CHANNEL_14
4644 * @arg @ref LL_ADC_CHANNEL_15
4645 * @arg @ref LL_ADC_CHANNEL_16
4646 * @arg @ref LL_ADC_CHANNEL_17
4647 * @arg @ref LL_ADC_CHANNEL_18
4648 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4649 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4650 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4651 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4652 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4653 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4654 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4655 *
4656 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4657 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4658 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4659 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4660 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4661 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4662 * @param Rank4_Channel This parameter can be one of the following values:
4663 * @arg @ref LL_ADC_CHANNEL_0
4664 * @arg @ref LL_ADC_CHANNEL_1
4665 * @arg @ref LL_ADC_CHANNEL_2
4666 * @arg @ref LL_ADC_CHANNEL_3
4667 * @arg @ref LL_ADC_CHANNEL_4
4668 * @arg @ref LL_ADC_CHANNEL_5
4669 * @arg @ref LL_ADC_CHANNEL_6
4670 * @arg @ref LL_ADC_CHANNEL_7
4671 * @arg @ref LL_ADC_CHANNEL_8
4672 * @arg @ref LL_ADC_CHANNEL_9
4673 * @arg @ref LL_ADC_CHANNEL_10
4674 * @arg @ref LL_ADC_CHANNEL_11
4675 * @arg @ref LL_ADC_CHANNEL_12
4676 * @arg @ref LL_ADC_CHANNEL_13
4677 * @arg @ref LL_ADC_CHANNEL_14
4678 * @arg @ref LL_ADC_CHANNEL_15
4679 * @arg @ref LL_ADC_CHANNEL_16
4680 * @arg @ref LL_ADC_CHANNEL_17
4681 * @arg @ref LL_ADC_CHANNEL_18
4682 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4683 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4684 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4685 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4686 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4687 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4688 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4689 *
4690 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4691 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4692 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4693 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4694 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4695 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4696 * @retval None
4697 */
4706 {
4707 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4708 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4709 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4710 /* because containing other bits reserved for other purpose. */
4711 /* If parameter "TriggerSource" is set to SW start, then parameter */
4712 /* "ExternalTriggerEdge" is discarded. */
4714 ADC_JSQR_JEXTSEL |
4715 ADC_JSQR_JEXTEN |
4716 ADC_JSQR_JSQ4 |
4717 ADC_JSQR_JSQ3 |
4718 ADC_JSQR_JSQ2 |
4719 ADC_JSQR_JSQ1 |
4720 ADC_JSQR_JL ,
4721 TriggerSource |
4723 ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4724 ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4725 ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4726 ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4727 SequencerNbRanks
4728 );
4729 }
4731 /**
4732 * @}
4733 */
4735 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4736 * @{
4737 */
4739 /**
4740 * @brief Set sampling time of the selected ADC channel
4741 * Unit: ADC clock cycles.
4742 * @note On this device, sampling time is on channel scope: independently
4743 * of channel mapped on ADC group regular or injected.
4744 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4745 * converted:
4746 * sampling time constraints must be respected (sampling time can be
4747 * adjusted in function of ADC clock frequency and sampling time
4748 * setting).
4749 * Refer to device datasheet for timings values (parameters TS_vrefint,
4750 * TS_temp, ...).
4751 * @note Conversion time is the addition of sampling time and processing time.
4752 * On this STM32 serie, ADC processing time is:
4753 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4754 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4755 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4756 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4757 * @note In case of ADC conversion of internal channel (VrefInt,
4758 * temperature sensor, ...), a sampling time minimum value
4759 * is required.
4760 * Refer to device datasheet.
4761 * @note On this STM32 serie, setting of this feature is conditioned to
4762 * ADC state:
4763 * ADC must be disabled or enabled without conversion on going
4764 * on either groups regular or injected.
4765 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4766 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4767 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4768 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4769 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4770 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4771 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4772 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4773 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4774 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4775 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4776 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4777 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4778 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4779 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4780 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4781 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4782 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4783 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4784 * @param ADCx ADC instance
4785 * @param Channel This parameter can be one of the following values:
4786 * @arg @ref LL_ADC_CHANNEL_0
4787 * @arg @ref LL_ADC_CHANNEL_1
4788 * @arg @ref LL_ADC_CHANNEL_2
4789 * @arg @ref LL_ADC_CHANNEL_3
4790 * @arg @ref LL_ADC_CHANNEL_4
4791 * @arg @ref LL_ADC_CHANNEL_5
4792 * @arg @ref LL_ADC_CHANNEL_6
4793 * @arg @ref LL_ADC_CHANNEL_7
4794 * @arg @ref LL_ADC_CHANNEL_8
4795 * @arg @ref LL_ADC_CHANNEL_9
4796 * @arg @ref LL_ADC_CHANNEL_10
4797 * @arg @ref LL_ADC_CHANNEL_11
4798 * @arg @ref LL_ADC_CHANNEL_12
4799 * @arg @ref LL_ADC_CHANNEL_13
4800 * @arg @ref LL_ADC_CHANNEL_14
4801 * @arg @ref LL_ADC_CHANNEL_15
4802 * @arg @ref LL_ADC_CHANNEL_16
4803 * @arg @ref LL_ADC_CHANNEL_17
4804 * @arg @ref LL_ADC_CHANNEL_18
4805 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4806 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4807 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4808 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4809 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4810 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4811 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4812 *
4813 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4814 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4815 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4816 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4817 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4818 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4819 * @param SamplingTime This parameter can be one of the following values:
4820 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4821 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4822 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
4823 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
4824 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
4825 * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
4826 * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
4827 * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
4828 * @retval None
4829 */
4830 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4831 {
4832 /* Set bits with content of parameter "SamplingTime" with bits position */
4833 /* in register and register position depending on parameter "Channel". */
4834 /* Parameter "Channel" is used with masks because containing */
4835 /* other bits reserved for other purpose. */
4836 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
4841 }
4843 /**
4844 * @brief Get sampling time of the selected ADC channel
4845 * Unit: ADC clock cycles.
4846 * @note On this device, sampling time is on channel scope: independently
4847 * of channel mapped on ADC group regular or injected.
4848 * @note Conversion time is the addition of sampling time and processing time.
4849 * On this STM32 serie, ADC processing time is:
4850 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4851 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4852 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4853 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4854 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4855 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4856 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4857 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4858 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4859 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4860 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4861 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4862 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4863 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4864 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4865 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4866 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4867 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4868 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4869 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4870 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4871 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4872 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4873 * @param ADCx ADC instance
4874 * @param Channel This parameter can be one of the following values:
4875 * @arg @ref LL_ADC_CHANNEL_0
4876 * @arg @ref LL_ADC_CHANNEL_1
4877 * @arg @ref LL_ADC_CHANNEL_2
4878 * @arg @ref LL_ADC_CHANNEL_3
4879 * @arg @ref LL_ADC_CHANNEL_4
4880 * @arg @ref LL_ADC_CHANNEL_5
4881 * @arg @ref LL_ADC_CHANNEL_6
4882 * @arg @ref LL_ADC_CHANNEL_7
4883 * @arg @ref LL_ADC_CHANNEL_8
4884 * @arg @ref LL_ADC_CHANNEL_9
4885 * @arg @ref LL_ADC_CHANNEL_10
4886 * @arg @ref LL_ADC_CHANNEL_11
4887 * @arg @ref LL_ADC_CHANNEL_12
4888 * @arg @ref LL_ADC_CHANNEL_13
4889 * @arg @ref LL_ADC_CHANNEL_14
4890 * @arg @ref LL_ADC_CHANNEL_15
4891 * @arg @ref LL_ADC_CHANNEL_16
4892 * @arg @ref LL_ADC_CHANNEL_17
4893 * @arg @ref LL_ADC_CHANNEL_18
4894 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4895 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4896 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4897 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4898 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4899 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4900 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4901 *
4902 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4903 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4904 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4905 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4906 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4907 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4908 * @retval Returned value can be one of the following values:
4909 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4910 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4911 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
4912 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
4913 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
4914 * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
4915 * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
4916 * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
4917 */
4919 {
4920 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
4925 );
4926 }
4928 /**
4929 * @brief Set mode single-ended or differential input of the selected
4930 * ADC channel.
4931 * @note Channel ending is on channel scope: independently of channel mapped
4932 * on ADC group regular or injected.
4933 * In differential mode: Differential measurement is carried out
4934 * between the selected channel 'i' (positive input) and
4935 * channel 'i+1' (negative input). Only channel 'i' has to be
4936 * configured, channel 'i+1' is configured automatically.
4937 * @note Refer to Reference Manual to ensure the selected channel is
4938 * available in differential mode.
4939 * For example, internal channels (VrefInt, TempSensor, ...) are
4940 * not available in differential mode.
4941 * @note When configuring a channel 'i' in differential mode,
4942 * the channel 'i+1' is not usable separately.
4943 * @note On STM32F3, channels 16, 17, 18 of ADC1,
4944 * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
4945 * are internally fixed to single-ended inputs configuration.
4946 * @note For ADC channels configured in differential mode, both inputs
4947 * should be biased at (Vref+)/2 +/-200mV.
4948 * (Vref+ is the analog voltage reference)
4949 * @note On this STM32 serie, setting of this feature is conditioned to
4950 * ADC state:
4951 * ADC must be ADC disabled.
4952 * @note One or several values can be selected.
4953 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4954 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
4955 * @param ADCx ADC instance
4956 * @param Channel This parameter can be one of the following values:
4957 * @arg @ref LL_ADC_CHANNEL_1
4958 * @arg @ref LL_ADC_CHANNEL_2
4959 * @arg @ref LL_ADC_CHANNEL_3
4960 * @arg @ref LL_ADC_CHANNEL_4
4961 * @arg @ref LL_ADC_CHANNEL_5
4962 * @arg @ref LL_ADC_CHANNEL_6
4963 * @arg @ref LL_ADC_CHANNEL_7
4964 * @arg @ref LL_ADC_CHANNEL_8
4965 * @arg @ref LL_ADC_CHANNEL_9
4966 * @arg @ref LL_ADC_CHANNEL_10
4967 * @arg @ref LL_ADC_CHANNEL_11
4968 * @arg @ref LL_ADC_CHANNEL_12
4969 * @arg @ref LL_ADC_CHANNEL_13
4970 * @arg @ref LL_ADC_CHANNEL_14
4971 * @arg @ref LL_ADC_CHANNEL_15
4972 * @arg @ref LL_ADC_CHANNEL_16 (1)
4973 *
4974 * (1) On STM32F3, parameter available only on ADC instance: ADC1.
4975 * @param SingleDiff This parameter can be a combination of the following values:
4976 * @arg @ref LL_ADC_SINGLE_ENDED
4977 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4978 * @retval None
4979 */
4980 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4981 {
4982 /* Bits of channels in single or differential mode are set only for */
4983 /* differential mode (for single mode, mask of bits allowed to be set is */
4984 /* shifted out of range of bits of channels in single or differential mode. */
4987 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4988 }
4990 /**
4991 * @brief Get mode single-ended or differential input of the selected
4992 * ADC channel.
4993 * @note When configuring a channel 'i' in differential mode,
4994 * the channel 'i+1' is not usable separately.
4995 * Therefore, to ensure a channel is configured in single-ended mode,
4996 * the configuration of channel itself and the channel 'i-1' must be
4997 * read back (to ensure that the selected channel channel has not been
4998 * configured in differential mode by the previous channel).
4999 * @note Refer to Reference Manual to ensure the selected channel is
5000 * available in differential mode.
5001 * For example, internal channels (VrefInt, TempSensor, ...) are
5002 * not available in differential mode.
5003 * @note When configuring a channel 'i' in differential mode,
5004 * the channel 'i+1' is not usable separately.
5005 * @note On STM32F3, channels 16, 17, 18 of ADC1,
5006 * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
5007 * are internally fixed to single-ended inputs configuration.
5008 * @note One or several values can be selected. In this case, the value
5009 * returned is null if all channels are in single ended-mode.
5010 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5011 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
5012 * @param ADCx ADC instance
5013 * @param Channel This parameter can be a combination of the following values:
5014 * @arg @ref LL_ADC_CHANNEL_0
5015 * @arg @ref LL_ADC_CHANNEL_1
5016 * @arg @ref LL_ADC_CHANNEL_2
5017 * @arg @ref LL_ADC_CHANNEL_3
5018 * @arg @ref LL_ADC_CHANNEL_4
5019 * @arg @ref LL_ADC_CHANNEL_5
5020 * @arg @ref LL_ADC_CHANNEL_6
5021 * @arg @ref LL_ADC_CHANNEL_7
5022 * @arg @ref LL_ADC_CHANNEL_8
5023 * @arg @ref LL_ADC_CHANNEL_9
5024 * @arg @ref LL_ADC_CHANNEL_10
5025 * @arg @ref LL_ADC_CHANNEL_11
5026 * @arg @ref LL_ADC_CHANNEL_12
5027 * @arg @ref LL_ADC_CHANNEL_13
5028 * @arg @ref LL_ADC_CHANNEL_14
5029 * @arg @ref LL_ADC_CHANNEL_15
5030 * @arg @ref LL_ADC_CHANNEL_16 (1)
5031 *
5032 * (1) On STM32F3, parameter available only on ADC instance: ADC1.
5033 * @retval 0: channel in single-ended mode, else: channel in differential mode
5034 */
5036 {
5038 }
5040 /**
5041 * @}
5042 */
5044 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5045 * @{
5046 */
5048 /**
5049 * @brief Set ADC analog watchdog monitored channels:
5050 * a single channel, multiple channels or all channels,
5051 * on ADC groups regular and-or injected.
5052 * @note Once monitored channels are selected, analog watchdog
5053 * is enabled.
5054 * @note In case of need to define a single channel to monitor
5055 * with analog watchdog from sequencer channel definition,
5056 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5057 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5058 * instance:
5059 * - AWD standard (instance AWD1):
5060 * - channels monitored: can monitor 1 channel or all channels.
5061 * - groups monitored: ADC groups regular and-or injected.
5062 * - resolution: resolution is not limited (corresponds to
5063 * ADC resolution configured).
5064 * - AWD flexible (instances AWD2, AWD3):
5065 * - channels monitored: flexible on channels monitored, selection is
5066 * channel wise, from from 1 to all channels.
5067 * Specificity of this analog watchdog: Multiple channels can
5068 * be selected. For example:
5069 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5070 * - groups monitored: not selection possible (monitoring on both
5071 * groups regular and injected).
5072 * Channels selected are monitored on groups regular and injected:
5073 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5074 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5075 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5076 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5077 * the 2 LSB are ignored.
5078 * @note On this STM32 serie, setting of this feature is conditioned to
5079 * ADC state:
5080 * ADC must be disabled or enabled without conversion on going
5081 * on either groups regular or injected.
5082 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5083 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5084 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5085 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5086 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5087 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5088 * @param ADCx ADC instance
5089 * @param AWDy This parameter can be one of the following values:
5090 * @arg @ref LL_ADC_AWD1
5091 * @arg @ref LL_ADC_AWD2
5092 * @arg @ref LL_ADC_AWD3
5093 * @param AWDChannelGroup This parameter can be one of the following values:
5094 * @arg @ref LL_ADC_AWD_DISABLE
5095 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5096 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5097 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5098 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5099 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5100 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5101 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5102 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5103 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5104 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5105 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5106 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5107 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5108 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5109 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5110 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5111 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5112 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5113 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5114 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5115 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5116 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5117 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5118 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5119 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5120 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5121 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5122 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5123 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5124 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5125 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5126 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5127 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5128 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5129 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5130 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5131 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5132 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5133 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5134 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5135 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5136 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5137 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5138 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5139 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5140 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5141 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5142 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5143 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5144 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5145 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5146 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5147 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5148 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5149 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5150 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5151 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5152 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5153 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5154 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5155 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
5156 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
5157 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
5158 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5159 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5160 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5161 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5162 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5163 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5164 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
5165 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
5166 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
5167 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
5168 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
5169 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
5170 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
5171 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
5172 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
5173 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
5174 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
5175 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
5176 *
5177 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
5178 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
5179 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
5180 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
5181 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
5182 * (5) On STM32F3, ADC channel available only on all ADC instances, but
5183 * only one ADC instance is allowed to be connected to VrefInt at the same time.
5184 * @retval None
5185 */
5186 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5187 {
5188 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5189 /* in register and register position depending on parameter "AWDy". */
5190 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5191 /* containing other bits reserved for other purpose. */
5192 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
5198 }
5200 /**
5201 * @brief Get ADC analog watchdog monitored channel.
5202 * @note Usage of the returned channel number:
5203 * - To reinject this channel into another function LL_ADC_xxx:
5204 * the returned channel number is only partly formatted on definition
5205 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5206 * with parts of literals LL_ADC_CHANNEL_x or using
5207 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5208 * Then the selected literal LL_ADC_CHANNEL_x can be used
5209 * as parameter for another function.
5210 * - To get the channel number in decimal format:
5211 * process the returned value with the helper macro
5212 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5213 * Applicable only when the analog watchdog is set to monitor
5214 * one channel.
5215 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5216 * instance:
5217 * - AWD standard (instance AWD1):
5218 * - channels monitored: can monitor 1 channel or all channels.
5219 * - groups monitored: ADC groups regular and-or injected.
5220 * - resolution: resolution is not limited (corresponds to
5221 * ADC resolution configured).
5222 * - AWD flexible (instances AWD2, AWD3):
5223 * - channels monitored: flexible on channels monitored, selection is
5224 * channel wise, from from 1 to all channels.
5225 * Specificity of this analog watchdog: Multiple channels can
5226 * be selected. For example:
5227 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5228 * - groups monitored: not selection possible (monitoring on both
5229 * groups regular and injected).
5230 * Channels selected are monitored on groups regular and injected:
5231 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5232 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5233 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5234 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5235 * the 2 LSB are ignored.
5236 * @note On this STM32 serie, setting of this feature is conditioned to
5237 * ADC state:
5238 * ADC must be disabled or enabled without conversion on going
5239 * on either groups regular or injected.
5240 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5241 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5242 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5243 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5244 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5245 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5246 * @param ADCx ADC instance
5247 * @param AWDy This parameter can be one of the following values:
5248 * @arg @ref LL_ADC_AWD1
5249 * @arg @ref LL_ADC_AWD2 (1)
5250 * @arg @ref LL_ADC_AWD3 (1)
5251 *
5252 * (1) On this AWD number, monitored channel can be retrieved
5253 * if only 1 channel is programmed (or none or all channels).
5254 * This function cannot retrieve monitored channel if
5255 * multiple channels are programmed simultaneously
5256 * by bitfield.
5257 * @retval Returned value can be one of the following values:
5258 * @arg @ref LL_ADC_AWD_DISABLE
5259 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5260 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5261 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5262 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5263 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5264 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5265 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5266 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5267 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5268 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5269 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5270 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5271 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5272 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5273 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5274 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5275 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5276 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5277 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5278 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5279 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5280 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5281 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5282 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5283 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5284 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5285 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5286 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5287 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5288 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5289 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5290 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5291 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5292 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5293 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5294 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5295 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5296 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5297 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5298 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5299 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5300 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5301 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5302 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5303 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5304 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5305 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5306 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5307 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5308 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5309 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5310 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5311 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5312 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5313 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5314 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5315 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5316 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5317 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5318 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5319 *
5320 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.
5321 */
5323 {
5324 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
5327 /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
5328 /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
5331 /* Set variable of AWD1 monitored channel according to AWD1 features */
5332 /* and ADC channel definition: */
5333 /* - channel ID with number */
5334 /* - channel ID with bitfield */
5335 /* - AWD1 single or all channels */
5336 /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
5337 /* AWD2 or AWD3 selected). */
5338 register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
5341 | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
5343 )
5344 * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
5345 );
5347 /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */
5348 /* features and ADC channel definition: */
5349 /* - channel ID with number */
5350 /* - channel ID with bitfield */
5351 /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */
5352 /* shift AWD1 equivalent single-all channels out of register) */
5353 /* - AWD2-3 enable or disable */
5354 /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */
5355 /* channel can be read back if only 1 channel monitoring */
5356 /* is activated, therefore the channel monitoring value channel "3" */
5357 /* is not not supported by this function, there is no risk of */
5358 /* conflict. */
5359 register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
5363 | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
5365 ) >> AWD23Enabled
5369 }
5371 /**
5372 * @brief Set ADC analog watchdog thresholds value of both thresholds
5373 * high and low.
5374 * @note If value of only one threshold high or low must be set,
5375 * use function @ref LL_ADC_SetAnalogWDThresholds().
5376 * @note In case of ADC resolution different of 12 bits,
5377 * analog watchdog thresholds data require a specific shift.
5378 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5379 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5380 * instance:
5381 * - AWD standard (instance AWD1):
5382 * - channels monitored: can monitor 1 channel or all channels.
5383 * - groups monitored: ADC groups regular and-or injected.
5384 * - resolution: resolution is not limited (corresponds to
5385 * ADC resolution configured).
5386 * - AWD flexible (instances AWD2, AWD3):
5387 * - channels monitored: flexible on channels monitored, selection is
5388 * channel wise, from from 1 to all channels.
5389 * Specificity of this analog watchdog: Multiple channels can
5390 * be selected. For example:
5391 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5392 * - groups monitored: not selection possible (monitoring on both
5393 * groups regular and injected).
5394 * Channels selected are monitored on groups regular and injected:
5395 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5396 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5397 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5398 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5399 * the 2 LSB are ignored.
5400 * @note On this STM32 serie, setting of this feature is conditioned to
5401 * ADC state:
5402 * ADC must be disabled or enabled without conversion on going
5403 * on either groups regular or injected.
5404 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5405 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5406 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5407 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5408 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5409 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5410 * @param ADCx ADC instance
5411 * @param AWDy This parameter can be one of the following values:
5412 * @arg @ref LL_ADC_AWD1
5413 * @arg @ref LL_ADC_AWD2
5414 * @arg @ref LL_ADC_AWD3
5415 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5416 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5417 * @retval None
5418 */
5419 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
5420 {
5421 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5422 /* position in register and register position depending on parameter */
5423 /* "AWDy". */
5424 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5425 /* containing other bits reserved for other purpose. */
5426 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5431 }
5433 /**
5434 * @brief Set ADC analog watchdog threshold value of threshold
5435 * high or low.
5436 * @note If values of both thresholds high or low must be set,
5437 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5438 * @note In case of ADC resolution different of 12 bits,
5439 * analog watchdog thresholds data require a specific shift.
5440 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5441 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5442 * instance:
5443 * - AWD standard (instance AWD1):
5444 * - channels monitored: can monitor 1 channel or all channels.
5445 * - groups monitored: ADC groups regular and-or injected.
5446 * - resolution: resolution is not limited (corresponds to
5447 * ADC resolution configured).
5448 * - AWD flexible (instances AWD2, AWD3):
5449 * - channels monitored: flexible on channels monitored, selection is
5450 * channel wise, from from 1 to all channels.
5451 * Specificity of this analog watchdog: Multiple channels can
5452 * be selected. For example:
5453 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5454 * - groups monitored: not selection possible (monitoring on both
5455 * groups regular and injected).
5456 * Channels selected are monitored on groups regular and injected:
5457 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5458 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5459 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5460 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5461 * the 2 LSB are ignored.
5462 * @note On this STM32 serie, setting of this feature is conditioned to
5463 * ADC state:
5464 * ADC must be disabled or enabled without conversion on going
5465 * on either groups regular or injected.
5466 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5467 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5468 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5469 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5470 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5471 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5472 * @param ADCx ADC instance
5473 * @param AWDy This parameter can be one of the following values:
5474 * @arg @ref LL_ADC_AWD1
5475 * @arg @ref LL_ADC_AWD2
5476 * @arg @ref LL_ADC_AWD3
5477 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5478 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5479 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5480 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5481 * @retval None
5482 */
5483 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
5484 {
5485 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5486 /* position in register and register position depending on parameters */
5487 /* "AWDThresholdsHighLow" and "AWDy". */
5488 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5489 /* containing other bits reserved for other purpose. */
5490 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5493 AWDThresholdsHighLow,
5495 }
5497 /**
5498 * @brief Get ADC analog watchdog threshold value of threshold high,
5499 * threshold low or raw data with ADC thresholds high and low
5500 * concatenated.
5501 * @note If raw data with ADC thresholds high and low is retrieved,
5502 * the data of each threshold high or low can be isolated
5503 * using helper macro:
5504 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5505 * @note In case of ADC resolution different of 12 bits,
5506 * analog watchdog thresholds data require a specific shift.
5507 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5508 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5509 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5510 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5511 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5512 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5513 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5514 * @param ADCx ADC instance
5515 * @param AWDy This parameter can be one of the following values:
5516 * @arg @ref LL_ADC_AWD1
5517 * @arg @ref LL_ADC_AWD2
5518 * @arg @ref LL_ADC_AWD3
5519 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5520 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5521 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5522 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5523 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5524 */
5525 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5526 {
5527 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5532 );
5533 }
5535 /**
5536 * @}
5537 */
5539 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5540 * @{
5541 */
5543 #if defined(ADC_MULTIMODE_SUPPORT)
5544 /**
5545 * @brief Set ADC multimode configuration to operate in independent mode
5546 * or multimode (for devices with several ADC instances).
5547 * @note If multimode configuration: the selected ADC instance is
5548 * either master or slave depending on hardware.
5549 * Refer to reference manual.
5550 * @note On this STM32 serie, setting of this feature is conditioned to
5551 * ADC state:
5552 * All ADC instances of the ADC common group must be disabled.
5553 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5554 * ADC instance or by using helper macro
5555 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5556 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5557 * @param ADCxy_COMMON ADC common instance
5558 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5559 * @param Multimode This parameter can be one of the following values:
5560 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5561 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5562 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5563 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5564 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5565 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5566 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5567 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5568 * @retval None
5569 */
5571 {
5573 }
5575 /**
5576 * @brief Get ADC multimode configuration to operate in independent mode
5577 * or multimode (for devices with several ADC instances).
5578 * @note If multimode configuration: the selected ADC instance is
5579 * either master or slave depending on hardware.
5580 * Refer to reference manual.
5581 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5582 * @param ADCxy_COMMON ADC common instance
5583 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5584 * @retval Returned value can be one of the following values:
5585 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5586 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5587 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5588 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5589 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5590 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5591 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5592 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5593 */
5595 {
5597 }
5599 /**
5600 * @brief Set ADC multimode conversion data transfer: no transfer
5601 * or transfer by DMA.
5602 * @note If ADC multimode transfer by DMA is not selected:
5603 * each ADC uses its own DMA channel, with its individual
5604 * DMA transfer settings.
5605 * If ADC multimode transfer by DMA is selected:
5606 * One DMA channel is used for both ADC (DMA of ADC master)
5607 * Specifies the DMA requests mode:
5608 * - Limited mode (One shot mode): DMA transfer requests are stopped
5609 * when number of DMA data transfers (number of
5610 * ADC conversions) is reached.
5611 * This ADC mode is intended to be used with DMA mode non-circular.
5612 * - Unlimited mode: DMA transfer requests are unlimited,
5613 * whatever number of DMA data transfers (number of
5614 * ADC conversions).
5615 * This ADC mode is intended to be used with DMA mode circular.
5616 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5617 * mode non-circular:
5618 * when DMA transfers size will be reached, DMA will stop transfers of
5619 * ADC conversions data ADC will raise an overrun error
5620 * (overrun flag and interruption if enabled).
5621 * @note How to retrieve multimode conversion data:
5622 * Whatever multimode transfer by DMA setting: using function
5623 * @ref LL_ADC_REG_ReadMultiConversionData32().
5624 * If ADC multimode transfer by DMA is selected: conversion data
5625 * is a raw data with ADC master and slave concatenated.
5626 * A macro is available to get the conversion data of
5627 * ADC master or ADC slave: see helper macro
5628 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5629 * @note On this STM32 serie, setting of this feature is conditioned to
5630 * ADC state:
5631 * All ADC instances of the ADC common group must be disabled
5632 * or enabled without conversion on going on group regular.
5633 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
5634 * CCR DMACFG LL_ADC_SetMultiDMATransfer
5635 * @param ADCxy_COMMON ADC common instance
5636 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5637 * @param MultiDMATransfer This parameter can be one of the following values:
5638 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5639 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5640 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5641 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5642 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5643 * @retval None
5644 */
5645 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5646 {
5648 }
5650 /**
5651 * @brief Get ADC multimode conversion data transfer: no transfer
5652 * or transfer by DMA.
5653 * @note If ADC multimode transfer by DMA is not selected:
5654 * each ADC uses its own DMA channel, with its individual
5655 * DMA transfer settings.
5656 * If ADC multimode transfer by DMA is selected:
5657 * One DMA channel is used for both ADC (DMA of ADC master)
5658 * Specifies the DMA requests mode:
5659 * - Limited mode (One shot mode): DMA transfer requests are stopped
5660 * when number of DMA data transfers (number of
5661 * ADC conversions) is reached.
5662 * This ADC mode is intended to be used with DMA mode non-circular.
5663 * - Unlimited mode: DMA transfer requests are unlimited,
5664 * whatever number of DMA data transfers (number of
5665 * ADC conversions).
5666 * This ADC mode is intended to be used with DMA mode circular.
5667 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5668 * mode non-circular:
5669 * when DMA transfers size will be reached, DMA will stop transfers of
5670 * ADC conversions data ADC will raise an overrun error
5671 * (overrun flag and interruption if enabled).
5672 * @note How to retrieve multimode conversion data:
5673 * Whatever multimode transfer by DMA setting: using function
5674 * @ref LL_ADC_REG_ReadMultiConversionData32().
5675 * If ADC multimode transfer by DMA is selected: conversion data
5676 * is a raw data with ADC master and slave concatenated.
5677 * A macro is available to get the conversion data of
5678 * ADC master or ADC slave: see helper macro
5679 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5680 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
5681 * CCR DMACFG LL_ADC_GetMultiDMATransfer
5682 * @param ADCxy_COMMON ADC common instance
5683 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5684 * @retval Returned value can be one of the following values:
5685 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5686 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5687 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5688 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5689 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5690 */
5692 {
5694 }
5696 /**
5697 * @brief Set ADC multimode delay between 2 sampling phases.
5698 * @note The sampling delay range depends on ADC resolution:
5699 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5700 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5701 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5702 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5703 * @note On this STM32 serie, setting of this feature is conditioned to
5704 * ADC state:
5705 * All ADC instances of the ADC common group must be disabled.
5706 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5707 * ADC instance or by using helper macro helper macro
5708 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5709 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5710 * @param ADCxy_COMMON ADC common instance
5711 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5712 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5719 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5720 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5721 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5722 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5723 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5724 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5725 *
5726 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5727 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5728 * (3) Parameter available only if ADC resolution is 12 bits.
5729 * @retval None
5730 */
5731 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5732 {
5734 }
5736 /**
5737 * @brief Get ADC multimode delay between 2 sampling phases.
5738 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5739 * @param ADCxy_COMMON ADC common instance
5740 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5741 * @retval Returned value can be one of the following values:
5742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5753 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5754 *
5755 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5756 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5757 * (3) Parameter available only if ADC resolution is 12 bits.
5758 */
5760 {
5762 }
5765 /**
5766 * @}
5767 */
5768 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5769 * @{
5770 */
5772 /**
5773 * @brief Enable ADC instance internal voltage regulator.
5774 * @note On this STM32 serie, after ADC internal voltage regulator enable,
5775 * a delay for ADC internal voltage regulator stabilization
5776 * is required before performing a ADC calibration or ADC enable.
5777 * Refer to device datasheet, parameter tADCVREG_STUP.
5778 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5779 * @note On this STM32 serie, setting of this feature is conditioned to
5780 * ADC state:
5781 * ADC must be ADC disabled.
5782 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5783 * @param ADCx ADC instance
5784 * @retval None
5785 */
5787 {
5788 /* 1. Set the intermediate state before moving the ADC voltage regulator */
5789 /* to state enable. */
5791 /* 2. Set the final state of ADC voltage regulator enable */
5792 /* (ADVREGEN bits set to 0x01). */
5793 /* Note: Write register with some additional bits forced to state reset */
5794 /* instead of modifying only the selected bit for this function, */
5795 /* to not interfere with bits with HW property "rs". */
5797 ADC_CR_BITS_PROPERTY_RS,
5798 ADC_CR_ADVREGEN_0);
5799 }
5801 /**
5802 * @brief Disable ADC internal voltage regulator.
5803 * @note On this STM32 serie, setting of this feature is conditioned to
5804 * ADC state:
5805 * ADC must be ADC disabled.
5806 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5807 * @param ADCx ADC instance
5808 * @retval None
5809 */
5811 {
5813 }
5815 /**
5816 * @brief Get the selected ADC instance internal voltage regulator state.
5817 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5818 * @param ADCx ADC instance
5819 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5820 */
5822 {
5824 }
5826 /**
5827 * @brief Enable the selected ADC instance.
5828 * @note On this STM32 serie, after ADC enable, a delay for
5829 * ADC internal analog stabilization is required before performing a
5830 * ADC conversion start.
5831 * Refer to device datasheet, parameter tSTAB.
5832 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5833 * is enabled and when conversion clock is active.
5834 * (not only core clock: this ADC has a dual clock domain)
5835 * @note On this STM32 serie, setting of this feature is conditioned to
5836 * ADC state:
5837 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
5838 * @rmtoll CR ADEN LL_ADC_Enable
5839 * @param ADCx ADC instance
5840 * @retval None
5841 */
5843 {
5844 /* Note: Write register with some additional bits forced to state reset */
5845 /* instead of modifying only the selected bit for this function, */
5846 /* to not interfere with bits with HW property "rs". */
5848 ADC_CR_BITS_PROPERTY_RS,
5849 ADC_CR_ADEN);
5850 }
5852 /**
5853 * @brief Disable the selected ADC instance.
5854 * @note On this STM32 serie, setting of this feature is conditioned to
5855 * ADC state:
5856 * ADC must be not disabled. Must be enabled without conversion on going
5857 * on either groups regular or injected.
5858 * @rmtoll CR ADDIS LL_ADC_Disable
5859 * @param ADCx ADC instance
5860 * @retval None
5861 */
5863 {
5864 /* Note: Write register with some additional bits forced to state reset */
5865 /* instead of modifying only the selected bit for this function, */
5866 /* to not interfere with bits with HW property "rs". */
5868 ADC_CR_BITS_PROPERTY_RS,
5869 ADC_CR_ADDIS);
5870 }
5872 /**
5873 * @brief Get the selected ADC instance enable state.
5874 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5875 * is enabled and when conversion clock is active.
5876 * (not only core clock: this ADC has a dual clock domain)
5877 * @rmtoll CR ADEN LL_ADC_IsEnabled
5878 * @param ADCx ADC instance
5879 * @retval 0: ADC is disabled, 1: ADC is enabled.
5880 */
5882 {
5884 }
5886 /**
5887 * @brief Get the selected ADC instance disable state.
5888 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
5889 * @param ADCx ADC instance
5890 * @retval 0: no ADC disable command on going.
5891 */
5893 {
5895 }
5897 /**
5898 * @brief Start ADC calibration in the mode single-ended
5899 * or differential (for devices with differential mode available).
5900 * @note On this STM32 serie, a minimum number of ADC clock cycles
5901 * are required between ADC end of calibration and ADC enable.
5902 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
5903 * @note For devices with differential mode available:
5904 * Calibration of offset is specific to each of
5905 * single-ended and differential modes
5906 * (calibration run must be performed for each of these
5907 * differential modes, if used afterwards and if the application
5908 * requires their calibration).
5909 * @note On this STM32 serie, setting of this feature is conditioned to
5910 * ADC state:
5911 * ADC must be ADC disabled.
5912 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
5913 * CR ADCALDIF LL_ADC_StartCalibration
5914 * @param ADCx ADC instance
5915 * @param SingleDiff This parameter can be one of the following values:
5916 * @arg @ref LL_ADC_SINGLE_ENDED
5917 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5918 * @retval None
5919 */
5921 {
5922 /* Note: Write register with some additional bits forced to state reset */
5923 /* instead of modifying only the selected bit for this function, */
5924 /* to not interfere with bits with HW property "rs". */
5928 }
5930 /**
5931 * @brief Get ADC calibration state.
5932 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
5933 * @param ADCx ADC instance
5934 * @retval 0: calibration complete, 1: calibration in progress.
5935 */
5937 {
5939 }
5941 /**
5942 * @}
5943 */
5945 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
5946 * @{
5947 */
5949 /**
5950 * @brief Start ADC group regular conversion.
5951 * @note On this STM32 serie, this function is relevant for both
5952 * internal trigger (SW start) and external trigger:
5953 * - If ADC trigger has been set to software start, ADC conversion
5954 * starts immediately.
5955 * - If ADC trigger has been set to external trigger, ADC conversion
5956 * will start at next trigger event (on the selected trigger edge)
5957 * following the ADC start conversion command.
5958 * @note On this STM32 serie, setting of this feature is conditioned to
5959 * ADC state:
5960 * ADC must be enabled without conversion on going on group regular,
5961 * without conversion stop command on going on group regular,
5962 * without ADC disable command on going.
5963 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
5964 * @param ADCx ADC instance
5965 * @retval None
5966 */
5968 {
5969 /* Note: Write register with some additional bits forced to state reset */
5970 /* instead of modifying only the selected bit for this function, */
5971 /* to not interfere with bits with HW property "rs". */
5973 ADC_CR_BITS_PROPERTY_RS,
5974 ADC_CR_ADSTART);
5975 }
5977 /**
5978 * @brief Stop ADC group regular conversion.
5979 * @note On this STM32 serie, setting of this feature is conditioned to
5980 * ADC state:
5981 * ADC must be enabled with conversion on going on group regular,
5982 * without ADC disable command on going.
5983 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
5984 * @param ADCx ADC instance
5985 * @retval None
5986 */
5988 {
5989 /* Note: Write register with some additional bits forced to state reset */
5990 /* instead of modifying only the selected bit for this function, */
5991 /* to not interfere with bits with HW property "rs". */
5993 ADC_CR_BITS_PROPERTY_RS,
5994 ADC_CR_ADSTP);
5995 }
5997 /**
5998 * @brief Get ADC group regular conversion state.
5999 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6000 * @param ADCx ADC instance
6001 * @retval 0: no conversion is on going on ADC group regular.
6002 */
6004 {
6006 }
6008 /**
6009 * @brief Get ADC group regular command of conversion stop state
6010 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6011 * @param ADCx ADC instance
6012 * @retval 0: no command of conversion stop is on going on ADC group regular.
6013 */
6015 {
6017 }
6019 /**
6020 * @brief Get ADC group regular conversion data, range fit for
6021 * all ADC configurations: all ADC resolutions and
6022 * all oversampling increased data width (for devices
6023 * with feature oversampling).
6024 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6025 * @param ADCx ADC instance
6026 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6027 */
6029 {
6031 }
6033 /**
6034 * @brief Get ADC group regular conversion data, range fit for
6035 * ADC resolution 12 bits.
6036 * @note For devices with feature oversampling: Oversampling
6037 * can increase data width, function for extended range
6038 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6039 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6040 * @param ADCx ADC instance
6041 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6042 */
6044 {
6046 }
6048 /**
6049 * @brief Get ADC group regular conversion data, range fit for
6050 * ADC resolution 10 bits.
6051 * @note For devices with feature oversampling: Oversampling
6052 * can increase data width, function for extended range
6053 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6054 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6055 * @param ADCx ADC instance
6056 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6057 */
6059 {
6061 }
6063 /**
6064 * @brief Get ADC group regular conversion data, range fit for
6065 * ADC resolution 8 bits.
6066 * @note For devices with feature oversampling: Oversampling
6067 * can increase data width, function for extended range
6068 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6069 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6070 * @param ADCx ADC instance
6071 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6072 */
6074 {
6076 }
6078 /**
6079 * @brief Get ADC group regular conversion data, range fit for
6080 * ADC resolution 6 bits.
6081 * @note For devices with feature oversampling: Oversampling
6082 * can increase data width, function for extended range
6083 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6084 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6085 * @param ADCx ADC instance
6086 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6087 */
6089 {
6091 }
6093 #if defined(ADC_MULTIMODE_SUPPORT)
6094 /**
6095 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6096 * or raw data with ADC master and slave concatenated.
6097 * @note If raw data with ADC master and slave concatenated is retrieved,
6098 * a macro is available to get the conversion data of
6099 * ADC master or ADC slave: see helper macro
6100 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6101 * (however this macro is mainly intended for multimode
6102 * transfer by DMA, because this function can do the same
6103 * by getting multimode conversion data of ADC master or ADC slave
6104 * separately).
6105 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6106 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6107 * @param ADCxy_COMMON ADC common instance
6108 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6109 * @param ConversionData This parameter can be one of the following values:
6110 * @arg @ref LL_ADC_MULTI_MASTER
6111 * @arg @ref LL_ADC_MULTI_SLAVE
6112 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6113 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6114 */
6115 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6116 {
6118 ConversionData)
6120 );
6121 }
6124 /**
6125 * @}
6126 */
6128 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6129 * @{
6130 */
6132 /**
6133 * @brief Start ADC group injected conversion.
6134 * @note On this STM32 serie, this function is relevant for both
6135 * internal trigger (SW start) and external trigger:
6136 * - If ADC trigger has been set to software start, ADC conversion
6137 * starts immediately.
6138 * - If ADC trigger has been set to external trigger, ADC conversion
6139 * will start at next trigger event (on the selected trigger edge)
6140 * following the ADC start conversion command.
6141 * @note On this STM32 serie, setting of this feature is conditioned to
6142 * ADC state:
6143 * ADC must be enabled without conversion on going on group injected,
6144 * without conversion stop command on going on group injected,
6145 * without ADC disable command on going.
6146 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6147 * @param ADCx ADC instance
6148 * @retval None
6149 */
6151 {
6152 /* Note: Write register with some additional bits forced to state reset */
6153 /* instead of modifying only the selected bit for this function, */
6154 /* to not interfere with bits with HW property "rs". */
6156 ADC_CR_BITS_PROPERTY_RS,
6157 ADC_CR_JADSTART);
6158 }
6160 /**
6161 * @brief Stop ADC group injected conversion.
6162 * @note On this STM32 serie, setting of this feature is conditioned to
6163 * ADC state:
6164 * ADC must be enabled with conversion on going on group injected,
6165 * without ADC disable command on going.
6166 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6167 * @param ADCx ADC instance
6168 * @retval None
6169 */
6171 {
6172 /* Note: Write register with some additional bits forced to state reset */
6173 /* instead of modifying only the selected bit for this function, */
6174 /* to not interfere with bits with HW property "rs". */
6176 ADC_CR_BITS_PROPERTY_RS,
6177 ADC_CR_JADSTP);
6178 }
6180 /**
6181 * @brief Get ADC group injected conversion state.
6182 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6183 * @param ADCx ADC instance
6184 * @retval 0: no conversion is on going on ADC group injected.
6185 */
6187 {
6189 }
6191 /**
6192 * @brief Get ADC group injected command of conversion stop state
6193 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6194 * @param ADCx ADC instance
6195 * @retval 0: no command of conversion stop is on going on ADC group injected.
6196 */
6198 {
6200 }
6202 /**
6203 * @brief Get ADC group regular conversion data, range fit for
6204 * all ADC configurations: all ADC resolutions and
6205 * all oversampling increased data width (for devices
6206 * with feature oversampling).
6207 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6208 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6209 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6210 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6211 * @param ADCx ADC instance
6212 * @param Rank This parameter can be one of the following values:
6213 * @arg @ref LL_ADC_INJ_RANK_1
6214 * @arg @ref LL_ADC_INJ_RANK_2
6215 * @arg @ref LL_ADC_INJ_RANK_3
6216 * @arg @ref LL_ADC_INJ_RANK_4
6217 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6218 */
6220 {
6221 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6224 ADC_JDR1_JDATA)
6225 );
6226 }
6228 /**
6229 * @brief Get ADC group injected conversion data, range fit for
6230 * ADC resolution 12 bits.
6231 * @note For devices with feature oversampling: Oversampling
6232 * can increase data width, function for extended range
6233 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6234 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6235 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6236 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6237 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6238 * @param ADCx ADC instance
6239 * @param Rank This parameter can be one of the following values:
6240 * @arg @ref LL_ADC_INJ_RANK_1
6241 * @arg @ref LL_ADC_INJ_RANK_2
6242 * @arg @ref LL_ADC_INJ_RANK_3
6243 * @arg @ref LL_ADC_INJ_RANK_4
6244 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6245 */
6247 {
6248 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6251 ADC_JDR1_JDATA)
6252 );
6253 }
6255 /**
6256 * @brief Get ADC group injected conversion data, range fit for
6257 * ADC resolution 10 bits.
6258 * @note For devices with feature oversampling: Oversampling
6259 * can increase data width, function for extended range
6260 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6261 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6262 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6263 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6264 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6265 * @param ADCx ADC instance
6266 * @param Rank This parameter can be one of the following values:
6267 * @arg @ref LL_ADC_INJ_RANK_1
6268 * @arg @ref LL_ADC_INJ_RANK_2
6269 * @arg @ref LL_ADC_INJ_RANK_3
6270 * @arg @ref LL_ADC_INJ_RANK_4
6271 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6272 */
6274 {
6275 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6278 ADC_JDR1_JDATA)
6279 );
6280 }
6282 /**
6283 * @brief Get ADC group injected conversion data, range fit for
6284 * ADC resolution 8 bits.
6285 * @note For devices with feature oversampling: Oversampling
6286 * can increase data width, function for extended range
6287 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6288 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6289 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6290 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6291 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6292 * @param ADCx ADC instance
6293 * @param Rank This parameter can be one of the following values:
6294 * @arg @ref LL_ADC_INJ_RANK_1
6295 * @arg @ref LL_ADC_INJ_RANK_2
6296 * @arg @ref LL_ADC_INJ_RANK_3
6297 * @arg @ref LL_ADC_INJ_RANK_4
6298 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6299 */
6301 {
6302 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6305 ADC_JDR1_JDATA)
6306 );
6307 }
6309 /**
6310 * @brief Get ADC group injected conversion data, range fit for
6311 * ADC resolution 6 bits.
6312 * @note For devices with feature oversampling: Oversampling
6313 * can increase data width, function for extended range
6314 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6315 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6316 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6317 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6318 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6319 * @param ADCx ADC instance
6320 * @param Rank This parameter can be one of the following values:
6321 * @arg @ref LL_ADC_INJ_RANK_1
6322 * @arg @ref LL_ADC_INJ_RANK_2
6323 * @arg @ref LL_ADC_INJ_RANK_3
6324 * @arg @ref LL_ADC_INJ_RANK_4
6325 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6326 */
6328 {
6329 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6332 ADC_JDR1_JDATA)
6333 );
6334 }
6336 /**
6337 * @}
6338 */
6340 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6341 * @{
6342 */
6344 /**
6345 * @brief Get flag ADC ready.
6346 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6347 * is enabled and when conversion clock is active.
6348 * (not only core clock: this ADC has a dual clock domain)
6349 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6350 * @param ADCx ADC instance
6351 * @retval State of bit (1 or 0).
6352 */
6354 {
6356 }
6358 /**
6359 * @brief Get flag ADC group regular end of unitary conversion.
6360 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6361 * @param ADCx ADC instance
6362 * @retval State of bit (1 or 0).
6363 */
6365 {
6367 }
6369 /**
6370 * @brief Get flag ADC group regular end of sequence conversions.
6371 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6372 * @param ADCx ADC instance
6373 * @retval State of bit (1 or 0).
6374 */
6376 {
6378 }
6380 /**
6381 * @brief Get flag ADC group regular overrun.
6382 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6383 * @param ADCx ADC instance
6384 * @retval State of bit (1 or 0).
6385 */
6387 {
6389 }
6391 /**
6392 * @brief Get flag ADC group regular end of sampling phase.
6393 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6394 * @param ADCx ADC instance
6395 * @retval State of bit (1 or 0).
6396 */
6398 {
6400 }
6402 /**
6403 * @brief Get flag ADC group injected end of unitary conversion.
6404 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6405 * @param ADCx ADC instance
6406 * @retval State of bit (1 or 0).
6407 */
6409 {
6411 }
6413 /**
6414 * @brief Get flag ADC group injected end of sequence conversions.
6415 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6416 * @param ADCx ADC instance
6417 * @retval State of bit (1 or 0).
6418 */
6420 {
6422 }
6424 /**
6425 * @brief Get flag ADC group injected contexts queue overflow.
6426 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6427 * @param ADCx ADC instance
6428 * @retval State of bit (1 or 0).
6429 */
6431 {
6433 }
6435 /**
6436 * @brief Get flag ADC analog watchdog 1 flag
6437 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6438 * @param ADCx ADC instance
6439 * @retval State of bit (1 or 0).
6440 */
6442 {
6444 }
6446 /**
6447 * @brief Get flag ADC analog watchdog 2.
6448 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6449 * @param ADCx ADC instance
6450 * @retval State of bit (1 or 0).
6451 */
6453 {
6455 }
6457 /**
6458 * @brief Get flag ADC analog watchdog 3.
6459 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6460 * @param ADCx ADC instance
6461 * @retval State of bit (1 or 0).
6462 */
6464 {
6466 }
6468 /**
6469 * @brief Clear flag ADC ready.
6470 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6471 * is enabled and when conversion clock is active.
6472 * (not only core clock: this ADC has a dual clock domain)
6473 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6474 * @param ADCx ADC instance
6475 * @retval None
6476 */
6478 {
6480 }
6482 /**
6483 * @brief Clear flag ADC group regular end of unitary conversion.
6484 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6485 * @param ADCx ADC instance
6486 * @retval None
6487 */
6489 {
6491 }
6493 /**
6494 * @brief Clear flag ADC group regular end of sequence conversions.
6495 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6496 * @param ADCx ADC instance
6497 * @retval None
6498 */
6500 {
6502 }
6504 /**
6505 * @brief Clear flag ADC group regular overrun.
6506 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6507 * @param ADCx ADC instance
6508 * @retval None
6509 */
6511 {
6513 }
6515 /**
6516 * @brief Clear flag ADC group regular end of sampling phase.
6517 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6518 * @param ADCx ADC instance
6519 * @retval None
6520 */
6522 {
6524 }
6526 /**
6527 * @brief Clear flag ADC group injected end of unitary conversion.
6528 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6529 * @param ADCx ADC instance
6530 * @retval None
6531 */
6533 {
6535 }
6537 /**
6538 * @brief Clear flag ADC group injected end of sequence conversions.
6539 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6540 * @param ADCx ADC instance
6541 * @retval None
6542 */
6544 {
6546 }
6548 /**
6549 * @brief Clear flag ADC group injected contexts queue overflow.
6550 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6551 * @param ADCx ADC instance
6552 * @retval None
6553 */
6555 {
6557 }
6559 /**
6560 * @brief Clear flag ADC analog watchdog 1.
6561 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6562 * @param ADCx ADC instance
6563 * @retval None
6564 */
6566 {
6568 }
6570 /**
6571 * @brief Clear flag ADC analog watchdog 2.
6572 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6573 * @param ADCx ADC instance
6574 * @retval None
6575 */
6577 {
6579 }
6581 /**
6582 * @brief Clear flag ADC analog watchdog 3.
6583 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6584 * @param ADCx ADC instance
6585 * @retval None
6586 */
6588 {
6590 }
6592 #if defined(ADC_MULTIMODE_SUPPORT)
6593 /**
6594 * @brief Get flag multimode ADC ready of the ADC master.
6595 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6596 * @param ADCxy_COMMON ADC common instance
6597 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6598 * @retval State of bit (1 or 0).
6599 */
6601 {
6603 }
6605 /**
6606 * @brief Get flag multimode ADC ready of the ADC slave.
6607 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6608 * @param ADCxy_COMMON ADC common instance
6609 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6610 * @retval State of bit (1 or 0).
6611 */
6613 {
6615 }
6617 /**
6618 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6619 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6620 * @param ADCxy_COMMON ADC common instance
6621 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6622 * @retval State of bit (1 or 0).
6623 */
6625 {
6627 }
6629 /**
6630 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6631 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6632 * @param ADCxy_COMMON ADC common instance
6633 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6634 * @retval State of bit (1 or 0).
6635 */
6637 {
6639 }
6641 /**
6642 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6643 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6644 * @param ADCxy_COMMON ADC common instance
6645 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6646 * @retval State of bit (1 or 0).
6647 */
6649 {
6651 }
6653 /**
6654 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6655 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6656 * @param ADCxy_COMMON ADC common instance
6657 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6658 * @retval State of bit (1 or 0).
6659 */
6661 {
6663 }
6665 /**
6666 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6667 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6668 * @param ADCxy_COMMON ADC common instance
6669 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6670 * @retval State of bit (1 or 0).
6671 */
6673 {
6675 }
6677 /**
6678 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6679 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6680 * @param ADCxy_COMMON ADC common instance
6681 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6682 * @retval State of bit (1 or 0).
6683 */
6685 {
6687 }
6689 /**
6690 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6691 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6692 * @param ADCxy_COMMON ADC common instance
6693 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6694 * @retval State of bit (1 or 0).
6695 */
6697 {
6699 }
6701 /**
6702 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6703 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6704 * @param ADCxy_COMMON ADC common instance
6705 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6706 * @retval State of bit (1 or 0).
6707 */
6709 {
6711 }
6713 /**
6714 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6715 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6716 * @param ADCxy_COMMON ADC common instance
6717 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6718 * @retval State of bit (1 or 0).
6719 */
6721 {
6723 }
6725 /**
6726 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6727 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6728 * @param ADCxy_COMMON ADC common instance
6729 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6730 * @retval State of bit (1 or 0).
6731 */
6733 {
6735 }
6737 /**
6738 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6739 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6740 * @param ADCxy_COMMON ADC common instance
6741 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6742 * @retval State of bit (1 or 0).
6743 */
6745 {
6747 }
6749 /**
6750 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6751 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6752 * @param ADCxy_COMMON ADC common instance
6753 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6754 * @retval State of bit (1 or 0).
6755 */
6757 {
6759 }
6761 /**
6762 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6763 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6764 * @param ADCxy_COMMON ADC common instance
6765 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6766 * @retval State of bit (1 or 0).
6767 */
6769 {
6771 }
6773 /**
6774 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6775 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6776 * @param ADCxy_COMMON ADC common instance
6777 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6778 * @retval State of bit (1 or 0).
6779 */
6781 {
6783 }
6785 /**
6786 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6787 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6788 * @param ADCxy_COMMON ADC common instance
6789 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6790 * @retval State of bit (1 or 0).
6791 */
6793 {
6795 }
6797 /**
6798 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6799 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6800 * @param ADCxy_COMMON ADC common instance
6801 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6802 * @retval State of bit (1 or 0).
6803 */
6805 {
6807 }
6809 /**
6810 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6811 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6812 * @param ADCxy_COMMON ADC common instance
6813 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6814 * @retval State of bit (1 or 0).
6815 */
6817 {
6819 }
6821 /**
6822 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6823 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6824 * @param ADCxy_COMMON ADC common instance
6825 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6826 * @retval State of bit (1 or 0).
6827 */
6829 {
6831 }
6833 /**
6834 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
6835 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
6836 * @param ADCxy_COMMON ADC common instance
6837 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6838 * @retval State of bit (1 or 0).
6839 */
6841 {
6843 }
6845 /**
6846 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
6847 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
6848 * @param ADCxy_COMMON ADC common instance
6849 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6850 * @retval State of bit (1 or 0).
6851 */
6853 {
6855 }
6858 /**
6859 * @}
6860 */
6862 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
6863 * @{
6864 */
6866 /**
6867 * @brief Enable ADC ready.
6868 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
6869 * @param ADCx ADC instance
6870 * @retval None
6871 */
6873 {
6875 }
6877 /**
6878 * @brief Enable interruption ADC group regular end of unitary conversion.
6879 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
6880 * @param ADCx ADC instance
6881 * @retval None
6882 */
6884 {
6886 }
6888 /**
6889 * @brief Enable interruption ADC group regular end of sequence conversions.
6890 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
6891 * @param ADCx ADC instance
6892 * @retval None
6893 */
6895 {
6897 }
6899 /**
6900 * @brief Enable ADC group regular interruption overrun.
6901 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
6902 * @param ADCx ADC instance
6903 * @retval None
6904 */
6906 {
6908 }
6910 /**
6911 * @brief Enable interruption ADC group regular end of sampling.
6912 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
6913 * @param ADCx ADC instance
6914 * @retval None
6915 */
6917 {
6919 }
6921 /**
6922 * @brief Enable interruption ADC group injected end of unitary conversion.
6923 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
6924 * @param ADCx ADC instance
6925 * @retval None
6926 */
6928 {
6930 }
6932 /**
6933 * @brief Enable interruption ADC group injected end of sequence conversions.
6934 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
6935 * @param ADCx ADC instance
6936 * @retval None
6937 */
6939 {
6941 }
6943 /**
6944 * @brief Enable interruption ADC group injected context queue overflow.
6945 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
6946 * @param ADCx ADC instance
6947 * @retval None
6948 */
6950 {
6952 }
6954 /**
6955 * @brief Enable interruption ADC analog watchdog 1.
6956 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
6957 * @param ADCx ADC instance
6958 * @retval None
6959 */
6961 {
6963 }
6965 /**
6966 * @brief Enable interruption ADC analog watchdog 2.
6967 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
6968 * @param ADCx ADC instance
6969 * @retval None
6970 */
6972 {
6974 }
6976 /**
6977 * @brief Enable interruption ADC analog watchdog 3.
6978 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
6979 * @param ADCx ADC instance
6980 * @retval None
6981 */
6983 {
6985 }
6987 /**
6988 * @brief Disable interruption ADC ready.
6989 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
6990 * @param ADCx ADC instance
6991 * @retval None
6992 */
6994 {
6996 }
6998 /**
6999 * @brief Disable interruption ADC group regular end of unitary conversion.
7000 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7001 * @param ADCx ADC instance
7002 * @retval None
7003 */
7005 {
7007 }
7009 /**
7010 * @brief Disable interruption ADC group regular end of sequence conversions.
7011 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7012 * @param ADCx ADC instance
7013 * @retval None
7014 */
7016 {
7018 }
7020 /**
7021 * @brief Disable interruption ADC group regular overrun.
7022 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7023 * @param ADCx ADC instance
7024 * @retval None
7025 */
7027 {
7029 }
7031 /**
7032 * @brief Disable interruption ADC group regular end of sampling.
7033 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7034 * @param ADCx ADC instance
7035 * @retval None
7036 */
7038 {
7040 }
7042 /**
7043 * @brief Disable interruption ADC group regular end of unitary conversion.
7044 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7045 * @param ADCx ADC instance
7046 * @retval None
7047 */
7049 {
7051 }
7053 /**
7054 * @brief Disable interruption ADC group injected end of sequence conversions.
7055 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7056 * @param ADCx ADC instance
7057 * @retval None
7058 */
7060 {
7062 }
7064 /**
7065 * @brief Disable interruption ADC group injected context queue overflow.
7066 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7067 * @param ADCx ADC instance
7068 * @retval None
7069 */
7071 {
7073 }
7075 /**
7076 * @brief Disable interruption ADC analog watchdog 1.
7077 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7078 * @param ADCx ADC instance
7079 * @retval None
7080 */
7082 {
7084 }
7086 /**
7087 * @brief Disable interruption ADC analog watchdog 2.
7088 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7089 * @param ADCx ADC instance
7090 * @retval None
7091 */
7093 {
7095 }
7097 /**
7098 * @brief Disable interruption ADC analog watchdog 3.
7099 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7100 * @param ADCx ADC instance
7101 * @retval None
7102 */
7104 {
7106 }
7108 /**
7109 * @brief Get state of interruption ADC ready
7110 * (0: interrupt disabled, 1: interrupt enabled).
7111 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7112 * @param ADCx ADC instance
7113 * @retval State of bit (1 or 0).
7114 */
7116 {
7118 }
7120 /**
7121 * @brief Get state of interruption ADC group regular end of unitary conversion
7122 * (0: interrupt disabled, 1: interrupt enabled).
7123 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7124 * @param ADCx ADC instance
7125 * @retval State of bit (1 or 0).
7126 */
7128 {
7130 }
7132 /**
7133 * @brief Get state of interruption ADC group regular end of sequence conversions
7134 * (0: interrupt disabled, 1: interrupt enabled).
7135 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7136 * @param ADCx ADC instance
7137 * @retval State of bit (1 or 0).
7138 */
7140 {
7142 }
7144 /**
7145 * @brief Get state of interruption ADC group regular overrun
7146 * (0: interrupt disabled, 1: interrupt enabled).
7147 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7148 * @param ADCx ADC instance
7149 * @retval State of bit (1 or 0).
7150 */
7152 {
7154 }
7156 /**
7157 * @brief Get state of interruption ADC group regular end of sampling
7158 * (0: interrupt disabled, 1: interrupt enabled).
7159 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7160 * @param ADCx ADC instance
7161 * @retval State of bit (1 or 0).
7162 */
7164 {
7166 }
7168 /**
7169 * @brief Get state of interruption ADC group injected end of unitary conversion
7170 * (0: interrupt disabled, 1: interrupt enabled).
7171 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7172 * @param ADCx ADC instance
7173 * @retval State of bit (1 or 0).
7174 */
7176 {
7178 }
7180 /**
7181 * @brief Get state of interruption ADC group injected end of sequence conversions
7182 * (0: interrupt disabled, 1: interrupt enabled).
7183 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7184 * @param ADCx ADC instance
7185 * @retval State of bit (1 or 0).
7186 */
7188 {
7190 }
7192 /**
7193 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7194 * (0: interrupt disabled, 1: interrupt enabled).
7195 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7196 * @param ADCx ADC instance
7197 * @retval State of bit (1 or 0).
7198 */
7200 {
7202 }
7204 /**
7205 * @brief Get state of interruption ADC analog watchdog 1
7206 * (0: interrupt disabled, 1: interrupt enabled).
7207 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7208 * @param ADCx ADC instance
7209 * @retval State of bit (1 or 0).
7210 */
7212 {
7214 }
7216 /**
7217 * @brief Get state of interruption Get ADC analog watchdog 2
7218 * (0: interrupt disabled, 1: interrupt enabled).
7219 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7220 * @param ADCx ADC instance
7221 * @retval State of bit (1 or 0).
7222 */
7224 {
7226 }
7228 /**
7229 * @brief Get state of interruption Get ADC analog watchdog 3
7230 * (0: interrupt disabled, 1: interrupt enabled).
7231 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7232 * @param ADCx ADC instance
7233 * @retval State of bit (1 or 0).
7234 */
7236 {
7238 }
7240 /**
7241 * @}
7242 */
7244 #if defined(USE_FULL_LL_DRIVER)
7245 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7246 * @{
7247 */
7249 /* Initialization of some features of ADC common parameters and multimode */
7251 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7254 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7255 /* (availability of ADC group injected depends on STM32 families) */
7258 /* Initialization of some features of ADC instance */
7262 /* Initialization of some features of ADC instance and ADC group regular */
7266 /* Initialization of some features of ADC instance and ADC group injected */
7270 /**
7271 * @}
7272 */
7275 /**
7276 * @}
7277 */
7279 /**
7280 * @}
7281 */
7286 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
7288 #if defined (ADC1_V2_5)
7290 #if defined (ADC1)
7292 /** @defgroup ADC_LL ADC
7293 * @{
7294 */
7296 /* Private types -------------------------------------------------------------*/
7297 /* Private variables ---------------------------------------------------------*/
7299 /* Private constants ---------------------------------------------------------*/
7300 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
7301 * @{
7302 */
7304 /* Internal mask for ADC group regular sequencer: */
7305 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
7306 /* - sequencer register offset */
7307 /* - sequencer rank bits position into the selected register */
7309 /* Internal register offset for ADC group regular sequencer configuration */
7310 /* (offset placed into a spare area of literal definition) */
7311 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
7312 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
7313 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
7314 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
7316 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
7317 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
7319 /* Definition of ADC group regular sequencer bits information to be inserted */
7320 /* into ADC group regular sequencer ranks literals definition. */
7321 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
7322 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
7323 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
7324 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
7325 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
7326 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
7327 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
7328 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
7329 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
7330 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
7331 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
7332 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
7333 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
7334 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
7335 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
7336 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
7340 /* Internal mask for ADC group injected sequencer: */
7341 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
7342 /* - data register offset */
7343 /* - offset register offset */
7344 /* - sequencer rank bits position into the selected register */
7346 /* Internal register offset for ADC group injected data register */
7347 /* (offset placed into a spare area of literal definition) */
7348 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
7349 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
7350 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
7351 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
7353 /* Internal register offset for ADC group injected offset configuration */
7354 /* (offset placed into a spare area of literal definition) */
7355 #define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
7356 #define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
7357 #define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
7358 #define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
7360 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
7361 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
7362 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
7364 /* Definition of ADC group injected sequencer bits information to be inserted */
7365 /* into ADC group injected sequencer ranks literals definition. */
7366 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
7367 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
7368 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
7369 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
7373 /* Internal mask for ADC channel: */
7374 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
7375 /* - channel identifier defined by number */
7376 /* - channel differentiation between external channels (connected to */
7377 /* GPIO pins) and internal channels (connected to internal paths) */
7378 /* - channel sampling time defined by SMPRx register offset */
7379 /* and SMPx bits positions into SMPRx register */
7380 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
7381 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
7382 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
7383 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
7384 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
7386 /* Channel differentiation between external and internal channels */
7388 #define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
7389 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
7391 /* Internal register offset for ADC channel sampling time configuration */
7392 /* (offset placed into a spare area of literal definition) */
7393 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
7394 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
7395 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
7397 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
7398 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
7400 /* Definition of channels ID number information to be inserted into */
7401 /* channels literals definition. */
7402 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
7403 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
7404 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
7405 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7406 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
7407 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
7408 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
7409 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7410 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
7411 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
7412 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
7413 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7414 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
7415 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
7416 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
7417 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7418 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
7419 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
7421 /* Definition of channels sampling time information to be inserted into */
7422 /* channels literals definition. */
7423 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
7424 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
7425 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
7426 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
7427 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
7428 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
7429 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
7430 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
7431 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
7432 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
7433 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
7434 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
7435 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
7436 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
7437 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
7438 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
7439 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
7440 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
7443 /* Internal mask for ADC analog watchdog: */
7444 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
7445 /* (concatenation of multiple bits used in different analog watchdogs, */
7446 /* (feature of several watchdogs not available on all STM32 families)). */
7447 /* - analog watchdog 1: monitored channel defined by number, */
7448 /* selection of ADC group (ADC groups regular and-or injected). */
7450 /* Internal register offset for ADC analog watchdog channel configuration */
7451 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
7453 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
7455 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
7456 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
7458 /* Internal register offset for ADC analog watchdog threshold configuration */
7459 #define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
7460 #define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
7461 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
7464 /* ADC registers bits positions */
7465 #define ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
7468 /* ADC internal channels related definitions */
7469 /* Internal voltage reference VrefInt */
7470 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7471 #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
7472 /* Temperature sensor */
7473 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7474 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7475 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
7476 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
7477 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
7480 /**
7481 * @}
7482 */
7485 /* Private macros ------------------------------------------------------------*/
7486 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
7487 * @{
7488 */
7490 /**
7491 * @brief Driver macro reserved for internal use: isolate bits with the
7492 * selected mask and shift them to the register LSB
7493 * (shift mask on register position bit 0).
7494 * @param __BITS__ Bits in register 32 bits
7495 * @param __MASK__ Mask in register 32 bits
7496 * @retval Bits in register 32 bits
7497 */
7498 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
7499 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
7501 /**
7502 * @brief Driver macro reserved for internal use: set a pointer to
7503 * a register from a register basis from which an offset
7504 * is applied.
7505 * @param __REG__ Register basis from which the offset is applied.
7506 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
7507 * @retval Pointer to register address
7508 */
7509 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
7510 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
7512 /**
7513 * @}
7514 */
7517 /* Exported types ------------------------------------------------------------*/
7518 #if defined(USE_FULL_LL_DRIVER)
7519 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
7520 * @{
7521 */
7523 /**
7524 * @brief Structure definition of some features of ADC instance.
7525 * @note These parameters have an impact on ADC scope: ADC instance.
7526 * Affects both group regular and group injected (availability
7527 * of ADC group injected depends on STM32 families).
7528 * Refer to corresponding unitary functions into
7529 * @ref ADC_LL_EF_Configuration_ADC_Instance .
7530 * @note The setting of these parameters by function @ref LL_ADC_Init()
7531 * is conditioned to ADC state:
7532 * ADC instance must be disabled.
7533 * This condition is applied to all ADC features, for efficiency
7534 * and compatibility over all STM32 families. However, the different
7535 * features can be set under different ADC state conditions
7536 * (setting possible with ADC enabled without conversion on going,
7537 * ADC enabled with conversion on going, ...)
7538 * Each feature can be updated afterwards with a unitary function
7539 * and potentially with ADC in a different state than disabled,
7540 * refer to description of each function for setting
7541 * conditioned to ADC state.
7542 */
7544 {
7546 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
7548 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
7551 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
7553 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
7557 /**
7558 * @brief Structure definition of some features of ADC group regular.
7559 * @note These parameters have an impact on ADC scope: ADC group regular.
7560 * Refer to corresponding unitary functions into
7561 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
7562 * (functions with prefix "REG").
7563 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
7564 * is conditioned to ADC state:
7565 * ADC instance must be disabled.
7566 * This condition is applied to all ADC features, for efficiency
7567 * and compatibility over all STM32 families. However, the different
7568 * features can be set under different ADC state conditions
7569 * (setting possible with ADC enabled without conversion on going,
7570 * ADC enabled with conversion on going, ...)
7571 * Each feature can be updated afterwards with a unitary function
7572 * and potentially with ADC in a different state than disabled,
7573 * refer to description of each function for setting
7574 * conditioned to ADC state.
7575 */
7577 {
7578 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
7579 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
7580 @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
7581 (only trigger polarity available on this STM32 serie).
7583 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
7586 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
7587 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
7589 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
7591 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
7592 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
7593 @note This parameter has an effect only if group regular sequencer is enabled
7594 (scan length of 2 ranks or more).
7596 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
7598 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
7599 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
7600 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
7602 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
7604 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
7605 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
7607 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
7611 /**
7612 * @brief Structure definition of some features of ADC group injected.
7613 * @note These parameters have an impact on ADC scope: ADC group injected.
7614 * Refer to corresponding unitary functions into
7615 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
7616 * (functions with prefix "INJ").
7617 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
7618 * is conditioned to ADC state:
7619 * ADC instance must be disabled.
7620 * This condition is applied to all ADC features, for efficiency
7621 * and compatibility over all STM32 families. However, the different
7622 * features can be set under different ADC state conditions
7623 * (setting possible with ADC enabled without conversion on going,
7624 * ADC enabled with conversion on going, ...)
7625 * Each feature can be updated afterwards with a unitary function
7626 * and potentially with ADC in a different state than disabled,
7627 * refer to description of each function for setting
7628 * conditioned to ADC state.
7629 */
7631 {
7632 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
7633 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
7634 @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
7635 (only trigger polarity available on this STM32 serie).
7637 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
7640 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
7641 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
7643 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
7645 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
7646 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
7647 @note This parameter has an effect only if group injected sequencer is enabled
7648 (scan length of 2 ranks or more).
7650 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
7652 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
7653 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
7654 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
7656 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
7660 /**
7661 * @}
7662 */
7665 /* Exported constants --------------------------------------------------------*/
7666 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
7667 * @{
7668 */
7670 /** @defgroup ADC_LL_EC_FLAG ADC flags
7671 * @brief Flags defines which can be used with LL_ADC_ReadReg function
7672 * @{
7673 */
7675 #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
7677 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
7679 /**
7680 * @}
7681 */
7683 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
7684 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
7685 * @{
7686 */
7687 #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
7688 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
7690 /**
7691 * @}
7692 */
7694 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
7695 * @{
7696 */
7697 /* List of ADC registers intended to be used (most commonly) with */
7698 /* DMA transfer. */
7699 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
7700 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
7701 /**
7702 * @}
7703 */
7705 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
7706 * @{
7707 */
7708 /* Note: Other measurement paths to internal channels may be available */
7709 /* (connections to other peripherals). */
7710 /* If they are not listed below, they do not require any specific */
7711 /* path enable. In this case, Access to measurement path is done */
7712 /* only by selecting the corresponding ADC internal channel. */
7713 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
7714 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
7715 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
7716 /**
7717 * @}
7718 */
7720 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
7721 * @{
7722 */
7724 /**
7725 * @}
7726 */
7728 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
7729 * @{
7730 */
7731 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
7732 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
7733 /**
7734 * @}
7735 */
7737 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
7738 * @{
7739 */
7740 #define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
7741 #define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
7742 /**
7743 * @}
7744 */
7746 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
7747 * @{
7748 */
7749 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
7750 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
7751 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
7752 /**
7753 * @}
7754 */
7756 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
7757 * @{
7758 */
7759 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
7760 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
7761 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
7762 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
7763 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
7764 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
7765 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
7766 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
7767 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
7768 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
7769 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
7770 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
7771 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
7772 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
7773 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
7774 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
7775 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
7776 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
7777 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1. */
7778 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
7779 /**
7780 * @}
7781 */
7783 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
7784 * @{
7785 */
7786 #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal (SW start) */
7787 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
7788 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
7789 #define LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
7790 #define LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting). */
7791 #define LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting). */
7792 #define LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting). */
7793 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
7794 /**
7795 * @}
7796 */
7798 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
7799 * @{
7800 */
7801 #define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger polarity set to rising edge */
7802 /**
7803 * @}
7804 */
7806 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
7807 * @{
7808 */
7809 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)/*!< ADC conversions are performed in single mode: one conversion per trigger */
7810 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
7811 /**
7812 * @}
7813 */
7815 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer
7816 * @{
7817 */
7818 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
7819 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
7820 /**
7821 * @}
7822 */
7824 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
7825 * @{
7826 */
7827 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
7828 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
7829 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
7830 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
7831 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
7832 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
7833 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
7834 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
7835 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
7836 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
7837 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
7838 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
7839 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
7840 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
7841 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
7842 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
7843 /**
7844 * @}
7845 */
7847 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
7848 * @{
7849 */
7850 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
7851 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
7852 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
7853 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
7854 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
7855 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
7856 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
7857 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
7858 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
7859 /**
7860 * @}
7861 */
7863 /** @defgroup ADC_LL_EC_REG_RANKS ADC group regular - Sequencer ranks
7864 * @{
7865 */
7866 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
7867 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
7868 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
7869 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
7870 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
7871 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
7872 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
7873 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
7874 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
7875 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
7876 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
7877 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
7878 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
7879 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
7880 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
7881 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
7882 /**
7883 * @}
7884 */
7886 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
7887 * @{
7888 */
7889 #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal (SW start) */
7890 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
7891 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
7892 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
7893 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
7894 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting). */
7895 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting). */
7896 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
7897 /**
7898 * @}
7899 */
7901 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
7902 * @{
7903 */
7904 #define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger polarity set to rising edge */
7905 /**
7906 * @}
7907 */
7909 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
7910 * @{
7911 */
7912 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
7913 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
7914 /**
7915 * @}
7916 */
7919 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
7920 * @{
7921 */
7922 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
7923 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
7924 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
7925 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
7926 /**
7927 * @}
7928 */
7930 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
7931 * @{
7932 */
7933 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
7934 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
7935 /**
7936 * @}
7937 */
7939 /** @defgroup ADC_LL_EC_INJ_RANKS ADC group injected - Sequencer ranks
7940 * @{
7941 */
7942 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
7943 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
7944 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
7945 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
7946 /**
7947 * @}
7948 */
7950 /** @defgroup ADC_LL_EC_SAMPLINGTIME Channel - Sampling time
7951 * @{
7952 */
7953 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
7954 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
7955 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
7956 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
7957 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
7958 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
7959 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
7960 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
7961 /**
7962 * @}
7963 */
7965 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
7966 * @{
7967 */
7968 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
7969 /**
7970 * @}
7971 */
7973 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
7974 * @{
7975 */
7976 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
7977 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
7978 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
7979 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
7980 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
7981 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
7982 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
7983 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
7984 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
7985 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
7986 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
7987 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
7988 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
7989 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
7990 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
7991 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
7992 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
7993 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
7994 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
7995 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
7996 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
7997 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
7998 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
7999 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
8000 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
8001 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
8002 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
8003 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
8004 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
8005 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
8006 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
8007 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
8008 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
8009 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
8010 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
8011 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
8012 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
8013 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
8014 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
8015 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
8016 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
8017 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
8018 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
8019 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
8020 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
8021 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
8022 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
8023 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
8024 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
8025 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
8026 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
8027 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
8028 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
8029 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
8030 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
8031 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
8032 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
8033 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
8034 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
8035 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
8036 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
8037 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
8038 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
8039 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
8040 /**
8041 * @}
8042 */
8044 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
8045 * @{
8046 */
8047 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
8048 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
8049 /**
8050 * @}
8051 */
8054 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
8055 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
8056 * not timeout values.
8057 * For details on delays values, refer to descriptions in source code
8058 * above each literal definition.
8059 * @{
8060 */
8062 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
8063 /* not timeout values. */
8064 /* Timeout values for ADC operations are dependent to device clock */
8065 /* configuration (system clock versus ADC clock), */
8066 /* and therefore must be defined in user application. */
8067 /* Indications for estimation of ADC timeout delays, for this */
8068 /* STM32 serie: */
8069 /* - ADC enable time: maximum delay is 1us */
8070 /* (refer to device datasheet, parameter "tSTAB") */
8071 /* - ADC conversion time: duration depending on ADC clock and ADC */
8072 /* configuration. */
8073 /* (refer to device reference manual, section "Timing") */
8075 /* Delay for temperature sensor stabilization time. */
8076 /* Literal set to maximum value (refer to device datasheet, */
8077 /* parameter "tSTART"). */
8078 /* Unit: us */
8079 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
8081 /* Delay required between ADC disable and ADC calibration start. */
8082 /* Note: On this STM32 serie, before starting a calibration, */
8083 /* ADC must be disabled. */
8084 /* A minimum number of ADC clock cycles are required */
8085 /* between ADC disable state and calibration start. */
8086 /* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */
8087 /* Wait time can be computed in user application by waiting for the */
8088 /* equivalent number of CPU cycles, by taking into account */
8089 /* ratio of CPU clock versus ADC clock prescalers. */
8090 /* Unit: ADC clock cycles. */
8091 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC disable and ADC calibration start */
8093 /**
8094 * @}
8095 */
8097 /**
8098 * @}
8099 */
8102 /* Exported macro ------------------------------------------------------------*/
8103 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
8104 * @{
8105 */
8107 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
8108 * @{
8109 */
8111 /**
8112 * @brief Write a value in ADC register
8113 * @param __INSTANCE__ ADC Instance
8114 * @param __REG__ Register to be written
8115 * @param __VALUE__ Value to be written in the register
8116 * @retval None
8117 */
8118 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
8120 /**
8121 * @brief Read a value in ADC register
8122 * @param __INSTANCE__ ADC Instance
8123 * @param __REG__ Register to be read
8124 * @retval Register value
8125 */
8126 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
8127 /**
8128 * @}
8129 */
8131 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
8132 * @{
8133 */
8135 /**
8136 * @brief Helper macro to get ADC channel number in decimal format
8137 * from literals LL_ADC_CHANNEL_x.
8138 * @note Example:
8139 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
8140 * will return decimal number "4".
8141 * @note The input can be a value from functions where a channel
8142 * number is returned, either defined with number
8143 * or with bitfield (only one bit must be set).
8144 * @param __CHANNEL__ This parameter can be one of the following values:
8145 * @arg @ref LL_ADC_CHANNEL_0
8146 * @arg @ref LL_ADC_CHANNEL_1
8147 * @arg @ref LL_ADC_CHANNEL_2
8148 * @arg @ref LL_ADC_CHANNEL_3
8149 * @arg @ref LL_ADC_CHANNEL_4
8150 * @arg @ref LL_ADC_CHANNEL_5
8151 * @arg @ref LL_ADC_CHANNEL_6
8152 * @arg @ref LL_ADC_CHANNEL_7
8153 * @arg @ref LL_ADC_CHANNEL_8
8154 * @arg @ref LL_ADC_CHANNEL_9
8155 * @arg @ref LL_ADC_CHANNEL_10
8156 * @arg @ref LL_ADC_CHANNEL_11
8157 * @arg @ref LL_ADC_CHANNEL_12
8158 * @arg @ref LL_ADC_CHANNEL_13
8159 * @arg @ref LL_ADC_CHANNEL_14
8160 * @arg @ref LL_ADC_CHANNEL_15
8161 * @arg @ref LL_ADC_CHANNEL_16
8162 * @arg @ref LL_ADC_CHANNEL_17
8163 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8164 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8165 *
8166 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8167 * @retval Value between Min_Data=0 and Max_Data=18
8168 */
8169 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
8170 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
8172 /**
8173 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
8174 * from number in decimal format.
8175 * @note Example:
8176 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
8177 * will return a data equivalent to "LL_ADC_CHANNEL_4".
8178 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
8179 * @retval Returned value can be one of the following values:
8180 * @arg @ref LL_ADC_CHANNEL_0
8181 * @arg @ref LL_ADC_CHANNEL_1
8182 * @arg @ref LL_ADC_CHANNEL_2
8183 * @arg @ref LL_ADC_CHANNEL_3
8184 * @arg @ref LL_ADC_CHANNEL_4
8185 * @arg @ref LL_ADC_CHANNEL_5
8186 * @arg @ref LL_ADC_CHANNEL_6
8187 * @arg @ref LL_ADC_CHANNEL_7
8188 * @arg @ref LL_ADC_CHANNEL_8
8189 * @arg @ref LL_ADC_CHANNEL_9
8190 * @arg @ref LL_ADC_CHANNEL_10
8191 * @arg @ref LL_ADC_CHANNEL_11
8192 * @arg @ref LL_ADC_CHANNEL_12
8193 * @arg @ref LL_ADC_CHANNEL_13
8194 * @arg @ref LL_ADC_CHANNEL_14
8195 * @arg @ref LL_ADC_CHANNEL_15
8196 * @arg @ref LL_ADC_CHANNEL_16
8197 * @arg @ref LL_ADC_CHANNEL_17
8198 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8199 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8200 *
8201 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
8202 * (1) For ADC channel read back from ADC register,
8203 * comparison with internal channel parameter to be done
8204 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
8205 */
8206 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
8207 (((__DECIMAL_NB__) <= 9U) \
8208 ? ( \
8209 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
8210 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
8211 ) \
8212 : \
8213 ( \
8214 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
8215 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
8216 ) \
8217 )
8219 /**
8220 * @brief Helper macro to determine whether the selected channel
8221 * corresponds to literal definitions of driver.
8222 * @note The different literal definitions of ADC channels are:
8223 * - ADC internal channel:
8224 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
8225 * - ADC external channel (channel connected to a GPIO pin):
8226 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
8227 * @note The channel parameter must be a value defined from literal
8228 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8229 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8230 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
8231 * must not be a value from functions where a channel number is
8232 * returned from ADC registers,
8233 * because internal and external channels share the same channel
8234 * number in ADC registers. The differentiation is made only with
8235 * parameters definitions of driver.
8236 * @param __CHANNEL__ This parameter can be one of the following values:
8237 * @arg @ref LL_ADC_CHANNEL_0
8238 * @arg @ref LL_ADC_CHANNEL_1
8239 * @arg @ref LL_ADC_CHANNEL_2
8240 * @arg @ref LL_ADC_CHANNEL_3
8241 * @arg @ref LL_ADC_CHANNEL_4
8242 * @arg @ref LL_ADC_CHANNEL_5
8243 * @arg @ref LL_ADC_CHANNEL_6
8244 * @arg @ref LL_ADC_CHANNEL_7
8245 * @arg @ref LL_ADC_CHANNEL_8
8246 * @arg @ref LL_ADC_CHANNEL_9
8247 * @arg @ref LL_ADC_CHANNEL_10
8248 * @arg @ref LL_ADC_CHANNEL_11
8249 * @arg @ref LL_ADC_CHANNEL_12
8250 * @arg @ref LL_ADC_CHANNEL_13
8251 * @arg @ref LL_ADC_CHANNEL_14
8252 * @arg @ref LL_ADC_CHANNEL_15
8253 * @arg @ref LL_ADC_CHANNEL_16
8254 * @arg @ref LL_ADC_CHANNEL_17
8255 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8256 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8257 *
8258 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8259 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
8260 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel
8261 */
8262 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
8263 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
8265 /**
8266 * @brief Helper macro to convert a channel defined from parameter
8267 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8268 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8269 * to its equivalent parameter definition of a ADC external channel
8270 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
8271 * @note The channel parameter can be, additionally to a value
8272 * defined from parameter definition of a ADC internal channel
8273 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
8274 * a value defined from parameter definition of
8275 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
8276 * or a value from functions where a channel number is returned
8277 * from ADC registers.
8278 * @param __CHANNEL__ This parameter can be one of the following values:
8279 * @arg @ref LL_ADC_CHANNEL_0
8280 * @arg @ref LL_ADC_CHANNEL_1
8281 * @arg @ref LL_ADC_CHANNEL_2
8282 * @arg @ref LL_ADC_CHANNEL_3
8283 * @arg @ref LL_ADC_CHANNEL_4
8284 * @arg @ref LL_ADC_CHANNEL_5
8285 * @arg @ref LL_ADC_CHANNEL_6
8286 * @arg @ref LL_ADC_CHANNEL_7
8287 * @arg @ref LL_ADC_CHANNEL_8
8288 * @arg @ref LL_ADC_CHANNEL_9
8289 * @arg @ref LL_ADC_CHANNEL_10
8290 * @arg @ref LL_ADC_CHANNEL_11
8291 * @arg @ref LL_ADC_CHANNEL_12
8292 * @arg @ref LL_ADC_CHANNEL_13
8293 * @arg @ref LL_ADC_CHANNEL_14
8294 * @arg @ref LL_ADC_CHANNEL_15
8295 * @arg @ref LL_ADC_CHANNEL_16
8296 * @arg @ref LL_ADC_CHANNEL_17
8297 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8298 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8299 *
8300 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8301 * @retval Returned value can be one of the following values:
8302 * @arg @ref LL_ADC_CHANNEL_0
8303 * @arg @ref LL_ADC_CHANNEL_1
8304 * @arg @ref LL_ADC_CHANNEL_2
8305 * @arg @ref LL_ADC_CHANNEL_3
8306 * @arg @ref LL_ADC_CHANNEL_4
8307 * @arg @ref LL_ADC_CHANNEL_5
8308 * @arg @ref LL_ADC_CHANNEL_6
8309 * @arg @ref LL_ADC_CHANNEL_7
8310 * @arg @ref LL_ADC_CHANNEL_8
8311 * @arg @ref LL_ADC_CHANNEL_9
8312 * @arg @ref LL_ADC_CHANNEL_10
8313 * @arg @ref LL_ADC_CHANNEL_11
8314 * @arg @ref LL_ADC_CHANNEL_12
8315 * @arg @ref LL_ADC_CHANNEL_13
8316 * @arg @ref LL_ADC_CHANNEL_14
8317 * @arg @ref LL_ADC_CHANNEL_15
8318 * @arg @ref LL_ADC_CHANNEL_16
8319 * @arg @ref LL_ADC_CHANNEL_17
8320 */
8321 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
8322 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
8324 /**
8325 * @brief Helper macro to determine whether the internal channel
8326 * selected is available on the ADC instance selected.
8327 * @note The channel parameter must be a value defined from parameter
8328 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8329 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8330 * must not be a value defined from parameter definition of
8331 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
8332 * or a value from functions where a channel number is
8333 * returned from ADC registers,
8334 * because internal and external channels share the same channel
8335 * number in ADC registers. The differentiation is made only with
8336 * parameters definitions of driver.
8337 * @param __ADC_INSTANCE__ ADC instance
8338 * @param __CHANNEL__ This parameter can be one of the following values:
8339 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8340 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8341 *
8342 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8343 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
8344 * Value "1" if the internal channel selected is available on the ADC instance selected.
8345 */
8346 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
8347 (((__ADC_INSTANCE__) == ADC1) \
8348 ? ( \
8349 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
8350 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
8351 ) \
8352 : \
8353 (0U) \
8354 )
8356 /**
8357 * @brief Helper macro to define ADC analog watchdog parameter:
8358 * define a single channel to monitor with analog watchdog
8359 * from sequencer channel and groups definition.
8360 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
8361 * Example:
8362 * LL_ADC_SetAnalogWDMonitChannels(
8363 * ADC1, LL_ADC_AWD1,
8364 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
8365 * @param __CHANNEL__ This parameter can be one of the following values:
8366 * @arg @ref LL_ADC_CHANNEL_0
8367 * @arg @ref LL_ADC_CHANNEL_1
8368 * @arg @ref LL_ADC_CHANNEL_2
8369 * @arg @ref LL_ADC_CHANNEL_3
8370 * @arg @ref LL_ADC_CHANNEL_4
8371 * @arg @ref LL_ADC_CHANNEL_5
8372 * @arg @ref LL_ADC_CHANNEL_6
8373 * @arg @ref LL_ADC_CHANNEL_7
8374 * @arg @ref LL_ADC_CHANNEL_8
8375 * @arg @ref LL_ADC_CHANNEL_9
8376 * @arg @ref LL_ADC_CHANNEL_10
8377 * @arg @ref LL_ADC_CHANNEL_11
8378 * @arg @ref LL_ADC_CHANNEL_12
8379 * @arg @ref LL_ADC_CHANNEL_13
8380 * @arg @ref LL_ADC_CHANNEL_14
8381 * @arg @ref LL_ADC_CHANNEL_15
8382 * @arg @ref LL_ADC_CHANNEL_16
8383 * @arg @ref LL_ADC_CHANNEL_17
8384 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8385 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8386 *
8387 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
8388 * (1) For ADC channel read back from ADC register,
8389 * comparison with internal channel parameter to be done
8390 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
8391 * @param __GROUP__ This parameter can be one of the following values:
8392 * @arg @ref LL_ADC_GROUP_REGULAR
8393 * @arg @ref LL_ADC_GROUP_INJECTED
8394 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
8395 * @retval Returned value can be one of the following values:
8396 * @arg @ref LL_ADC_AWD_DISABLE
8397 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
8398 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
8399 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
8400 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
8401 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
8402 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
8403 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
8404 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
8405 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
8406 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
8407 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
8408 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
8409 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
8410 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
8411 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
8412 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
8413 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
8414 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
8415 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
8416 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
8417 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
8418 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
8419 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
8420 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
8421 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
8422 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
8423 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
8424 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
8425 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
8426 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
8427 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
8428 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
8429 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
8430 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
8431 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
8432 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
8433 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
8434 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
8435 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
8436 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
8437 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
8438 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
8439 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
8440 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
8441 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
8442 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
8443 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
8444 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
8445 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
8446 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
8447 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
8448 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
8449 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
8450 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
8451 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
8452 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
8453 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
8454 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
8455 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
8456 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
8457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
8458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
8459 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
8460 *
8461 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8462 */
8463 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
8464 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
8465 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
8466 : \
8467 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
8468 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
8469 : \
8470 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
8471 )
8473 /**
8474 * @brief Helper macro to set the value of ADC analog watchdog threshold high
8475 * or low in function of ADC resolution, when ADC resolution is
8476 * different of 12 bits.
8477 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
8478 * Example, with a ADC resolution of 8 bits, to set the value of
8479 * analog watchdog threshold high (on 8 bits):
8480 * LL_ADC_SetAnalogWDThresholds
8481 * (< ADCx param >,
8482 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
8483 * );
8484 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8485 * @arg @ref LL_ADC_RESOLUTION_12B
8486 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
8487 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8488 */
8489 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
8490 /* This macro has been kept anyway for compatibility with other */
8491 /* STM32 families featuring different ADC resolutions. */
8492 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
8493 ((__AWD_THRESHOLD__) << (0U))
8495 /**
8496 * @brief Helper macro to get the value of ADC analog watchdog threshold high
8497 * or low in function of ADC resolution, when ADC resolution is
8498 * different of 12 bits.
8499 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
8500 * Example, with a ADC resolution of 8 bits, to get the value of
8501 * analog watchdog threshold high (on 8 bits):
8502 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
8503 * (LL_ADC_RESOLUTION_8B,
8504 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
8505 * );
8506 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8507 * @arg @ref LL_ADC_RESOLUTION_12B
8508 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
8509 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8510 */
8511 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
8512 /* This macro has been kept anyway for compatibility with other */
8513 /* STM32 families featuring different ADC resolutions. */
8514 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
8515 (__AWD_THRESHOLD_12_BITS__)
8517 /**
8518 * @brief Helper macro to select the ADC common instance
8519 * to which is belonging the selected ADC instance.
8520 * @note ADC common register instance can be used for:
8521 * - Set parameters common to several ADC instances
8522 * - Multimode (for devices with several ADC instances)
8523 * Refer to functions having argument "ADCxy_COMMON" as parameter.
8524 * @note On STM32F37x, there is no common ADC instance.
8525 * However, ADC instance ADC1 has a role of common ADC instance
8526 * (equivalence with other STM32 families featuring several
8527 * ADC instances).
8528 * @param __ADCx__ ADC instance
8529 * @retval ADC common register instance
8530 */
8531 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
8532 (ADC1_COMMON)
8534 /**
8535 * @brief Helper macro to check if all ADC instances sharing the same
8536 * ADC common instance are disabled.
8537 * @note This check is required by functions with setting conditioned to
8538 * ADC state:
8539 * All ADC instances of the ADC common group must be disabled.
8540 * Refer to functions having argument "ADCxy_COMMON" as parameter.
8541 * @note On devices with only 1 ADC common instance, parameter of this macro
8542 * is useless and can be ignored (parameter kept for compatibility
8543 * with devices featuring several ADC common instances).
8544 * @note On STM32F37x, there is no common ADC instance.
8545 * However, ADC instance ADC1 has a role of common ADC instance
8546 * (equivalence with other STM32 families featuring several
8547 * ADC instances).
8548 * @param __ADCXY_COMMON__ ADC common instance
8549 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8550 * @retval Value "0" All ADC instances sharing the same ADC common instance
8551 * are disabled.
8552 * Value "1" At least one ADC instance sharing the same ADC common instance
8553 * is enabled
8554 */
8555 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
8556 LL_ADC_IsEnabled(ADC1)
8558 /**
8559 * @brief Helper macro to define the ADC conversion data full-scale digital
8560 * value corresponding to the selected ADC resolution.
8561 * @note ADC conversion data full-scale corresponds to voltage range
8562 * determined by analog voltage references Vref+ and Vref-
8563 * (refer to reference manual).
8564 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8565 * @arg @ref LL_ADC_RESOLUTION_12B
8566 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
8567 */
8568 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
8569 ((uint32_t)0xFFFU)
8571 /**
8572 * @brief Helper macro to convert the ADC conversion data from
8573 * a resolution to another resolution.
8574 * @note On STM32F37x, the only ADC resolution available is 12 bits.
8575 * This macro has been kept for compatibility purpose over other
8576 * STM32 families.
8577 * @param __DATA__ ADC conversion data to be converted
8578 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
8579 * This parameter can be one of the following values:
8580 * @arg @ref LL_ADC_RESOLUTION_12B
8581 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
8582 * This parameter can be one of the following values:
8583 * @arg @ref LL_ADC_RESOLUTION_12B
8584 * @retval ADC conversion data to the requested resolution
8585 */
8586 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
8587 __ADC_RESOLUTION_CURRENT__,\
8588 __ADC_RESOLUTION_TARGET__) \
8589 (((__DATA__) \
8590 << ((__ADC_RESOLUTION_CURRENT__) >> (0U))) \
8591 >> ((__ADC_RESOLUTION_TARGET__) >> (0U)) \
8592 )
8594 /**
8595 * @brief Helper macro to calculate the voltage (unit: mVolt)
8596 * corresponding to a ADC conversion data (unit: digital value).
8597 * @note Analog reference voltage (Vref+) must be either known from
8598 * user board environment or can be calculated using ADC measurement
8599 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8600 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
8601 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
8602 * (unit: digital value).
8603 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8604 * @arg @ref LL_ADC_RESOLUTION_12B
8605 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
8606 */
8607 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
8608 __ADC_DATA__,\
8609 __ADC_RESOLUTION__) \
8610 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
8611 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
8612 )
8615 /**
8616 * @brief Helper macro to calculate analog reference voltage (Vref+)
8617 * (unit: mVolt) from ADC conversion data of internal voltage
8618 * reference VrefInt.
8619 * @note Computation is using VrefInt calibration value
8620 * stored in system memory for each device during production.
8621 * @note This voltage depends on user board environment: voltage level
8622 * connected to pin Vref+.
8623 * On devices with small package, the pin Vref+ is not present
8624 * and internally bonded to pin Vdda.
8625 * @note On this STM32 serie, calibration data of internal voltage reference
8626 * VrefInt corresponds to a resolution of 12 bits,
8627 * this is the recommended ADC resolution to convert voltage of
8628 * internal voltage reference VrefInt.
8629 * On STM32F37x, the only ADC resolution available is 12 bits.
8630 * The parameter of ADC resolution is kept for compatibility purpose
8631 * over other STM32 families.
8632 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
8633 * of internal voltage reference VrefInt (unit: digital value).
8634 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8635 * @arg @ref LL_ADC_RESOLUTION_12B
8636 * @retval Analog reference voltage (unit: mV)
8637 */
8638 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
8639 __ADC_RESOLUTION__) \
8640 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
8641 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
8642 (__ADC_RESOLUTION__), \
8643 LL_ADC_RESOLUTION_12B) \
8644 )
8646 /**
8647 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
8648 * from ADC conversion data of internal temperature sensor.
8649 * @note Computation is using temperature sensor calibration values
8650 * stored in system memory for each device during production.
8651 * @note Calculation formula:
8652 * Temperature = ((TS_ADC_DATA - TS_CAL1)
8653 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
8654 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
8655 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8656 * Avg_Slope = (TS_CAL2 - TS_CAL1)
8657 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
8658 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
8659 * TEMP_DEGC_CAL1 (calibrated in factory)
8660 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
8661 * TEMP_DEGC_CAL2 (calibrated in factory)
8662 * Caution: Calculation relevancy under reserve that calibration
8663 * parameters are correct (address and data).
8664 * To calculate temperature using temperature sensor
8665 * datasheet typical values (generic values less, therefore
8666 * less accurate than calibrated values),
8667 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
8668 * @note As calculation input, the analog reference voltage (Vref+) must be
8669 * defined as it impacts the ADC LSB equivalent voltage.
8670 * @note Analog reference voltage (Vref+) must be either known from
8671 * user board environment or can be calculated using ADC measurement
8672 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8673 * @note On this STM32 serie, calibration data of temperature sensor
8674 * corresponds to a resolution of 12 bits,
8675 * this is the recommended ADC resolution to convert voltage of
8676 * temperature sensor.
8677 * On STM32F37x, the only ADC resolution available is 12 bits.
8678 * The parameter of ADC resolution is kept for compatibility purpose
8679 * over other STM32 families.
8680 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
8681 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
8682 * temperature sensor (unit: digital value).
8683 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
8684 * sensor voltage has been measured.
8685 * This parameter can be one of the following values:
8686 * @arg @ref LL_ADC_RESOLUTION_12B
8687 * @retval Temperature (unit: degree Celsius)
8688 */
8689 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
8690 __TEMPSENSOR_ADC_DATA__,\
8691 __ADC_RESOLUTION__) \
8692 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
8693 (__ADC_RESOLUTION__), \
8694 LL_ADC_RESOLUTION_12B) \
8695 * (__VREFANALOG_VOLTAGE__)) \
8696 / TEMPSENSOR_CAL_VREFANALOG) \
8697 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
8698 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
8699 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
8700 ) + TEMPSENSOR_CAL1_TEMP \
8701 )
8703 /**
8704 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
8705 * from ADC conversion data of internal temperature sensor.
8706 * @note Computation is using temperature sensor typical values
8707 * (refer to device datasheet).
8708 * @note Calculation formula:
8709 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
8710 * / Avg_Slope + CALx_TEMP
8711 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8712 * (unit: digital value)
8713 * Avg_Slope = temperature sensor slope
8714 * (unit: uV/Degree Celsius)
8715 * TS_TYP_CALx_VOLT = temperature sensor digital value at
8716 * temperature CALx_TEMP (unit: mV)
8717 * Caution: Calculation relevancy under reserve the temperature sensor
8718 * of the current device has characteristics in line with
8719 * datasheet typical values.
8720 * If temperature sensor calibration values are available on
8721 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
8722 * temperature calculation will be more accurate using
8723 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
8724 * @note As calculation input, the analog reference voltage (Vref+) must be
8725 * defined as it impacts the ADC LSB equivalent voltage.
8726 * @note Analog reference voltage (Vref+) must be either known from
8727 * user board environment or can be calculated using ADC measurement
8728 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8729 * @note ADC measurement data must correspond to a resolution of 12bits
8730 * (full scale digital value 4095). If not the case, the data must be
8731 * preliminarily rescaled to an equivalent resolution of 12 bits.
8732 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
8733 * On STM32F37x, refer to device datasheet parameter "Avg_Slope".
8734 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
8735 * On STM32F37x, refer to device datasheet parameter "V25".
8736 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
8737 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
8738 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
8739 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
8740 * This parameter can be one of the following values:
8741 * @arg @ref LL_ADC_RESOLUTION_12B
8742 * @retval Temperature (unit: degree Celsius)
8743 */
8744 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
8745 __TEMPSENSOR_TYP_CALX_V__,\
8746 __TEMPSENSOR_CALX_TEMP__,\
8747 __VREFANALOG_VOLTAGE__,\
8748 __TEMPSENSOR_ADC_DATA__,\
8749 __ADC_RESOLUTION__) \
8750 ((( ( \
8751 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
8752 * 1000) \
8753 - \
8754 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
8755 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
8756 * 1000) \
8757 ) \
8758 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
8759 ) + (__TEMPSENSOR_CALX_TEMP__) \
8760 )
8762 /**
8763 * @}
8764 */
8766 /**
8767 * @}
8768 */
8771 /* Exported functions --------------------------------------------------------*/
8772 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
8773 * @{
8774 */
8776 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
8777 * @{
8778 */
8779 /* Note: LL ADC functions to set DMA transfer are located into sections of */
8780 /* configuration of ADC instance, groups and multimode (if available): */
8781 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
8783 /**
8784 * @brief Function to help to configure DMA transfer from ADC: retrieve the
8785 * ADC register address from ADC instance and a list of ADC registers
8786 * intended to be used (most commonly) with DMA transfer.
8787 * @note These ADC registers are data registers:
8788 * when ADC conversion data is available in ADC data registers,
8789 * ADC generates a DMA transfer request.
8790 * @note This macro is intended to be used with LL DMA driver, refer to
8791 * function "LL_DMA_ConfigAddresses()".
8792 * Example:
8793 * LL_DMA_ConfigAddresses(DMA1,
8794 * LL_DMA_CHANNEL_1,
8795 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
8796 * (uint32_t)&< array or variable >,
8797 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
8798 * @note For devices with several ADC: in multimode, some devices
8799 * use a different data register outside of ADC instance scope
8800 * (common data register). This macro manages this register difference,
8801 * only ADC instance has to be set as parameter.
8802 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
8803 * @param ADCx ADC instance
8804 * @param Register This parameter can be one of the following values:
8805 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
8806 * @retval ADC register address
8807 */
8809 {
8810 /* Retrieve address of register DR */
8812 }
8814 /**
8815 * @}
8816 */
8818 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
8819 * @{
8820 */
8822 /**
8823 * @brief Set parameter common to several ADC: measurement path to internal
8824 * channels (VrefInt, temperature sensor, ...).
8825 * @note One or several values can be selected.
8826 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
8827 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
8828 * @note Stabilization time of measurement path to internal channel:
8829 * After enabling internal paths, before starting ADC conversion,
8830 * a delay is required for internal voltage reference and
8831 * temperature sensor stabilization time.
8832 * Refer to device datasheet.
8833 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
8834 * @note ADC internal channel sampling time constraint:
8835 * For ADC conversion of internal channels,
8836 * a sampling time minimum value is required.
8837 * Refer to device datasheet.
8838 * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
8839 * @param ADCxy_COMMON ADC common instance
8840 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8841 * @param PathInternal This parameter can be a combination of the following values:
8842 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
8843 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
8844 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
8845 * @retval None
8846 */
8847 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
8848 {
8850 }
8852 /**
8853 * @brief Get parameter common to several ADC: measurement path to internal
8854 * channels (VrefInt, temperature sensor, ...).
8855 * @note One or several values can be selected.
8856 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
8857 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
8858 * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
8859 * @param ADCxy_COMMON ADC common instance
8860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8861 * @retval Returned value can be a combination of the following values:
8862 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
8863 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
8864 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
8865 */
8867 {
8869 }
8871 /**
8872 * @}
8873 */
8875 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
8876 * @{
8877 */
8879 /**
8880 * @brief Set ADC conversion data alignment.
8881 * @note Refer to reference manual for alignments formats
8882 * dependencies to ADC resolutions.
8883 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
8884 * @param ADCx ADC instance
8885 * @param DataAlignment This parameter can be one of the following values:
8886 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
8887 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
8888 * @retval None
8889 */
8891 {
8893 }
8895 /**
8896 * @brief Get ADC conversion data alignment.
8897 * @note Refer to reference manual for alignments formats
8898 * dependencies to ADC resolutions.
8899 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
8900 * @param ADCx ADC instance
8901 * @retval Returned value can be one of the following values:
8902 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
8903 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
8904 */
8906 {
8908 }
8910 /**
8911 * @brief Set ADC sequencers scan mode, for all ADC groups
8912 * (group regular, group injected).
8913 * @note According to sequencers scan mode :
8914 * - If disabled: ADC conversion is performed in unitary conversion
8915 * mode (one channel converted, that defined in rank 1).
8916 * Configuration of sequencers of all ADC groups
8917 * (sequencer scan length, ...) is discarded: equivalent to
8918 * scan length of 1 rank.
8919 * - If enabled: ADC conversions are performed in sequence conversions
8920 * mode, according to configuration of sequencers of
8921 * each ADC group (sequencer scan length, ...).
8922 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
8923 * and to function @ref LL_ADC_INJ_SetSequencerLength().
8924 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
8925 * @param ADCx ADC instance
8926 * @param ScanMode This parameter can be one of the following values:
8927 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
8928 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
8929 * @retval None
8930 */
8932 {
8934 }
8936 /**
8937 * @brief Get ADC sequencers scan mode, for all ADC groups
8938 * (group regular, group injected).
8939 * @note According to sequencers scan mode :
8940 * - If disabled: ADC conversion is performed in unitary conversion
8941 * mode (one channel converted, that defined in rank 1).
8942 * Configuration of sequencers of all ADC groups
8943 * (sequencer scan length, ...) is discarded: equivalent to
8944 * scan length of 1 rank.
8945 * - If enabled: ADC conversions are performed in sequence conversions
8946 * mode, according to configuration of sequencers of
8947 * each ADC group (sequencer scan length, ...).
8948 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
8949 * and to function @ref LL_ADC_INJ_SetSequencerLength().
8950 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
8951 * @param ADCx ADC instance
8952 * @retval Returned value can be one of the following values:
8953 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
8954 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
8955 */
8957 {
8959 }
8961 /**
8962 * @}
8963 */
8965 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
8966 * @{
8967 */
8969 /**
8970 * @brief Set ADC group regular conversion trigger source:
8971 * internal (SW start) or external from timer or external interrupt.
8972 * @note On this STM32 serie, external trigger is set with trigger polarity:
8973 * rising edge (only trigger polarity available on this STM32 serie).
8974 * @note Availability of parameters of trigger sources from timer
8975 * depends on timers availability on the selected device.
8976 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
8977 * @param ADCx ADC instance
8978 * @param TriggerSource This parameter can be one of the following values:
8979 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
8980 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
8981 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
8982 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
8983 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
8984 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
8985 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
8986 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
8987 * @retval None
8988 */
8990 {
8991 /* Note: On this STM32 serie, ADC group regular external trigger edge */
8992 /* is used to perform a ADC conversion start. */
8993 /* This function does not set external trigger edge. */
8994 /* This feature is set using function */
8995 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
8997 }
8999 /**
9000 * @brief Get ADC group regular conversion trigger source:
9001 * internal (SW start) or external from timer or external interrupt.
9002 * @note To determine whether group regular trigger source is
9003 * internal (SW start) or external, without detail
9004 * of which peripheral is selected as external trigger,
9005 * (equivalent to
9006 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
9007 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
9008 * @note Availability of parameters of trigger sources from timer
9009 * depends on timers availability on the selected device.
9010 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
9011 * @param ADCx ADC instance
9012 * @retval Returned value can be one of the following values:
9013 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
9014 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
9015 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
9016 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
9017 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
9018 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
9019 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
9020 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
9021 */
9023 {
9025 }
9027 /**
9028 * @brief Get ADC group regular conversion trigger source internal (SW start)
9029 or external.
9030 * @note In case of group regular trigger source set to external trigger,
9031 * to determine which peripheral is selected as external trigger,
9032 * use function @ref LL_ADC_REG_GetTriggerSource().
9033 * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
9034 * @param ADCx ADC instance
9035 * @retval Value "0" trigger source external trigger
9036 * Value "1" trigger source SW start.
9037 */
9039 {
9041 }
9044 /**
9045 * @brief Set ADC group regular sequencer length and scan direction.
9046 * @note Description of ADC group regular sequencer features:
9047 * - For devices with sequencer fully configurable
9048 * (function "LL_ADC_REG_SetSequencerRanks()" available):
9049 * sequencer length and each rank affectation to a channel
9050 * are configurable.
9051 * This function performs configuration of:
9052 * - Sequence length: Number of ranks in the scan sequence.
9053 * - Sequence direction: Unless specified in parameters, sequencer
9054 * scan direction is forward (from rank 1 to rank n).
9055 * Sequencer ranks are selected using
9056 * function "LL_ADC_REG_SetSequencerRanks()".
9057 * - For devices with sequencer not fully configurable
9058 * (function "LL_ADC_REG_SetSequencerChannels()" available):
9059 * sequencer length and each rank affectation to a channel
9060 * are defined by channel number.
9061 * This function performs configuration of:
9062 * - Sequence length: Number of ranks in the scan sequence is
9063 * defined by number of channels set in the sequence,
9064 * rank of each channel is fixed by channel HW number.
9065 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
9066 * - Sequence direction: Unless specified in parameters, sequencer
9067 * scan direction is forward (from lowest channel number to
9068 * highest channel number).
9069 * Sequencer ranks are selected using
9070 * function "LL_ADC_REG_SetSequencerChannels()".
9071 * @note On this STM32 serie, group regular sequencer configuration
9072 * is conditioned to ADC instance sequencer mode.
9073 * If ADC instance sequencer mode is disabled, sequencers of
9074 * all groups (group regular, group injected) can be configured
9075 * but their execution is disabled (limited to rank 1).
9076 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9077 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9078 * ADC conversion on only 1 channel.
9079 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
9080 * @param ADCx ADC instance
9081 * @param SequencerNbRanks This parameter can be one of the following values:
9082 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
9083 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
9084 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
9085 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
9086 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
9087 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
9088 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
9089 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
9090 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
9091 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
9092 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
9093 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
9094 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
9095 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
9096 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
9097 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
9098 * @retval None
9099 */
9100 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
9101 {
9103 }
9105 /**
9106 * @brief Get ADC group regular sequencer length and scan direction.
9107 * @note Description of ADC group regular sequencer features:
9108 * - For devices with sequencer fully configurable
9109 * (function "LL_ADC_REG_SetSequencerRanks()" available):
9110 * sequencer length and each rank affectation to a channel
9111 * are configurable.
9112 * This function retrieves:
9113 * - Sequence length: Number of ranks in the scan sequence.
9114 * - Sequence direction: Unless specified in parameters, sequencer
9115 * scan direction is forward (from rank 1 to rank n).
9116 * Sequencer ranks are selected using
9117 * function "LL_ADC_REG_SetSequencerRanks()".
9118 * - For devices with sequencer not fully configurable
9119 * (function "LL_ADC_REG_SetSequencerChannels()" available):
9120 * sequencer length and each rank affectation to a channel
9121 * are defined by channel number.
9122 * This function retrieves:
9123 * - Sequence length: Number of ranks in the scan sequence is
9124 * defined by number of channels set in the sequence,
9125 * rank of each channel is fixed by channel HW number.
9126 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
9127 * - Sequence direction: Unless specified in parameters, sequencer
9128 * scan direction is forward (from lowest channel number to
9129 * highest channel number).
9130 * Sequencer ranks are selected using
9131 * function "LL_ADC_REG_SetSequencerChannels()".
9132 * @note On this STM32 serie, group regular sequencer configuration
9133 * is conditioned to ADC instance sequencer mode.
9134 * If ADC instance sequencer mode is disabled, sequencers of
9135 * all groups (group regular, group injected) can be configured
9136 * but their execution is disabled (limited to rank 1).
9137 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9138 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9139 * ADC conversion on only 1 channel.
9140 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
9141 * @param ADCx ADC instance
9142 * @retval Returned value can be one of the following values:
9143 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
9144 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
9145 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
9146 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
9147 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
9148 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
9149 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
9150 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
9151 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
9152 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
9153 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
9154 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
9155 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
9156 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
9157 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
9158 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
9159 */
9161 {
9163 }
9165 /**
9166 * @brief Set ADC group regular sequencer discontinuous mode:
9167 * sequence subdivided and scan conversions interrupted every selected
9168 * number of ranks.
9169 * @note It is not possible to enable both ADC group regular
9170 * continuous mode and sequencer discontinuous mode.
9171 * @note It is not possible to enable both ADC auto-injected mode
9172 * and ADC group regular sequencer discontinuous mode.
9173 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
9174 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
9175 * @param ADCx ADC instance
9176 * @param SeqDiscont This parameter can be one of the following values:
9177 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
9178 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
9179 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
9180 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
9181 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
9182 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
9183 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
9184 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
9185 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
9186 * @retval None
9187 */
9189 {
9191 }
9193 /**
9194 * @brief Get ADC group regular sequencer discontinuous mode:
9195 * sequence subdivided and scan conversions interrupted every selected
9196 * number of ranks.
9197 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
9198 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
9199 * @param ADCx ADC instance
9200 * @retval Returned value can be one of the following values:
9201 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
9202 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
9203 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
9204 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
9205 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
9206 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
9207 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
9208 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
9209 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
9210 */
9212 {
9214 }
9216 /**
9217 * @brief Set ADC group regular sequence: channel on the selected
9218 * scan sequence rank.
9219 * @note This function performs configuration of:
9220 * - Channels ordering into each rank of scan sequence:
9221 * whatever channel can be placed into whatever rank.
9222 * @note On this STM32 serie, ADC group regular sequencer is
9223 * fully configurable: sequencer length and each rank
9224 * affectation to a channel are configurable.
9225 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
9226 * @note Depending on devices and packages, some channels may not be available.
9227 * Refer to device datasheet for channels availability.
9228 * @note On this STM32 serie, to measure internal channels (VrefInt,
9229 * TempSensor, ...), measurement paths to internal channels must be
9230 * enabled separately.
9231 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
9232 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
9233 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
9234 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
9235 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
9236 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
9237 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
9238 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
9239 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
9240 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
9241 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
9242 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
9243 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
9244 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
9245 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
9246 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
9247 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
9248 * @param ADCx ADC instance
9249 * @param Rank This parameter can be one of the following values:
9250 * @arg @ref LL_ADC_REG_RANK_1
9251 * @arg @ref LL_ADC_REG_RANK_2
9252 * @arg @ref LL_ADC_REG_RANK_3
9253 * @arg @ref LL_ADC_REG_RANK_4
9254 * @arg @ref LL_ADC_REG_RANK_5
9255 * @arg @ref LL_ADC_REG_RANK_6
9256 * @arg @ref LL_ADC_REG_RANK_7
9257 * @arg @ref LL_ADC_REG_RANK_8
9258 * @arg @ref LL_ADC_REG_RANK_9
9259 * @arg @ref LL_ADC_REG_RANK_10
9260 * @arg @ref LL_ADC_REG_RANK_11
9261 * @arg @ref LL_ADC_REG_RANK_12
9262 * @arg @ref LL_ADC_REG_RANK_13
9263 * @arg @ref LL_ADC_REG_RANK_14
9264 * @arg @ref LL_ADC_REG_RANK_15
9265 * @arg @ref LL_ADC_REG_RANK_16
9266 * @param Channel This parameter can be one of the following values:
9267 * @arg @ref LL_ADC_CHANNEL_0
9268 * @arg @ref LL_ADC_CHANNEL_1
9269 * @arg @ref LL_ADC_CHANNEL_2
9270 * @arg @ref LL_ADC_CHANNEL_3
9271 * @arg @ref LL_ADC_CHANNEL_4
9272 * @arg @ref LL_ADC_CHANNEL_5
9273 * @arg @ref LL_ADC_CHANNEL_6
9274 * @arg @ref LL_ADC_CHANNEL_7
9275 * @arg @ref LL_ADC_CHANNEL_8
9276 * @arg @ref LL_ADC_CHANNEL_9
9277 * @arg @ref LL_ADC_CHANNEL_10
9278 * @arg @ref LL_ADC_CHANNEL_11
9279 * @arg @ref LL_ADC_CHANNEL_12
9280 * @arg @ref LL_ADC_CHANNEL_13
9281 * @arg @ref LL_ADC_CHANNEL_14
9282 * @arg @ref LL_ADC_CHANNEL_15
9283 * @arg @ref LL_ADC_CHANNEL_16
9284 * @arg @ref LL_ADC_CHANNEL_17
9285 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9286 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9287 *
9288 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9289 * @retval None
9290 */
9291 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
9292 {
9293 /* Set bits with content of parameter "Channel" with bits position */
9294 /* in register and register position depending on parameter "Rank". */
9295 /* Parameters "Rank" and "Channel" are used with masks because containing */
9296 /* other bits reserved for other purpose. */
9297 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
9302 }
9304 /**
9305 * @brief Get ADC group regular sequence: channel on the selected
9306 * scan sequence rank.
9307 * @note On this STM32 serie, ADC group regular sequencer is
9308 * fully configurable: sequencer length and each rank
9309 * affectation to a channel are configurable.
9310 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
9311 * @note Depending on devices and packages, some channels may not be available.
9312 * Refer to device datasheet for channels availability.
9313 * @note Usage of the returned channel number:
9314 * - To reinject this channel into another function LL_ADC_xxx:
9315 * the returned channel number is only partly formatted on definition
9316 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
9317 * with parts of literals LL_ADC_CHANNEL_x or using
9318 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9319 * Then the selected literal LL_ADC_CHANNEL_x can be used
9320 * as parameter for another function.
9321 * - To get the channel number in decimal format:
9322 * process the returned value with the helper macro
9323 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9324 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
9325 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
9326 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
9327 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
9328 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
9329 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
9330 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
9331 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
9332 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
9333 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
9334 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
9335 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
9336 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
9337 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
9338 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
9339 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
9340 * @param ADCx ADC instance
9341 * @param Rank This parameter can be one of the following values:
9342 * @arg @ref LL_ADC_REG_RANK_1
9343 * @arg @ref LL_ADC_REG_RANK_2
9344 * @arg @ref LL_ADC_REG_RANK_3
9345 * @arg @ref LL_ADC_REG_RANK_4
9346 * @arg @ref LL_ADC_REG_RANK_5
9347 * @arg @ref LL_ADC_REG_RANK_6
9348 * @arg @ref LL_ADC_REG_RANK_7
9349 * @arg @ref LL_ADC_REG_RANK_8
9350 * @arg @ref LL_ADC_REG_RANK_9
9351 * @arg @ref LL_ADC_REG_RANK_10
9352 * @arg @ref LL_ADC_REG_RANK_11
9353 * @arg @ref LL_ADC_REG_RANK_12
9354 * @arg @ref LL_ADC_REG_RANK_13
9355 * @arg @ref LL_ADC_REG_RANK_14
9356 * @arg @ref LL_ADC_REG_RANK_15
9357 * @arg @ref LL_ADC_REG_RANK_16
9358 * @retval Returned value can be one of the following values:
9359 * @arg @ref LL_ADC_CHANNEL_0
9360 * @arg @ref LL_ADC_CHANNEL_1
9361 * @arg @ref LL_ADC_CHANNEL_2
9362 * @arg @ref LL_ADC_CHANNEL_3
9363 * @arg @ref LL_ADC_CHANNEL_4
9364 * @arg @ref LL_ADC_CHANNEL_5
9365 * @arg @ref LL_ADC_CHANNEL_6
9366 * @arg @ref LL_ADC_CHANNEL_7
9367 * @arg @ref LL_ADC_CHANNEL_8
9368 * @arg @ref LL_ADC_CHANNEL_9
9369 * @arg @ref LL_ADC_CHANNEL_10
9370 * @arg @ref LL_ADC_CHANNEL_11
9371 * @arg @ref LL_ADC_CHANNEL_12
9372 * @arg @ref LL_ADC_CHANNEL_13
9373 * @arg @ref LL_ADC_CHANNEL_14
9374 * @arg @ref LL_ADC_CHANNEL_15
9375 * @arg @ref LL_ADC_CHANNEL_16
9376 * @arg @ref LL_ADC_CHANNEL_17
9377 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9378 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9379 *
9380 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
9381 * (1) For ADC channel read back from ADC register,
9382 * comparison with internal channel parameter to be done
9383 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
9384 */
9386 {
9387 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
9392 );
9393 }
9395 /**
9396 * @brief Set ADC continuous conversion mode on ADC group regular.
9397 * @note Description of ADC continuous conversion mode:
9398 * - single mode: one conversion per trigger
9399 * - continuous mode: after the first trigger, following
9400 * conversions launched successively automatically.
9401 * @note It is not possible to enable both ADC group regular
9402 * continuous mode and sequencer discontinuous mode.
9403 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
9404 * @param ADCx ADC instance
9405 * @param Continuous This parameter can be one of the following values:
9406 * @arg @ref LL_ADC_REG_CONV_SINGLE
9407 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
9408 * @retval None
9409 */
9411 {
9413 }
9415 /**
9416 * @brief Get ADC continuous conversion mode on ADC group regular.
9417 * @note Description of ADC continuous conversion mode:
9418 * - single mode: one conversion per trigger
9419 * - continuous mode: after the first trigger, following
9420 * conversions launched successively automatically.
9421 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
9422 * @param ADCx ADC instance
9423 * @retval Returned value can be one of the following values:
9424 * @arg @ref LL_ADC_REG_CONV_SINGLE
9425 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
9426 */
9428 {
9430 }
9432 /**
9433 * @brief Set ADC group regular conversion data transfer: no transfer or
9434 * transfer by DMA, and DMA requests mode.
9435 * @note If transfer by DMA selected, specifies the DMA requests
9436 * mode:
9437 * - Limited mode (One shot mode): DMA transfer requests are stopped
9438 * when number of DMA data transfers (number of
9439 * ADC conversions) is reached.
9440 * This ADC mode is intended to be used with DMA mode non-circular.
9441 * - Unlimited mode: DMA transfer requests are unlimited,
9442 * whatever number of DMA data transfers (number of
9443 * ADC conversions).
9444 * This ADC mode is intended to be used with DMA mode circular.
9445 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
9446 * mode non-circular:
9447 * when DMA transfers size will be reached, DMA will stop transfers of
9448 * ADC conversions data ADC will raise an overrun error
9449 * (overrun flag and interruption if enabled).
9450 * @note To configure DMA source address (peripheral address),
9451 * use function @ref LL_ADC_DMA_GetRegAddr().
9452 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
9453 * @param ADCx ADC instance
9454 * @param DMATransfer This parameter can be one of the following values:
9455 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
9456 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
9457 * @retval None
9458 */
9460 {
9462 }
9464 /**
9465 * @brief Get ADC group regular conversion data transfer: no transfer or
9466 * transfer by DMA, and DMA requests mode.
9467 * @note If transfer by DMA selected, specifies the DMA requests
9468 * mode:
9469 * - Limited mode (One shot mode): DMA transfer requests are stopped
9470 * when number of DMA data transfers (number of
9471 * ADC conversions) is reached.
9472 * This ADC mode is intended to be used with DMA mode non-circular.
9473 * - Unlimited mode: DMA transfer requests are unlimited,
9474 * whatever number of DMA data transfers (number of
9475 * ADC conversions).
9476 * This ADC mode is intended to be used with DMA mode circular.
9477 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
9478 * mode non-circular:
9479 * when DMA transfers size will be reached, DMA will stop transfers of
9480 * ADC conversions data ADC will raise an overrun error
9481 * (overrun flag and interruption if enabled).
9482 * @note To configure DMA source address (peripheral address),
9483 * use function @ref LL_ADC_DMA_GetRegAddr().
9484 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
9485 * @param ADCx ADC instance
9486 * @retval Returned value can be one of the following values:
9487 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
9488 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
9489 */
9491 {
9493 }
9495 /**
9496 * @}
9497 */
9499 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
9500 * @{
9501 */
9503 /**
9504 * @brief Set ADC group injected conversion trigger source:
9505 * internal (SW start) or external from timer or external interrupt.
9506 * @note On this STM32 serie, external trigger is set with trigger polarity:
9507 * rising edge (only trigger polarity available on this STM32 serie).
9508 * @note Availability of parameters of trigger sources from timer
9509 * depends on timers availability on the selected device.
9510 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
9511 * @param ADCx ADC instance
9512 * @param TriggerSource This parameter can be one of the following values:
9513 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
9514 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
9515 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
9516 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
9517 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
9518 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
9519 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
9520 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
9521 * @retval None
9522 */
9524 {
9525 /* Note: On this STM32 serie, ADC group injected external trigger edge */
9526 /* is used to perform a ADC conversion start. */
9527 /* This function does not set external trigger edge. */
9528 /* This feature is set using function */
9529 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
9531 }
9533 /**
9534 * @brief Get ADC group injected conversion trigger source:
9535 * internal (SW start) or external from timer or external interrupt.
9536 * @note To determine whether group injected trigger source is
9537 * internal (SW start) or external, without detail
9538 * of which peripheral is selected as external trigger,
9539 * (equivalent to
9540 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
9541 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
9542 * @note Availability of parameters of trigger sources from timer
9543 * depends on timers availability on the selected device.
9544 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
9545 * @param ADCx ADC instance
9546 * @retval Returned value can be one of the following values:
9547 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
9548 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
9549 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
9550 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
9551 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
9552 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
9553 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
9554 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
9555 */
9557 {
9559 }
9561 /**
9562 * @brief Get ADC group injected conversion trigger source internal (SW start)
9563 or external
9564 * @note In case of group injected trigger source set to external trigger,
9565 * to determine which peripheral is selected as external trigger,
9566 * use function @ref LL_ADC_INJ_GetTriggerSource.
9567 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
9568 * @param ADCx ADC instance
9569 * @retval Value "0" trigger source external trigger
9570 * Value "1" trigger source SW start.
9571 */
9573 {
9575 }
9577 /**
9578 * @brief Set ADC group injected sequencer length and scan direction.
9579 * @note This function performs configuration of:
9580 * - Sequence length: Number of ranks in the scan sequence.
9581 * - Sequence direction: Unless specified in parameters, sequencer
9582 * scan direction is forward (from rank 1 to rank n).
9583 * @note On this STM32 serie, group injected sequencer configuration
9584 * is conditioned to ADC instance sequencer mode.
9585 * If ADC instance sequencer mode is disabled, sequencers of
9586 * all groups (group regular, group injected) can be configured
9587 * but their execution is disabled (limited to rank 1).
9588 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9589 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9590 * ADC conversion on only 1 channel.
9591 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
9592 * @param ADCx ADC instance
9593 * @param SequencerNbRanks This parameter can be one of the following values:
9594 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
9595 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
9596 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
9597 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
9598 * @retval None
9599 */
9600 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
9601 {
9603 }
9605 /**
9606 * @brief Get ADC group injected sequencer length and scan direction.
9607 * @note This function retrieves:
9608 * - Sequence length: Number of ranks in the scan sequence.
9609 * - Sequence direction: Unless specified in parameters, sequencer
9610 * scan direction is forward (from rank 1 to rank n).
9611 * @note On this STM32 serie, group injected sequencer configuration
9612 * is conditioned to ADC instance sequencer mode.
9613 * If ADC instance sequencer mode is disabled, sequencers of
9614 * all groups (group regular, group injected) can be configured
9615 * but their execution is disabled (limited to rank 1).
9616 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9617 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9618 * ADC conversion on only 1 channel.
9619 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
9620 * @param ADCx ADC instance
9621 * @retval Returned value can be one of the following values:
9622 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
9623 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
9624 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
9625 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
9626 */
9628 {
9630 }
9632 /**
9633 * @brief Set ADC group injected sequencer discontinuous mode:
9634 * sequence subdivided and scan conversions interrupted every selected
9635 * number of ranks.
9636 * @note It is not possible to enable both ADC group injected
9637 * auto-injected mode and sequencer discontinuous mode.
9638 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
9639 * @param ADCx ADC instance
9640 * @param SeqDiscont This parameter can be one of the following values:
9641 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
9642 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
9643 * @retval None
9644 */
9646 {
9648 }
9650 /**
9651 * @brief Get ADC group injected sequencer discontinuous mode:
9652 * sequence subdivided and scan conversions interrupted every selected
9653 * number of ranks.
9654 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
9655 * @param ADCx ADC instance
9656 * @retval Returned value can be one of the following values:
9657 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
9658 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
9659 */
9661 {
9663 }
9665 /**
9666 * @brief Set ADC group injected sequence: channel on the selected
9667 * sequence rank.
9668 * @note Depending on devices and packages, some channels may not be available.
9669 * Refer to device datasheet for channels availability.
9670 * @note On this STM32 serie, to measure internal channels (VrefInt,
9671 * TempSensor, ...), measurement paths to internal channels must be
9672 * enabled separately.
9673 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
9674 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
9675 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
9676 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
9677 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
9678 * @param ADCx ADC instance
9679 * @param Rank This parameter can be one of the following values:
9680 * @arg @ref LL_ADC_INJ_RANK_1
9681 * @arg @ref LL_ADC_INJ_RANK_2
9682 * @arg @ref LL_ADC_INJ_RANK_3
9683 * @arg @ref LL_ADC_INJ_RANK_4
9684 * @param Channel This parameter can be one of the following values:
9685 * @arg @ref LL_ADC_CHANNEL_0
9686 * @arg @ref LL_ADC_CHANNEL_1
9687 * @arg @ref LL_ADC_CHANNEL_2
9688 * @arg @ref LL_ADC_CHANNEL_3
9689 * @arg @ref LL_ADC_CHANNEL_4
9690 * @arg @ref LL_ADC_CHANNEL_5
9691 * @arg @ref LL_ADC_CHANNEL_6
9692 * @arg @ref LL_ADC_CHANNEL_7
9693 * @arg @ref LL_ADC_CHANNEL_8
9694 * @arg @ref LL_ADC_CHANNEL_9
9695 * @arg @ref LL_ADC_CHANNEL_10
9696 * @arg @ref LL_ADC_CHANNEL_11
9697 * @arg @ref LL_ADC_CHANNEL_12
9698 * @arg @ref LL_ADC_CHANNEL_13
9699 * @arg @ref LL_ADC_CHANNEL_14
9700 * @arg @ref LL_ADC_CHANNEL_15
9701 * @arg @ref LL_ADC_CHANNEL_16
9702 * @arg @ref LL_ADC_CHANNEL_17
9703 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9704 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9705 *
9706 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9707 * @retval None
9708 */
9709 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
9710 {
9711 /* Set bits with content of parameter "Channel" with bits position */
9712 /* in register depending on parameter "Rank". */
9713 /* Parameters "Rank" and "Channel" are used with masks because containing */
9714 /* other bits reserved for other purpose. */
9718 }
9720 /**
9721 * @brief Get ADC group injected sequence: channel on the selected
9722 * sequence rank.
9723 * @note Depending on devices and packages, some channels may not be available.
9724 * Refer to device datasheet for channels availability.
9725 * @note Usage of the returned channel number:
9726 * - To reinject this channel into another function LL_ADC_xxx:
9727 * the returned channel number is only partly formatted on definition
9728 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
9729 * with parts of literals LL_ADC_CHANNEL_x or using
9730 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9731 * Then the selected literal LL_ADC_CHANNEL_x can be used
9732 * as parameter for another function.
9733 * - To get the channel number in decimal format:
9734 * process the returned value with the helper macro
9735 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9736 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
9737 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
9738 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
9739 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
9740 * @param ADCx ADC instance
9741 * @param Rank This parameter can be one of the following values:
9742 * @arg @ref LL_ADC_INJ_RANK_1
9743 * @arg @ref LL_ADC_INJ_RANK_2
9744 * @arg @ref LL_ADC_INJ_RANK_3
9745 * @arg @ref LL_ADC_INJ_RANK_4
9746 * @retval Returned value can be one of the following values:
9747 * @arg @ref LL_ADC_CHANNEL_0
9748 * @arg @ref LL_ADC_CHANNEL_1
9749 * @arg @ref LL_ADC_CHANNEL_2
9750 * @arg @ref LL_ADC_CHANNEL_3
9751 * @arg @ref LL_ADC_CHANNEL_4
9752 * @arg @ref LL_ADC_CHANNEL_5
9753 * @arg @ref LL_ADC_CHANNEL_6
9754 * @arg @ref LL_ADC_CHANNEL_7
9755 * @arg @ref LL_ADC_CHANNEL_8
9756 * @arg @ref LL_ADC_CHANNEL_9
9757 * @arg @ref LL_ADC_CHANNEL_10
9758 * @arg @ref LL_ADC_CHANNEL_11
9759 * @arg @ref LL_ADC_CHANNEL_12
9760 * @arg @ref LL_ADC_CHANNEL_13
9761 * @arg @ref LL_ADC_CHANNEL_14
9762 * @arg @ref LL_ADC_CHANNEL_15
9763 * @arg @ref LL_ADC_CHANNEL_16
9764 * @arg @ref LL_ADC_CHANNEL_17
9765 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9766 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9767 *
9768 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
9769 * (1) For ADC channel read back from ADC register,
9770 * comparison with internal channel parameter to be done
9771 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
9772 */
9774 {
9778 );
9779 }
9781 /**
9782 * @brief Set ADC group injected conversion trigger:
9783 * independent or from ADC group regular.
9784 * @note This mode can be used to extend number of data registers
9785 * updated after one ADC conversion trigger and with data
9786 * permanently kept (not erased by successive conversions of scan of
9787 * ADC sequencer ranks), up to 5 data registers:
9788 * 1 data register on ADC group regular, 4 data registers
9789 * on ADC group injected.
9790 * @note If ADC group injected injected trigger source is set to an
9791 * external trigger, this feature must be must be set to
9792 * independent trigger.
9793 * ADC group injected automatic trigger is compliant only with
9794 * group injected trigger source set to SW start, without any
9795 * further action on ADC group injected conversion start or stop:
9796 * in this case, ADC group injected is controlled only
9797 * from ADC group regular.
9798 * @note It is not possible to enable both ADC group injected
9799 * auto-injected mode and sequencer discontinuous mode.
9800 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
9801 * @param ADCx ADC instance
9802 * @param TrigAuto This parameter can be one of the following values:
9803 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
9804 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
9805 * @retval None
9806 */
9808 {
9810 }
9812 /**
9813 * @brief Get ADC group injected conversion trigger:
9814 * independent or from ADC group regular.
9815 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
9816 * @param ADCx ADC instance
9817 * @retval Returned value can be one of the following values:
9818 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
9819 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
9820 */
9822 {
9824 }
9826 /**
9827 * @brief Set ADC group injected offset.
9828 * @note It sets:
9829 * - ADC group injected rank to which the offset programmed
9830 * will be applied
9831 * - Offset level (offset to be subtracted from the raw
9832 * converted data).
9833 * Caution: Offset format is dependent to ADC resolution:
9834 * offset has to be left-aligned on bit 11, the LSB (right bits)
9835 * are set to 0.
9836 * @note Offset cannot be enabled or disabled.
9837 * To emulate offset disabled, set an offset value equal to 0.
9838 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
9839 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
9840 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
9841 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
9842 * @param ADCx ADC instance
9843 * @param Rank This parameter can be one of the following values:
9844 * @arg @ref LL_ADC_INJ_RANK_1
9845 * @arg @ref LL_ADC_INJ_RANK_2
9846 * @arg @ref LL_ADC_INJ_RANK_3
9847 * @arg @ref LL_ADC_INJ_RANK_4
9848 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
9849 * @retval None
9850 */
9851 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
9852 {
9853 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
9856 ADC_JOFR1_JOFFSET1,
9857 OffsetLevel);
9858 }
9860 /**
9861 * @brief Get ADC group injected offset.
9862 * @note It gives offset level (offset to be subtracted from the raw converted data).
9863 * Caution: Offset format is dependent to ADC resolution:
9864 * offset has to be left-aligned on bit 11, the LSB (right bits)
9865 * are set to 0.
9866 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
9867 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
9868 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
9869 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
9870 * @param ADCx ADC instance
9871 * @param Rank This parameter can be one of the following values:
9872 * @arg @ref LL_ADC_INJ_RANK_1
9873 * @arg @ref LL_ADC_INJ_RANK_2
9874 * @arg @ref LL_ADC_INJ_RANK_3
9875 * @arg @ref LL_ADC_INJ_RANK_4
9876 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
9877 */
9879 {
9880 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
9883 ADC_JOFR1_JOFFSET1)
9884 );
9885 }
9887 /**
9888 * @}
9889 */
9891 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
9892 * @{
9893 */
9895 /**
9896 * @brief Set sampling time of the selected ADC channel
9897 * Unit: ADC clock cycles.
9898 * @note On this device, sampling time is on channel scope: independently
9899 * of channel mapped on ADC group regular or injected.
9900 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
9901 * converted:
9902 * sampling time constraints must be respected (sampling time can be
9903 * adjusted in function of ADC clock frequency and sampling time
9904 * setting).
9905 * Refer to device datasheet for timings values (parameters TS_vrefint,
9906 * TS_temp, ...).
9907 * @note Conversion time is the addition of sampling time and processing time.
9908 * Refer to reference manual for ADC processing time of
9909 * this STM32 serie.
9910 * @note In case of ADC conversion of internal channel (VrefInt,
9911 * temperature sensor, ...), a sampling time minimum value
9912 * is required.
9913 * Refer to device datasheet.
9914 * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
9915 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
9916 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
9917 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
9918 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
9919 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
9920 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
9921 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
9922 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
9923 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
9924 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
9925 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
9926 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
9927 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
9928 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
9929 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
9930 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
9931 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
9932 * @param ADCx ADC instance
9933 * @param Channel This parameter can be one of the following values:
9934 * @arg @ref LL_ADC_CHANNEL_0
9935 * @arg @ref LL_ADC_CHANNEL_1
9936 * @arg @ref LL_ADC_CHANNEL_2
9937 * @arg @ref LL_ADC_CHANNEL_3
9938 * @arg @ref LL_ADC_CHANNEL_4
9939 * @arg @ref LL_ADC_CHANNEL_5
9940 * @arg @ref LL_ADC_CHANNEL_6
9941 * @arg @ref LL_ADC_CHANNEL_7
9942 * @arg @ref LL_ADC_CHANNEL_8
9943 * @arg @ref LL_ADC_CHANNEL_9
9944 * @arg @ref LL_ADC_CHANNEL_10
9945 * @arg @ref LL_ADC_CHANNEL_11
9946 * @arg @ref LL_ADC_CHANNEL_12
9947 * @arg @ref LL_ADC_CHANNEL_13
9948 * @arg @ref LL_ADC_CHANNEL_14
9949 * @arg @ref LL_ADC_CHANNEL_15
9950 * @arg @ref LL_ADC_CHANNEL_16
9951 * @arg @ref LL_ADC_CHANNEL_17
9952 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9953 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9954 *
9955 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9956 * @param SamplingTime This parameter can be one of the following values:
9957 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
9958 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
9959 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
9960 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
9961 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
9962 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
9963 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
9964 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
9965 * @retval None
9966 */
9967 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
9968 {
9969 /* Set bits with content of parameter "SamplingTime" with bits position */
9970 /* in register and register position depending on parameter "Channel". */
9971 /* Parameter "Channel" is used with masks because containing */
9972 /* other bits reserved for other purpose. */
9973 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
9978 }
9980 /**
9981 * @brief Get sampling time of the selected ADC channel
9982 * Unit: ADC clock cycles.
9983 * @note On this device, sampling time is on channel scope: independently
9984 * of channel mapped on ADC group regular or injected.
9985 * @note Conversion time is the addition of sampling time and processing time.
9986 * Refer to reference manual for ADC processing time of
9987 * this STM32 serie.
9988 * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
9989 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
9990 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
9991 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
9992 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
9993 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
9994 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
9995 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
9996 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
9997 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
9998 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
9999 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
10000 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
10001 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
10002 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
10003 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
10004 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
10005 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
10006 * @param ADCx ADC instance
10007 * @param Channel This parameter can be one of the following values:
10008 * @arg @ref LL_ADC_CHANNEL_0
10009 * @arg @ref LL_ADC_CHANNEL_1
10010 * @arg @ref LL_ADC_CHANNEL_2
10011 * @arg @ref LL_ADC_CHANNEL_3
10012 * @arg @ref LL_ADC_CHANNEL_4
10013 * @arg @ref LL_ADC_CHANNEL_5
10014 * @arg @ref LL_ADC_CHANNEL_6
10015 * @arg @ref LL_ADC_CHANNEL_7
10016 * @arg @ref LL_ADC_CHANNEL_8
10017 * @arg @ref LL_ADC_CHANNEL_9
10018 * @arg @ref LL_ADC_CHANNEL_10
10019 * @arg @ref LL_ADC_CHANNEL_11
10020 * @arg @ref LL_ADC_CHANNEL_12
10021 * @arg @ref LL_ADC_CHANNEL_13
10022 * @arg @ref LL_ADC_CHANNEL_14
10023 * @arg @ref LL_ADC_CHANNEL_15
10024 * @arg @ref LL_ADC_CHANNEL_16
10025 * @arg @ref LL_ADC_CHANNEL_17
10026 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
10027 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
10028 *
10029 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10030 * @retval Returned value can be one of the following values:
10031 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
10032 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
10033 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
10034 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
10035 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
10036 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
10037 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
10038 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
10039 */
10041 {
10042 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
10047 );
10048 }
10050 /**
10051 * @}
10052 */
10054 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
10055 * @{
10056 */
10058 /**
10059 * @brief Set ADC analog watchdog monitored channels:
10060 * a single channel or all channels,
10061 * on ADC groups regular and-or injected.
10062 * @note Once monitored channels are selected, analog watchdog
10063 * is enabled.
10064 * @note In case of need to define a single channel to monitor
10065 * with analog watchdog from sequencer channel definition,
10066 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
10067 * @note On this STM32 serie, there is only 1 kind of analog watchdog
10068 * instance:
10069 * - AWD standard (instance AWD1):
10070 * - channels monitored: can monitor 1 channel or all channels.
10071 * - groups monitored: ADC groups regular and-or injected.
10072 * - resolution: resolution is not limited (corresponds to
10073 * ADC resolution configured).
10074 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
10075 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
10076 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
10077 * @param ADCx ADC instance
10078 * @param AWDChannelGroup This parameter can be one of the following values:
10079 * @arg @ref LL_ADC_AWD_DISABLE
10080 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10081 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10082 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10083 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10084 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10085 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10086 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10087 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10088 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10089 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10090 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10091 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10092 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10093 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10094 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10095 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10096 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10097 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10098 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10099 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10100 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10101 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10102 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10103 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10104 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10105 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10106 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10107 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10108 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10109 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10110 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10111 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10112 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10113 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10114 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10115 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10116 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10117 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10118 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10119 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10120 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10121 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10122 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10123 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10124 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10125 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10126 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10127 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10128 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10129 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10130 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10131 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10132 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10133 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10134 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10135 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10136 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10137 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
10138 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
10139 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
10140 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
10141 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
10142 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
10143 *
10144 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10145 * @retval None
10146 */
10147 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
10148 {
10151 AWDChannelGroup);
10152 }
10154 /**
10155 * @brief Get ADC analog watchdog monitored channel.
10156 * @note Usage of the returned channel number:
10157 * - To reinject this channel into another function LL_ADC_xxx:
10158 * the returned channel number is only partly formatted on definition
10159 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
10160 * with parts of literals LL_ADC_CHANNEL_x or using
10161 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10162 * Then the selected literal LL_ADC_CHANNEL_x can be used
10163 * as parameter for another function.
10164 * - To get the channel number in decimal format:
10165 * process the returned value with the helper macro
10166 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10167 * Applicable only when the analog watchdog is set to monitor
10168 * one channel.
10169 * @note On this STM32 serie, there is only 1 kind of analog watchdog
10170 * instance:
10171 * - AWD standard (instance AWD1):
10172 * - channels monitored: can monitor 1 channel or all channels.
10173 * - groups monitored: ADC groups regular and-or injected.
10174 * - resolution: resolution is not limited (corresponds to
10175 * ADC resolution configured).
10176 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
10177 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
10178 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
10179 * @param ADCx ADC instance
10180 * @retval Returned value can be one of the following values:
10181 * @arg @ref LL_ADC_AWD_DISABLE
10182 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10183 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10184 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10185 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10186 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10187 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10188 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10189 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10190 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10191 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10192 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10193 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10194 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10195 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10196 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10197 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10198 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10199 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10200 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10201 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10202 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10203 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10204 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10205 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10206 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10207 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10208 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10209 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10210 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10211 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10212 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10213 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10214 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10215 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10216 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10217 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10218 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10219 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10220 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10221 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10222 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10223 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10224 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10225 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10226 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10227 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10228 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10229 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10230 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10231 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10232 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10233 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10234 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10235 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10236 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10237 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10238 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10239 */
10241 {
10242 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
10243 }
10245 /**
10246 * @brief Set ADC analog watchdog threshold value of threshold
10247 * high or low.
10248 * @note On this STM32 serie, there is only 1 kind of analog watchdog
10249 * instance:
10250 * - AWD standard (instance AWD1):
10251 * - channels monitored: can monitor 1 channel or all channels.
10252 * - groups monitored: ADC groups regular and-or injected.
10253 * - resolution: resolution is not limited (corresponds to
10254 * ADC resolution configured).
10255 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
10256 * LTR LT LL_ADC_SetAnalogWDThresholds
10257 * @param ADCx ADC instance
10258 * @param AWDThresholdsHighLow This parameter can be one of the following values:
10259 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10260 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10261 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
10262 * @retval None
10263 */
10264 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
10265 {
10269 ADC_HTR_HT,
10270 AWDThresholdValue);
10271 }
10273 /**
10274 * @brief Get ADC analog watchdog threshold value of threshold high or
10275 * threshold low.
10276 * @note In case of ADC resolution different of 12 bits,
10277 * analog watchdog thresholds data require a specific shift.
10278 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
10279 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
10280 * LTR LT LL_ADC_GetAnalogWDThresholds
10281 * @param ADCx ADC instance
10282 * @param AWDThresholdsHighLow This parameter can be one of the following values:
10283 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10284 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10285 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10286 */
10287 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
10288 {
10292 }
10294 /**
10295 * @}
10296 */
10298 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
10299 * @{
10300 */
10302 /**
10303 * @brief Enable the selected ADC instance.
10304 * @note On this STM32 serie, after ADC enable, a delay for
10305 * ADC internal analog stabilization is required before performing a
10306 * ADC conversion start.
10307 * Refer to device datasheet, parameter tSTAB.
10308 * @rmtoll CR2 ADON LL_ADC_Enable
10309 * @param ADCx ADC instance
10310 * @retval None
10311 */
10313 {
10315 }
10317 /**
10318 * @brief Disable the selected ADC instance.
10319 * @rmtoll CR2 ADON LL_ADC_Disable
10320 * @param ADCx ADC instance
10321 * @retval None
10322 */
10324 {
10326 }
10328 /**
10329 * @brief Get the selected ADC instance enable state.
10330 * @rmtoll CR2 ADON LL_ADC_IsEnabled
10331 * @param ADCx ADC instance
10332 * @retval 0: ADC is disabled, 1: ADC is enabled.
10333 */
10335 {
10337 }
10339 /**
10340 * @brief Start ADC calibration in the mode single-ended
10341 * or differential (for devices with differential mode available).
10342 * @note On this STM32 serie, before starting a calibration,
10343 * ADC must be disabled.
10344 * A minimum number of ADC clock cycles are required
10345 * between ADC disable state and calibration start.
10346 * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
10347 * @note On this STM32 serie, hardware prerequisite before starting a calibration:
10348 the ADC must have been in power-on state for at least
10349 two ADC clock cycles.
10350 * @rmtoll CR2 CAL LL_ADC_StartCalibration
10351 * @param ADCx ADC instance
10352 * @retval None
10353 */
10355 {
10357 }
10359 /**
10360 * @brief Get ADC calibration state.
10361 * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
10362 * @param ADCx ADC instance
10363 * @retval 0: calibration complete, 1: calibration in progress.
10364 */
10366 {
10368 }
10370 /**
10371 * @}
10372 */
10374 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
10375 * @{
10376 */
10378 /**
10379 * @brief Start ADC group regular conversion.
10380 * @note On this STM32 serie, this function is relevant for both
10381 * internal trigger (SW start) and external trigger:
10382 * - If ADC trigger has been set to software start, ADC conversion
10383 * starts immediately.
10384 * - If ADC trigger has been set to external trigger, ADC conversion
10385 * will start at next trigger event (on the selected trigger edge)
10386 * following the ADC start conversion command.
10387 * @rmtoll CR2 EXTTRIG LL_ADC_REG_StartConversion
10388 * @param ADCx ADC instance
10389 * @retval None
10390 */
10392 {
10393 /* Note: Set bit ADC_CR2_SWSTART for case of trigger source set to */
10394 /* SW start. In case of external trigger selected, this bit */
10395 /* has no effect. */
10397 }
10399 /**
10400 * @brief Stop ADC group regular conversion from external trigger.
10401 * @note No more ADC conversion will start at next trigger event
10402 * following the ADC stop conversion command.
10403 * If a conversion is on-going, it will be completed.
10404 * @note On this STM32 serie, there is no specific command
10405 * to stop a conversion on-going or to stop ADC converting
10406 * in continuous mode. These actions can be performed
10407 * using function @ref LL_ADC_Disable().
10408 * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
10409 * @param ADCx ADC instance
10410 * @retval None
10411 */
10413 {
10415 }
10417 /**
10418 * @brief Get ADC group regular conversion data, range fit for
10419 * all ADC configurations: all ADC resolutions and
10420 * all oversampling increased data width (for devices
10421 * with feature oversampling).
10422 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
10423 * @param ADCx ADC instance
10424 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10425 */
10427 {
10429 }
10431 /**
10432 * @brief Get ADC group regular conversion data, range fit for
10433 * ADC resolution 12 bits.
10434 * @note For devices with feature oversampling: Oversampling
10435 * can increase data width, function for extended range
10436 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
10437 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
10438 * @param ADCx ADC instance
10439 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10440 */
10442 {
10444 }
10446 /**
10447 * @}
10448 */
10450 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
10451 * @{
10452 */
10454 /**
10455 * @brief Start ADC group injected conversion.
10456 * @note On this STM32 serie, this function is relevant for both
10457 * internal trigger (SW start) and external trigger:
10458 * - If ADC trigger has been set to software start, ADC conversion
10459 * starts immediately.
10460 * - If ADC trigger has been set to external trigger, ADC conversion
10461 * will start at next trigger event (on the selected trigger edge)
10462 * following the ADC start conversion command.
10463 * @rmtoll CR2 JEXTTRIG LL_ADC_REG_StartConversion
10464 * @param ADCx ADC instance
10465 * @retval None
10466 */
10468 {
10469 /* Note: Set bit ADC_CR2_JSWSTART for case of trigger source set to */
10470 /* SW start. In case of external trigger selected, this bit */
10471 /* has no effect. */
10473 }
10475 /**
10476 * @brief Stop ADC group injected conversion from external trigger.
10477 * @note No more ADC conversion will start at next trigger event
10478 * following the ADC stop conversion command.
10479 * If a conversion is on-going, it will be completed.
10480 * @note On this STM32 serie, there is no specific command
10481 * to stop a conversion on-going or to stop ADC converting
10482 * in continuous mode. These actions can be performed
10483 * using function @ref LL_ADC_Disable().
10484 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
10485 * @param ADCx ADC instance
10486 * @retval None
10487 */
10489 {
10491 }
10493 /**
10494 * @brief Get ADC group regular conversion data, range fit for
10495 * all ADC configurations: all ADC resolutions and
10496 * all oversampling increased data width (for devices
10497 * with feature oversampling).
10498 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
10499 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
10500 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
10501 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
10502 * @param ADCx ADC instance
10503 * @param Rank This parameter can be one of the following values:
10504 * @arg @ref LL_ADC_INJ_RANK_1
10505 * @arg @ref LL_ADC_INJ_RANK_2
10506 * @arg @ref LL_ADC_INJ_RANK_3
10507 * @arg @ref LL_ADC_INJ_RANK_4
10508 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10509 */
10511 {
10512 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10515 ADC_JDR1_JDATA)
10516 );
10517 }
10519 /**
10520 * @brief Get ADC group injected conversion data, range fit for
10521 * ADC resolution 12 bits.
10522 * @note For devices with feature oversampling: Oversampling
10523 * can increase data width, function for extended range
10524 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
10525 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
10526 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
10527 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
10528 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
10529 * @param ADCx ADC instance
10530 * @param Rank This parameter can be one of the following values:
10531 * @arg @ref LL_ADC_INJ_RANK_1
10532 * @arg @ref LL_ADC_INJ_RANK_2
10533 * @arg @ref LL_ADC_INJ_RANK_3
10534 * @arg @ref LL_ADC_INJ_RANK_4
10535 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10536 */
10538 {
10539 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10542 ADC_JDR1_JDATA)
10543 );
10544 }
10546 /**
10547 * @}
10548 */
10550 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
10551 * @{
10552 */
10554 /**
10555 * @brief Get flag ADC group regular end of sequence conversions.
10556 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
10557 * @param ADCx ADC instance
10558 * @retval State of bit (1 or 0).
10559 */
10561 {
10562 /* Note: on this STM32 serie, there is no flag ADC group regular */
10563 /* end of unitary conversion. */
10564 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10565 /* in other STM32 families). */
10567 }
10570 /**
10571 * @brief Get flag ADC group injected end of sequence conversions.
10572 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
10573 * @param ADCx ADC instance
10574 * @retval State of bit (1 or 0).
10575 */
10577 {
10578 /* Note: on this STM32 serie, there is no flag ADC group injected */
10579 /* end of unitary conversion. */
10580 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10581 /* in other STM32 families). */
10583 }
10585 /**
10586 * @brief Get flag ADC analog watchdog 1 flag
10587 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
10588 * @param ADCx ADC instance
10589 * @retval State of bit (1 or 0).
10590 */
10592 {
10594 }
10596 /**
10597 * @brief Clear flag ADC group regular end of sequence conversions.
10598 * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
10599 * @param ADCx ADC instance
10600 * @retval None
10601 */
10603 {
10604 /* Note: on this STM32 serie, there is no flag ADC group regular */
10605 /* end of unitary conversion. */
10606 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10607 /* in other STM32 families). */
10609 }
10612 /**
10613 * @brief Clear flag ADC group injected end of sequence conversions.
10614 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
10615 * @param ADCx ADC instance
10616 * @retval None
10617 */
10619 {
10620 /* Note: on this STM32 serie, there is no flag ADC group injected */
10621 /* end of unitary conversion. */
10622 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10623 /* in other STM32 families). */
10625 }
10627 /**
10628 * @brief Clear flag ADC analog watchdog 1.
10629 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
10630 * @param ADCx ADC instance
10631 * @retval None
10632 */
10634 {
10636 }
10638 /**
10639 * @}
10640 */
10642 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
10643 * @{
10644 */
10646 /**
10647 * @brief Enable interruption ADC group regular end of sequence conversions.
10648 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
10649 * @param ADCx ADC instance
10650 * @retval None
10651 */
10653 {
10654 /* Note: on this STM32 serie, there is no flag ADC group regular */
10655 /* end of unitary conversion. */
10656 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10657 /* in other STM32 families). */
10659 }
10662 /**
10663 * @brief Enable interruption ADC group injected end of sequence conversions.
10664 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10665 * @param ADCx ADC instance
10666 * @retval None
10667 */
10669 {
10670 /* Note: on this STM32 serie, there is no flag ADC group injected */
10671 /* end of unitary conversion. */
10672 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10673 /* in other STM32 families). */
10675 }
10677 /**
10678 * @brief Enable interruption ADC analog watchdog 1.
10679 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10680 * @param ADCx ADC instance
10681 * @retval None
10682 */
10684 {
10686 }
10688 /**
10689 * @brief Disable interruption ADC group regular end of sequence conversions.
10690 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
10691 * @param ADCx ADC instance
10692 * @retval None
10693 */
10695 {
10696 /* Note: on this STM32 serie, there is no flag ADC group regular */
10697 /* end of unitary conversion. */
10698 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10699 /* in other STM32 families). */
10701 }
10704 /**
10705 * @brief Disable interruption ADC group injected end of sequence conversions.
10706 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10707 * @param ADCx ADC instance
10708 * @retval None
10709 */
10711 {
10712 /* Note: on this STM32 serie, there is no flag ADC group injected */
10713 /* end of unitary conversion. */
10714 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10715 /* in other STM32 families). */
10717 }
10719 /**
10720 * @brief Disable interruption ADC analog watchdog 1.
10721 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10722 * @param ADCx ADC instance
10723 * @retval None
10724 */
10726 {
10728 }
10730 /**
10731 * @brief Get state of interruption ADC group regular end of sequence conversions
10732 * (0: interrupt disabled, 1: interrupt enabled).
10733 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
10734 * @param ADCx ADC instance
10735 * @retval State of bit (1 or 0).
10736 */
10738 {
10739 /* Note: on this STM32 serie, there is no flag ADC group regular */
10740 /* end of unitary conversion. */
10741 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10742 /* in other STM32 families). */
10744 }
10747 /**
10748 * @brief Get state of interruption ADC group injected end of sequence conversions
10749 * (0: interrupt disabled, 1: interrupt enabled).
10750 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10751 * @param ADCx ADC instance
10752 * @retval State of bit (1 or 0).
10753 */
10755 {
10756 /* Note: on this STM32 serie, there is no flag ADC group injected */
10757 /* end of unitary conversion. */
10758 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10759 /* in other STM32 families). */
10761 }
10763 /**
10764 * @brief Get state of interruption ADC analog watchdog 1
10765 * (0: interrupt disabled, 1: interrupt enabled).
10766 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10767 * @param ADCx ADC instance
10768 * @retval State of bit (1 or 0).
10769 */
10771 {
10773 }
10775 /**
10776 * @}
10777 */
10779 #if defined(USE_FULL_LL_DRIVER)
10780 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
10781 * @{
10782 */
10784 /* Initialization of some features of ADC common parameters and multimode */
10785 /* Note: On STM32F37x ADC, there is no ADC common initialization */
10786 /* function. */
10789 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
10790 /* (availability of ADC group injected depends on STM32 families) */
10793 /* Initialization of some features of ADC instance */
10797 /* Initialization of some features of ADC instance and ADC group regular */
10801 /* Initialization of some features of ADC instance and ADC group injected */
10805 /**
10806 * @}
10807 */
10810 /**
10811 * @}
10812 */
10814 /**
10815 * @}
10816 */
10823 /**
10824 * @}
10825 */
10827 #ifdef __cplusplus
10828 }
10829 #endif
10833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/