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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_dac.h
blob26e78081756d63ae57393d4ae95b761bbe1b3c3a
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_DAC_H
38 #define __STM32F3xx_LL_DAC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx.h"
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 #if defined (DAC1) || defined (DAC2)
52
53 /** @defgroup DAC_LL DAC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
62 * @{
63 */
64
65 /* Internal masks for DAC channels definition */
66 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
67 /* - channel bits position into register CR */
68 /* - channel bits position into register SWTRIG */
69 /* - channel register offset of data holding register DHRx */
70 /* - channel register offset of data output register DORx */
71 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
72 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
73 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
74
75 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
76 #if defined(DAC_CHANNEL2_SUPPORT)
77 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
78 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
79 #else
80 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
81 #endif /* DAC_CHANNEL2_SUPPORT */
82
83 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
84 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
85 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
86 #if defined(DAC_CHANNEL2_SUPPORT)
87 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
88 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
89 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
90 #endif /* DAC_CHANNEL2_SUPPORT */
91 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
92 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
93 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
94 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
95
96 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
97 #if defined(DAC_CHANNEL2_SUPPORT)
98 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
99 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
100 #else
101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
102 #endif /* DAC_CHANNEL2_SUPPORT */
103
104 /* DAC registers bits positions */
105 #if defined(DAC_CHANNEL2_SUPPORT)
106 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
107 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
108 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
109 #endif /* DAC_CHANNEL2_SUPPORT */
110
111 /* Miscellaneous data */
112 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
113
114 /**
115 * @}
116 */
117
118
119 /* Private macros ------------------------------------------------------------*/
120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
121 * @{
122 */
123
124 /**
125 * @brief Driver macro reserved for internal use: isolate bits with the
126 * selected mask and shift them to the register LSB
127 * (shift mask on register position bit 0).
128 * @param __BITS__ Bits in register 32 bits
129 * @param __MASK__ Mask in register 32 bits
130 * @retval Bits in register 32 bits
131 */
132 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
133 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
134
135 /**
136 * @brief Driver macro reserved for internal use: set a pointer to
137 * a register from a register basis from which an offset
138 * is applied.
139 * @param __REG__ Register basis from which the offset is applied.
140 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
141 * @retval Pointer to register address
142 */
143 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
144 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
145
146 /**
147 * @}
148 */
149
150
151 /* Exported types ------------------------------------------------------------*/
152 #if defined(USE_FULL_LL_DRIVER)
153 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
154 * @{
155 */
156
157 /**
158 * @brief Structure definition of some features of DAC instance.
159 */
160 typedef struct
161 {
162 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
163 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
164
165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
166
167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
169
170 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
171
172 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
173 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
174 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
175 @note If waveform automatic generation mode is disabled, this parameter is discarded.
176
177 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
178
179 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
180 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
181
182 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
183
184 } LL_DAC_InitTypeDef;
185
186 /**
187 * @}
188 */
189 #endif /* USE_FULL_LL_DRIVER */
190
191 /* Exported constants --------------------------------------------------------*/
192 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
193 * @{
194 */
195
196 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
197 * @brief Flags defines which can be used with LL_DAC_ReadReg function
198 * @{
199 */
200 /* DAC channel 1 flags */
201 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
202
203 #if defined(DAC_CHANNEL2_SUPPORT)
204 /* DAC channel 2 flags */
205 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
206 #endif /* DAC_CHANNEL2_SUPPORT */
207 /**
208 * @}
209 */
210
211 /** @defgroup DAC_LL_EC_IT DAC interruptions
212 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
213 * @{
214 */
215 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
216 #if defined(DAC_CHANNEL2_SUPPORT)
217 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
218 #endif /* DAC_CHANNEL2_SUPPORT */
219 /**
220 * @}
221 */
222
223 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
224 * @{
225 */
226 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
227 #if defined(DAC_CHANNEL2_SUPPORT)
228 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
229 #endif /* DAC_CHANNEL2_SUPPORT */
230 /**
231 * @}
232 */
233
234 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
235 * @{
236 */
237 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
238 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
239 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
240 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
241 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
242 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
246 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
247
248 #elif defined(STM32F303x8) || defined(STM32F328xx)
249 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
250 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
251 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
252 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
253 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
254 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
255
256 #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
257 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
258 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
259 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
260 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
261 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
262 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
263
264 #elif defined(STM32F301x8) || defined(STM32F318xx)
265 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
266 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
267 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
268 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
269
270 #elif defined(STM32F373xC) || defined(STM32F378xx)
271 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
272 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
273 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
274 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
275 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
276 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
277 #define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
278 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
279
280 #elif defined(STM32F334x8)
281 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
282 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
283 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
284 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
285 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
286 #define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
287 #define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
288 #define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
289 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
290
291 #endif
292 /**
293 * @}
294 */
295
296 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
297 * @{
298 */
299 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
300 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
301 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
302 /**
303 * @}
304 */
305
306 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
307 * @{
308 */
309 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
321 /**
322 * @}
323 */
324
325 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
326 * @{
327 */
328 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
329 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
330 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
331 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
340 /**
341 * @}
342 */
343
344 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
345 * @{
346 */
347 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
348 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
349
350 #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
351 #define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
352 #define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
353 #endif
354 /**
355 * @}
356 */
357
358
359 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
360 * @{
361 */
362 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
363 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
364 /**
365 * @}
366 */
367
368 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
369 * @{
370 */
371 /* List of DAC registers intended to be used (most commonly) with */
372 /* DMA transfer. */
373 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
374 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
375 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
376 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
377 /**
378 * @}
379 */
380
381 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
382 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
383 * not timeout values.
384 * For details on delays values, refer to descriptions in source code
385 * above each literal definition.
386 * @{
387 */
388
389 /* Delay for DAC channel voltage settling time from DAC channel startup */
390 /* (transition from disable to enable). */
391 /* Note: DAC channel startup time depends on board application environment: */
392 /* impedance connected to DAC channel output. */
393 /* The delay below is specified under conditions: */
394 /* - voltage maximum transition (lowest to highest value) */
395 /* - until voltage reaches final value +-1LSB */
396 /* - DAC channel output buffer enabled */
397 /* - load impedance of 5kOhm (min), 50pF (max) */
398 /* Literal set to maximum value (refer to device datasheet, */
399 /* parameter "tWAKEUP"). */
400 /* Unit: us */
401 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
402
403 /* Delay for DAC channel voltage settling time. */
404 /* Note: DAC channel startup time depends on board application environment: */
405 /* impedance connected to DAC channel output. */
406 /* The delay below is specified under conditions: */
407 /* - voltage maximum transition (lowest to highest value) */
408 /* - until voltage reaches final value +-1LSB */
409 /* - DAC channel output buffer enabled */
410 /* - load impedance of 5kOhm min, 50pF max */
411 /* Literal set to maximum value (refer to device datasheet, */
412 /* parameter "tSETTLING"). */
413 /* Unit: us */
414 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
415 /**
416 * @}
417 */
418
419 /**
420 * @}
421 */
422
423 /* Exported macro ------------------------------------------------------------*/
424 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
425 * @{
426 */
427
428 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
429 * @{
430 */
431
432 /**
433 * @brief Write a value in DAC register
434 * @param __INSTANCE__ DAC Instance
435 * @param __REG__ Register to be written
436 * @param __VALUE__ Value to be written in the register
437 * @retval None
438 */
439 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
440
441 /**
442 * @brief Read a value in DAC register
443 * @param __INSTANCE__ DAC Instance
444 * @param __REG__ Register to be read
445 * @retval Register value
446 */
447 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
448
449 /**
450 * @}
451 */
452
453 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
454 * @{
455 */
456
457 /**
458 * @brief Helper macro to get DAC channel number in decimal format
459 * from literals LL_DAC_CHANNEL_x.
460 * Example:
461 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
462 * will return decimal number "1".
463 * @note The input can be a value from functions where a channel
464 * number is returned.
465 * @param __CHANNEL__ This parameter can be one of the following values:
466 * @arg @ref LL_DAC_CHANNEL_1
467 * @arg @ref LL_DAC_CHANNEL_2 (1)
468 *
469 * (1) On this STM32 serie, parameter not available on all devices.
470 * Refer to device datasheet for channels availability.
471 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
472 */
473 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
474 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
475
476 /**
477 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
478 * from number in decimal format.
479 * Example:
480 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
481 * will return a data equivalent to "LL_DAC_CHANNEL_1".
482 * @note If the input parameter does not correspond to a DAC channel,
483 * this macro returns value '0'.
484 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
485 * @retval Returned value can be one of the following values:
486 * @arg @ref LL_DAC_CHANNEL_1
487 * @arg @ref LL_DAC_CHANNEL_2 (1)
488 *
489 * (1) On this STM32 serie, parameter not available on all devices.
490 * Refer to device datasheet for channels availability.
491 */
492 #if defined(DAC_CHANNEL2_SUPPORT)
493 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
494 (((__DECIMAL_NB__) == 1U) \
495 ? ( \
496 LL_DAC_CHANNEL_1 \
497 ) \
498 : \
499 (((__DECIMAL_NB__) == 2U) \
500 ? ( \
501 LL_DAC_CHANNEL_2 \
502 ) \
503 : \
504 ( \
505 0 \
506 ) \
507 ) \
508 )
509 #else
510 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
511 (((__DECIMAL_NB__) == 1U) \
512 ? ( \
513 LL_DAC_CHANNEL_1 \
514 ) \
515 : \
516 ( \
517 0 \
518 ) \
519 )
520 #endif /* DAC_CHANNEL2_SUPPORT */
521
522 /**
523 * @brief Helper macro to define the DAC conversion data full-scale digital
524 * value corresponding to the selected DAC resolution.
525 * @note DAC conversion data full-scale corresponds to voltage range
526 * determined by analog voltage references Vref+ and Vref-
527 * (refer to reference manual).
528 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
529 * @arg @ref LL_DAC_RESOLUTION_12B
530 * @arg @ref LL_DAC_RESOLUTION_8B
531 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
532 */
533 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
534 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
535
536 /**
537 * @brief Helper macro to calculate the DAC conversion data (unit: digital
538 * value) corresponding to a voltage (unit: mVolt).
539 * @note This helper macro is intended to provide input data in voltage
540 * rather than digital value,
541 * to be used with LL DAC functions such as
542 * @ref LL_DAC_ConvertData12RightAligned().
543 * @note Analog reference voltage (Vref+) must be either known from
544 * user board environment or can be calculated using ADC measurement
545 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
546 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
547 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
548 * (unit: mVolt).
549 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
550 * @arg @ref LL_DAC_RESOLUTION_12B
551 * @arg @ref LL_DAC_RESOLUTION_8B
552 * @retval DAC conversion data (unit: digital value)
553 */
554 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
555 __DAC_VOLTAGE__,\
556 __DAC_RESOLUTION__) \
557 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
558 / (__VREFANALOG_VOLTAGE__) \
559 )
560
561 /**
562 * @}
563 */
564
565 /**
566 * @}
567 */
568
569
570 /* Exported functions --------------------------------------------------------*/
571 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
572 * @{
573 */
574 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
575 * @{
576 */
577
578 /**
579 * @brief Set the conversion trigger source for the selected DAC channel.
580 * @note For conversion trigger source to be effective, DAC trigger
581 * must be enabled using function @ref LL_DAC_EnableTrigger().
582 * @note To set conversion trigger source, DAC channel must be disabled.
583 * Otherwise, the setting is discarded.
584 * @note Availability of parameters of trigger sources from timer
585 * depends on timers availability on the selected device.
586 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
587 * CR TSEL2 LL_DAC_SetTriggerSource
588 * @param DACx DAC instance
589 * @param DAC_Channel This parameter can be one of the following values:
590 * @arg @ref LL_DAC_CHANNEL_1
591 * @arg @ref LL_DAC_CHANNEL_2 (1)
592 *
593 * (1) On this STM32 serie, parameter not available on all devices.
594 * Refer to device datasheet for channels availability.
595 * @param TriggerSource This parameter can be one of the following values:
596 * @arg @ref LL_DAC_TRIG_SOFTWARE
597 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
598 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
599 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
600 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
601 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
602 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
603 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
604 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
605 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
606 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
607 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
608 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
609 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
610 *
611 * (1) On STM32F3, parameter not available on all devices
612 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
613 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
614 * @retval None
615 */
616 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
617 {
618 MODIFY_REG(DACx->CR,
619 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
620 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
621 }
622
623 /**
624 * @brief Get the conversion trigger source for the selected DAC channel.
625 * @note For conversion trigger source to be effective, DAC trigger
626 * must be enabled using function @ref LL_DAC_EnableTrigger().
627 * @note Availability of parameters of trigger sources from timer
628 * depends on timers availability on the selected device.
629 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
630 * CR TSEL2 LL_DAC_GetTriggerSource
631 * @param DACx DAC instance
632 * @param DAC_Channel This parameter can be one of the following values:
633 * @arg @ref LL_DAC_CHANNEL_1
634 * @arg @ref LL_DAC_CHANNEL_2 (1)
635 *
636 * (1) On this STM32 serie, parameter not available on all devices.
637 * Refer to device datasheet for channels availability.
638 * @retval Returned value can be one of the following values:
639 * @arg @ref LL_DAC_TRIG_SOFTWARE
640 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
641 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
642 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
643 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
644 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
645 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
646 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
647 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
648 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
649 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
650 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
651 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
652 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
653 *
654 * (1) On STM32F3, parameter not available on all devices
655 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
656 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
657 */
658 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
659 {
660 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
661 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
662 );
663 }
664
665 /**
666 * @brief Set the waveform automatic generation mode
667 * for the selected DAC channel.
668 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
669 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
670 * @param DACx DAC instance
671 * @param DAC_Channel This parameter can be one of the following values:
672 * @arg @ref LL_DAC_CHANNEL_1
673 * @arg @ref LL_DAC_CHANNEL_2 (1)
674 *
675 * (1) On this STM32 serie, parameter not available on all devices.
676 * Refer to device datasheet for channels availability.
677 * @param WaveAutoGeneration This parameter can be one of the following values:
678 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
679 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
680 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
681 * @retval None
682 */
683 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
684 {
685 MODIFY_REG(DACx->CR,
686 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
687 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
688 }
689
690 /**
691 * @brief Get the waveform automatic generation mode
692 * for the selected DAC channel.
693 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
694 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
695 * @param DACx DAC instance
696 * @param DAC_Channel This parameter can be one of the following values:
697 * @arg @ref LL_DAC_CHANNEL_1
698 * @arg @ref LL_DAC_CHANNEL_2 (1)
699 *
700 * (1) On this STM32 serie, parameter not available on all devices.
701 * Refer to device datasheet for channels availability.
702 * @retval Returned value can be one of the following values:
703 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
704 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
705 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
706 */
707 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
708 {
709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
711 );
712 }
713
714 /**
715 * @brief Set the noise waveform generation for the selected DAC channel:
716 * Noise mode and parameters LFSR (linear feedback shift register).
717 * @note For wave generation to be effective, DAC channel
718 * wave generation mode must be enabled using
719 * function @ref LL_DAC_SetWaveAutoGeneration().
720 * @note This setting can be set when the selected DAC channel is disabled
721 * (otherwise, the setting operation is ignored).
722 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
723 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
724 * @param DACx DAC instance
725 * @param DAC_Channel This parameter can be one of the following values:
726 * @arg @ref LL_DAC_CHANNEL_1
727 * @arg @ref LL_DAC_CHANNEL_2 (1)
728 *
729 * (1) On this STM32 serie, parameter not available on all devices.
730 * Refer to device datasheet for channels availability.
731 * @param NoiseLFSRMask This parameter can be one of the following values:
732 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
733 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
734 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
735 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
736 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
737 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
738 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
739 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
740 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
741 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
742 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
743 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
744 * @retval None
745 */
746 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
747 {
748 MODIFY_REG(DACx->CR,
749 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
750 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
751 }
752
753 /**
754 * @brief Set the noise waveform generation for the selected DAC channel:
755 * Noise mode and parameters LFSR (linear feedback shift register).
756 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
757 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
758 * @param DACx DAC instance
759 * @param DAC_Channel This parameter can be one of the following values:
760 * @arg @ref LL_DAC_CHANNEL_1
761 * @arg @ref LL_DAC_CHANNEL_2 (1)
762 *
763 * (1) On this STM32 serie, parameter not available on all devices.
764 * Refer to device datasheet for channels availability.
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
767 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
768 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
769 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
770 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
771 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
772 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
773 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
774 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
775 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
776 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
777 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
778 */
779 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
780 {
781 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
782 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
783 );
784 }
785
786 /**
787 * @brief Set the triangle waveform generation for the selected DAC channel:
788 * triangle mode and amplitude.
789 * @note For wave generation to be effective, DAC channel
790 * wave generation mode must be enabled using
791 * function @ref LL_DAC_SetWaveAutoGeneration().
792 * @note This setting can be set when the selected DAC channel is disabled
793 * (otherwise, the setting operation is ignored).
794 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
795 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
796 * @param DACx DAC instance
797 * @param DAC_Channel This parameter can be one of the following values:
798 * @arg @ref LL_DAC_CHANNEL_1
799 * @arg @ref LL_DAC_CHANNEL_2 (1)
800 *
801 * (1) On this STM32 serie, parameter not available on all devices.
802 * Refer to device datasheet for channels availability.
803 * @param TriangleAmplitude This parameter can be one of the following values:
804 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
805 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
806 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
807 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
808 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
809 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
810 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
811 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
812 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
813 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
814 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
815 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
816 * @retval None
817 */
818 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
819 {
820 MODIFY_REG(DACx->CR,
821 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
822 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
823 }
824
825 /**
826 * @brief Set the triangle waveform generation for the selected DAC channel:
827 * triangle mode and amplitude.
828 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
829 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
830 * @param DACx DAC instance
831 * @param DAC_Channel This parameter can be one of the following values:
832 * @arg @ref LL_DAC_CHANNEL_1
833 * @arg @ref LL_DAC_CHANNEL_2 (1)
834 *
835 * (1) On this STM32 serie, parameter not available on all devices.
836 * Refer to device datasheet for channels availability.
837 * @retval Returned value can be one of the following values:
838 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
839 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
840 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
841 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
842 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
843 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
844 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
845 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
846 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
847 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
848 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
849 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
850 */
851 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
852 {
853 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
854 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
855 );
856 }
857
858 /**
859 * @brief Set the output buffer for the selected DAC channel.
860 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
861 * CR BOFF2 LL_DAC_SetOutputBuffer
862 * @param DACx DAC instance
863 * @param DAC_Channel This parameter can be one of the following values:
864 * @arg @ref LL_DAC_CHANNEL_1
865 * @arg @ref LL_DAC_CHANNEL_2 (1)
866 *
867 * (1) On this STM32 serie, parameter not available on all devices.
868 * Refer to device datasheet for channels availability.
869 * @param OutputBuffer This parameter can be one of the following values:
870 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
871 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
872 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
873 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
874 *
875 * (1) Feature specific to STM32F303x6/8 and STM32F328:
876 * On DAC1 channel 2, output buffer is replaced by a switch
877 * to connect DAC channel output to pin PA5.
878 * On DAC2 channel 1, output buffer is replaced by a switch
879 * to connect DAC channel output to pin PA6.
880 * @retval None
881 */
882 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
883 {
884 MODIFY_REG(DACx->CR,
885 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
886 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
887 }
888
889 /**
890 * @brief Get the output buffer state for the selected DAC channel.
891 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
892 * CR BOFF2 LL_DAC_GetOutputBuffer
893 * @param DACx DAC instance
894 * @param DAC_Channel This parameter can be one of the following values:
895 * @arg @ref LL_DAC_CHANNEL_1
896 * @arg @ref LL_DAC_CHANNEL_2 (1)
897 *
898 * (1) On this STM32 serie, parameter not available on all devices.
899 * Refer to device datasheet for channels availability.
900 * @retval Returned value can be one of the following values:
901 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
902 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
903 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
904 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
905 *
906 * (1) Feature specific to STM32F303x6/8 and STM32F328:
907 * On DAC1 channel 2, output buffer is replaced by a switch
908 * to connect DAC channel output to pin PA5.
909 * On DAC2 channel 1, output buffer is replaced by a switch
910 * to connect DAC channel output to pin PA6.
911 */
912 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
913 {
914 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
915 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
916 );
917 }
918
919 /**
920 * @}
921 */
922
923 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
924 * @{
925 */
926
927 /**
928 * @brief Enable DAC DMA transfer request of the selected channel.
929 * @note To configure DMA source address (peripheral address),
930 * use function @ref LL_DAC_DMA_GetRegAddr().
931 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
932 * CR DMAEN2 LL_DAC_EnableDMAReq
933 * @param DACx DAC instance
934 * @param DAC_Channel This parameter can be one of the following values:
935 * @arg @ref LL_DAC_CHANNEL_1
936 * @arg @ref LL_DAC_CHANNEL_2 (1)
937 *
938 * (1) On this STM32 serie, parameter not available on all devices.
939 * Refer to device datasheet for channels availability.
940 * @retval None
941 */
942 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
943 {
944 SET_BIT(DACx->CR,
945 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
946 }
947
948 /**
949 * @brief Disable DAC DMA transfer request of the selected channel.
950 * @note To configure DMA source address (peripheral address),
951 * use function @ref LL_DAC_DMA_GetRegAddr().
952 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
953 * CR DMAEN2 LL_DAC_DisableDMAReq
954 * @param DACx DAC instance
955 * @param DAC_Channel This parameter can be one of the following values:
956 * @arg @ref LL_DAC_CHANNEL_1
957 * @arg @ref LL_DAC_CHANNEL_2 (1)
958 *
959 * (1) On this STM32 serie, parameter not available on all devices.
960 * Refer to device datasheet for channels availability.
961 * @retval None
962 */
963 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
964 {
965 CLEAR_BIT(DACx->CR,
966 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
967 }
968
969 /**
970 * @brief Get DAC DMA transfer request state of the selected channel.
971 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
972 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
973 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
974 * @param DACx DAC instance
975 * @param DAC_Channel This parameter can be one of the following values:
976 * @arg @ref LL_DAC_CHANNEL_1
977 * @arg @ref LL_DAC_CHANNEL_2 (1)
978 *
979 * (1) On this STM32 serie, parameter not available on all devices.
980 * Refer to device datasheet for channels availability.
981 * @retval State of bit (1 or 0).
982 */
983 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
984 {
985 return (READ_BIT(DACx->CR,
986 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
987 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
988 }
989
990 /**
991 * @brief Function to help to configure DMA transfer to DAC: retrieve the
992 * DAC register address from DAC instance and a list of DAC registers
993 * intended to be used (most commonly) with DMA transfer.
994 * @note These DAC registers are data holding registers:
995 * when DAC conversion is requested, DAC generates a DMA transfer
996 * request to have data available in DAC data holding registers.
997 * @note This macro is intended to be used with LL DMA driver, refer to
998 * function "LL_DMA_ConfigAddresses()".
999 * Example:
1000 * LL_DMA_ConfigAddresses(DMA1,
1001 * LL_DMA_CHANNEL_1,
1002 * (uint32_t)&< array or variable >,
1003 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1004 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1005 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1006 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1007 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1008 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1009 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1010 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1011 * @param DACx DAC instance
1012 * @param DAC_Channel This parameter can be one of the following values:
1013 * @arg @ref LL_DAC_CHANNEL_1
1014 * @arg @ref LL_DAC_CHANNEL_2 (1)
1015 *
1016 * (1) On this STM32 serie, parameter not available on all devices.
1017 * Refer to device datasheet for channels availability.
1018 * @param Register This parameter can be one of the following values:
1019 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1020 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1021 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1022 * @retval DAC register address
1023 */
1024 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1025 {
1026 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1027 /* DAC channel selected. */
1028 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
1029 }
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1035 * @{
1036 */
1037
1038 /**
1039 * @brief Enable DAC selected channel.
1040 * @rmtoll CR EN1 LL_DAC_Enable\n
1041 * CR EN2 LL_DAC_Enable
1042 * @note After enable from off state, DAC channel requires a delay
1043 * for output voltage to reach accuracy +/- 1 LSB.
1044 * Refer to device datasheet, parameter "tWAKEUP".
1045 * @param DACx DAC instance
1046 * @param DAC_Channel This parameter can be one of the following values:
1047 * @arg @ref LL_DAC_CHANNEL_1
1048 * @arg @ref LL_DAC_CHANNEL_2 (1)
1049 *
1050 * (1) On this STM32 serie, parameter not available on all devices.
1051 * Refer to device datasheet for channels availability.
1052 * @retval None
1053 */
1054 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1055 {
1056 SET_BIT(DACx->CR,
1057 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1058 }
1059
1060 /**
1061 * @brief Disable DAC selected channel.
1062 * @rmtoll CR EN1 LL_DAC_Disable\n
1063 * CR EN2 LL_DAC_Disable
1064 * @param DACx DAC instance
1065 * @param DAC_Channel This parameter can be one of the following values:
1066 * @arg @ref LL_DAC_CHANNEL_1
1067 * @arg @ref LL_DAC_CHANNEL_2 (1)
1068 *
1069 * (1) On this STM32 serie, parameter not available on all devices.
1070 * Refer to device datasheet for channels availability.
1071 * @retval None
1072 */
1073 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1074 {
1075 CLEAR_BIT(DACx->CR,
1076 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1077 }
1078
1079 /**
1080 * @brief Get DAC enable state of the selected channel.
1081 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1082 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1083 * CR EN2 LL_DAC_IsEnabled
1084 * @param DACx DAC instance
1085 * @param DAC_Channel This parameter can be one of the following values:
1086 * @arg @ref LL_DAC_CHANNEL_1
1087 * @arg @ref LL_DAC_CHANNEL_2 (1)
1088 *
1089 * (1) On this STM32 serie, parameter not available on all devices.
1090 * Refer to device datasheet for channels availability.
1091 * @retval State of bit (1 or 0).
1092 */
1093 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1094 {
1095 return (READ_BIT(DACx->CR,
1096 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1097 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1098 }
1099
1100 /**
1101 * @brief Enable DAC trigger of the selected channel.
1102 * @note - If DAC trigger is disabled, DAC conversion is performed
1103 * automatically once the data holding register is updated,
1104 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1105 * @ref LL_DAC_ConvertData12RightAligned(), ...
1106 * - If DAC trigger is enabled, DAC conversion is performed
1107 * only when a hardware of software trigger event is occurring.
1108 * Select trigger source using
1109 * function @ref LL_DAC_SetTriggerSource().
1110 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1111 * CR TEN2 LL_DAC_EnableTrigger
1112 * @param DACx DAC instance
1113 * @param DAC_Channel This parameter can be one of the following values:
1114 * @arg @ref LL_DAC_CHANNEL_1
1115 * @arg @ref LL_DAC_CHANNEL_2 (1)
1116 *
1117 * (1) On this STM32 serie, parameter not available on all devices.
1118 * Refer to device datasheet for channels availability.
1119 * @retval None
1120 */
1121 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1122 {
1123 SET_BIT(DACx->CR,
1124 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1125 }
1126
1127 /**
1128 * @brief Disable DAC trigger of the selected channel.
1129 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1130 * CR TEN2 LL_DAC_DisableTrigger
1131 * @param DACx DAC instance
1132 * @param DAC_Channel This parameter can be one of the following values:
1133 * @arg @ref LL_DAC_CHANNEL_1
1134 * @arg @ref LL_DAC_CHANNEL_2 (1)
1135 *
1136 * (1) On this STM32 serie, parameter not available on all devices.
1137 * Refer to device datasheet for channels availability.
1138 * @retval None
1139 */
1140 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1141 {
1142 CLEAR_BIT(DACx->CR,
1143 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1144 }
1145
1146 /**
1147 * @brief Get DAC trigger state of the selected channel.
1148 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1149 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1150 * CR TEN2 LL_DAC_IsTriggerEnabled
1151 * @param DACx DAC instance
1152 * @param DAC_Channel This parameter can be one of the following values:
1153 * @arg @ref LL_DAC_CHANNEL_1
1154 * @arg @ref LL_DAC_CHANNEL_2 (1)
1155 *
1156 * (1) On this STM32 serie, parameter not available on all devices.
1157 * Refer to device datasheet for channels availability.
1158 * @retval State of bit (1 or 0).
1159 */
1160 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1161 {
1162 return (READ_BIT(DACx->CR,
1163 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1164 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1165 }
1166
1167 /**
1168 * @brief Trig DAC conversion by software for the selected DAC channel.
1169 * @note Preliminarily, DAC trigger must be set to software trigger
1170 * using function @ref LL_DAC_SetTriggerSource()
1171 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1172 * and DAC trigger must be enabled using
1173 * function @ref LL_DAC_EnableTrigger().
1174 * @note For devices featuring DAC with 2 channels: this function
1175 * can perform a SW start of both DAC channels simultaneously.
1176 * Two channels can be selected as parameter.
1177 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1178 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1179 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1180 * @param DACx DAC instance
1181 * @param DAC_Channel This parameter can a combination of the following values:
1182 * @arg @ref LL_DAC_CHANNEL_1
1183 * @arg @ref LL_DAC_CHANNEL_2 (1)
1184 *
1185 * (1) On this STM32 serie, parameter not available on all devices.
1186 * Refer to device datasheet for channels availability.
1187 * @retval None
1188 */
1189 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1190 {
1191 SET_BIT(DACx->SWTRIGR,
1192 (DAC_Channel & DAC_SWTR_CHX_MASK));
1193 }
1194
1195 /**
1196 * @brief Set the data to be loaded in the data holding register
1197 * in format 12 bits left alignment (LSB aligned on bit 0),
1198 * for the selected DAC channel.
1199 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1200 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1201 * @param DACx DAC instance
1202 * @param DAC_Channel This parameter can be one of the following values:
1203 * @arg @ref LL_DAC_CHANNEL_1
1204 * @arg @ref LL_DAC_CHANNEL_2 (1)
1205 *
1206 * (1) On this STM32 serie, parameter not available on all devices.
1207 * Refer to device datasheet for channels availability.
1208 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1209 * @retval None
1210 */
1211 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1212 {
1213 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1214
1215 MODIFY_REG(*preg,
1216 DAC_DHR12R1_DACC1DHR,
1217 Data);
1218 }
1219
1220 /**
1221 * @brief Set the data to be loaded in the data holding register
1222 * in format 12 bits left alignment (MSB aligned on bit 15),
1223 * for the selected DAC channel.
1224 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1225 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1226 * @param DACx DAC instance
1227 * @param DAC_Channel This parameter can be one of the following values:
1228 * @arg @ref LL_DAC_CHANNEL_1
1229 * @arg @ref LL_DAC_CHANNEL_2 (1)
1230 *
1231 * (1) On this STM32 serie, parameter not available on all devices.
1232 * Refer to device datasheet for channels availability.
1233 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1234 * @retval None
1235 */
1236 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1237 {
1238 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1239
1240 MODIFY_REG(*preg,
1241 DAC_DHR12L1_DACC1DHR,
1242 Data);
1243 }
1244
1245 /**
1246 * @brief Set the data to be loaded in the data holding register
1247 * in format 8 bits left alignment (LSB aligned on bit 0),
1248 * for the selected DAC channel.
1249 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1250 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1251 * @param DACx DAC instance
1252 * @param DAC_Channel This parameter can be one of the following values:
1253 * @arg @ref LL_DAC_CHANNEL_1
1254 * @arg @ref LL_DAC_CHANNEL_2 (1)
1255 *
1256 * (1) On this STM32 serie, parameter not available on all devices.
1257 * Refer to device datasheet for channels availability.
1258 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1259 * @retval None
1260 */
1261 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1262 {
1263 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1264
1265 MODIFY_REG(*preg,
1266 DAC_DHR8R1_DACC1DHR,
1267 Data);
1268 }
1269
1270 #if defined(DAC_CHANNEL2_SUPPORT)
1271 /**
1272 * @brief Set the data to be loaded in the data holding register
1273 * in format 12 bits left alignment (LSB aligned on bit 0),
1274 * for both DAC channels.
1275 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1276 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1277 * @param DACx DAC instance
1278 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1279 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1280 * @retval None
1281 */
1282 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1283 {
1284 MODIFY_REG(DACx->DHR12RD,
1285 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1286 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1287 }
1288
1289 /**
1290 * @brief Set the data to be loaded in the data holding register
1291 * in format 12 bits left alignment (MSB aligned on bit 15),
1292 * for both DAC channels.
1293 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1294 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1295 * @param DACx DAC instance
1296 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1297 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1298 * @retval None
1299 */
1300 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1301 {
1302 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1303 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1304 /* the 4 LSB must be taken into account for the shift value. */
1305 MODIFY_REG(DACx->DHR12LD,
1306 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1307 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1308 }
1309
1310 /**
1311 * @brief Set the data to be loaded in the data holding register
1312 * in format 8 bits left alignment (LSB aligned on bit 0),
1313 * for both DAC channels.
1314 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1315 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1316 * @param DACx DAC instance
1317 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1318 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1319 * @retval None
1320 */
1321 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1322 {
1323 MODIFY_REG(DACx->DHR8RD,
1324 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1325 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1326 }
1327
1328 #endif /* DAC_CHANNEL2_SUPPORT */
1329 /**
1330 * @brief Retrieve output data currently generated for the selected DAC channel.
1331 * @note Whatever alignment and resolution settings
1332 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1333 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1334 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1335 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1336 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1337 * @param DACx DAC instance
1338 * @param DAC_Channel This parameter can be one of the following values:
1339 * @arg @ref LL_DAC_CHANNEL_1
1340 * @arg @ref LL_DAC_CHANNEL_2 (1)
1341 *
1342 * (1) On this STM32 serie, parameter not available on all devices.
1343 * Refer to device datasheet for channels availability.
1344 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1345 */
1346 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1347 {
1348 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1349
1350 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1351 }
1352
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1358 * @{
1359 */
1360 /**
1361 * @brief Get DAC underrun flag for DAC channel 1
1362 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1363 * @param DACx DAC instance
1364 * @retval State of bit (1 or 0).
1365 */
1366 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1367 {
1368 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1369 }
1370
1371 #if defined(DAC_CHANNEL2_SUPPORT)
1372 /**
1373 * @brief Get DAC underrun flag for DAC channel 2
1374 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1375 * @param DACx DAC instance
1376 * @retval State of bit (1 or 0).
1377 */
1378 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1379 {
1380 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1381 }
1382 #endif /* DAC_CHANNEL2_SUPPORT */
1383
1384 /**
1385 * @brief Clear DAC underrun flag for DAC channel 1
1386 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1387 * @param DACx DAC instance
1388 * @retval None
1389 */
1390 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1391 {
1392 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1393 }
1394
1395 #if defined(DAC_CHANNEL2_SUPPORT)
1396 /**
1397 * @brief Clear DAC underrun flag for DAC channel 2
1398 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1399 * @param DACx DAC instance
1400 * @retval None
1401 */
1402 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1403 {
1404 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1405 }
1406 #endif /* DAC_CHANNEL2_SUPPORT */
1407
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup DAC_LL_EF_IT_Management IT management
1413 * @{
1414 */
1415
1416 /**
1417 * @brief Enable DMA underrun interrupt for DAC channel 1
1418 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1419 * @param DACx DAC instance
1420 * @retval None
1421 */
1422 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1423 {
1424 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1425 }
1426
1427 #if defined(DAC_CHANNEL2_SUPPORT)
1428 /**
1429 * @brief Enable DMA underrun interrupt for DAC channel 2
1430 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1431 * @param DACx DAC instance
1432 * @retval None
1433 */
1434 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1435 {
1436 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1437 }
1438 #endif /* DAC_CHANNEL2_SUPPORT */
1439
1440 /**
1441 * @brief Disable DMA underrun interrupt for DAC channel 1
1442 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1443 * @param DACx DAC instance
1444 * @retval None
1445 */
1446 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1447 {
1448 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1449 }
1450
1451 #if defined(DAC_CHANNEL2_SUPPORT)
1452 /**
1453 * @brief Disable DMA underrun interrupt for DAC channel 2
1454 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1455 * @param DACx DAC instance
1456 * @retval None
1457 */
1458 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1459 {
1460 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1461 }
1462 #endif /* DAC_CHANNEL2_SUPPORT */
1463
1464 /**
1465 * @brief Get DMA underrun interrupt for DAC channel 1
1466 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1467 * @param DACx DAC instance
1468 * @retval State of bit (1 or 0).
1469 */
1470 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1471 {
1472 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1473 }
1474
1475 #if defined(DAC_CHANNEL2_SUPPORT)
1476 /**
1477 * @brief Get DMA underrun interrupt for DAC channel 2
1478 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1479 * @param DACx DAC instance
1480 * @retval State of bit (1 or 0).
1481 */
1482 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1483 {
1484 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1485 }
1486 #endif /* DAC_CHANNEL2_SUPPORT */
1487
1488 /**
1489 * @}
1490 */
1491
1492 #if defined(USE_FULL_LL_DRIVER)
1493 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1494 * @{
1495 */
1496
1497 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1498 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1499 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1500
1501 /**
1502 * @}
1503 */
1504 #endif /* USE_FULL_LL_DRIVER */
1505
1506 /**
1507 * @}
1508 */
1509
1510 /**
1511 * @}
1512 */
1513
1514 #endif /* DAC1 || DAC2 */
1515
1516 /**
1517 * @}
1518 */
1519
1520 #ifdef __cplusplus
1521 }
1522 #endif
1523
1524 #endif /* __STM32F3xx_LL_DAC_H */
1525
1526 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/